diff --git a/specification/ch_4.xml b/specification/ch_4.xml
index 5ecf5d7..6b5be70 100644
--- a/specification/ch_4.xml
+++ b/specification/ch_4.xml
@@ -565,42 +565,51 @@ int main(int argc, char *argv[ ], char *envp[ ], ElfW(auxv_t) *auxvec)
+AT_EXECFN 31 /* File name of executable */
+AT_SYSINFO_EHDR 33 /* In many architectures, the kernel
+ provides a virtual dynamic shared
+ object (VDSO) that contains a function
+ callable from the user state.
+ AT_SYSINFO_EHDR is the address of the
+ VDSO header that is used by the
+ dynamic linker to resolve function
+ symbols with the VDSO. */
+AT_L1I_CACHESIZE 40 /* Cache sizes and geometries. */
+AT_L1I_CACHEGEOMETRY 41
+AT_L1D_CACHESIZE 42
+AT_L1D_CACHEGEOMETRY 43
+AT_L2_CACHESIZE 44
+AT_L2_CACHEGEOMETRY 45
+AT_L3_CACHESIZE 46
+AT_L3_CACHEGEOMETRY 47
+
AT_NULL
The auxiliary vector has no fixed length; instead an entry of this
type denotes the end of the vector. The corresponding value of a_un is
@@ -710,6 +719,31 @@ PPC_FEATURE2_HAS_IEEE128 0x00400000 /* VSX IEEE Binary Float 128-bit */
+ AT_L1I_CACHESIZE
+ The size of the level-1 instruction cache, in bytes.
+ AT_L1I_CACHEGEOMETRY
+ The geometry of the level-1 instruction cache. The low-order
+ sixteen bits contain the cache associativity as a value N, where
+ N = 1 represents a direct-mapped cache, N = 0xffff represents a
+ fully associative cache, and any other N represents an N-way
+ set-associative cache. The next higher-order sixteen bits contain
+ the size of the cache line in bytes. Note that the cache line
+ size is not necessarily the same as the cache block size.
+ AT_L1D_CACHESIZE
+ The size of the level-1 data cache, in bytes.
+ AT_L1D_CACHEGEOMETRY
+ The geometry of the level-1 data cache, defined in the same
+ manner as for AT_L1I_CACHEGEOMETRY.
+ AT_L2_CACHESIZE
+ The size of the level-2 cache, in bytes.
+ AT_L2_CACHEGEOMETRY
+ The geometry of the level-2 cache, defined in the same
+ manner as for AT_L1I_CACHEGEOMETRY.
+ AT_L3_CACHESIZE
+ The size of the level-3 cache, in bytes.
+ AT_L3_CACHEGEOMETRY
+ The geometry of the level-3 cache, defined in the same
+ manner as for AT_L1I_CACHEGEOMETRY.