diff --git a/specification/app_a.xml b/specification/app_a.xml index 0013b34..812b8dc 100644 --- a/specification/app_a.xml +++ b/specification/app_a.xml @@ -2323,7 +2323,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> approximationestimate of the value of the corresponding element of ARG1 divided by 2 to the power of ARG2, which should - be in the range 0 - 31. + be in the range 0–31. @@ -2355,7 +2355,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> signed-integer value, truncated towards zero, obtained by multiplying the corresponding element of ARG1 by 2 to the power - of ARG2, which should be in the range 0 - 31. + of ARG2, which should be in the range 0–31. @@ -2378,7 +2378,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> unsigned-integer value, truncated towards zero, obtained by multiplying the corresponding element of ARG1 by 2 to the power - of ARG2, which should be in the range 0 - 31. + of ARG2, which should be in the range 0–31. @@ -2950,7 +2950,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> - VEC_EXTRACT_FP32-_FROM_SHORTH (ARG1) + VEC_EXTRACT_FP32_ FROM_SHORTH (ARG1) POWER ISA 3.0 @@ -2977,7 +2977,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> - VEC_EXTRACT_FP32-_FROM_SHORTL (ARG1) + VEC_EXTRACT_FP32_ FROM_SHORTL (ARG1) POWER ISA 3.0 @@ -3050,8 +3050,8 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> Result value: The first doubleword element of the result contains the zero-extended extracted word from ARG1. The second doubleword is - set to 0. ARG2 specifies the least-significant byte number (0 - - 12) of the word to be extracted. + set to 0. ARG2 specifies the least-significant byte number + (0–12) of the word to be extracted. @@ -3790,7 +3790,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> Result value: The first doubleword element of the result contains the zero-extended extracted word from ARG1. The second doubleword is - set to 0. ARG2 specifies the least-significant byte (0 - 12) of + set to 0. ARG2 specifies the least-significant byte (0–12) of the extracted word. @@ -4723,7 +4723,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> beginning with 0. If ARG1 is a vector signed char or a vector unsigned char vector, then let m be 4. Otherwise, let m be 2. For each element n of the result vector, the value is obtained in the - following way: For p = mn to mn+m-1, multiply element p of ARG1 + following way: For p = mn to mn + m – 1, multiply element p of ARG1 by element p of ARG2. Add the sum of these products to element n of ARG3. All additions are performed using 32-bit modular arithmetic. @@ -5353,8 +5353,8 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> Result value: The value of each element of the result is the product of the corresponding elements of ARG1 and ARG2, added to the - corresponding elements of ARG3, and then multiplied by - -1.0. + corresponding elements of ARG3, then multiplied by + –1.0. @@ -5387,7 +5387,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> The value of each element of the result is the product of the corresponding elements of ARG1 and ARG2, subtracted from the corresponding element of ARG3, and then multiplied by - -1.0. + –1.0. @@ -6408,8 +6408,8 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> Applies a permute and exclusive-OR operation on two vectors of byte elements. Result value: - For each i (0 ≤ i < 16), let index1 be bits 0 - 3 and - index2 be bits 4 - 7 of byte element i of mask ARG3. + For each i (0 ≤ i < 16), let index1 be bits 0–3 and + index2 be bits 4–7 of byte element i of mask ARG3. Byte element i of the result is set to the exclusive-OR of byte elements index1 of ARG1 and index2 of ARG2. @@ -7696,8 +7696,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> Result value: The result is the most-significant 16 bytes obtained by concatenating ARG1 and ARG2 and shifting left by the number of - bytes specified by ARG3, which should be in the range 0 - - 15. + bytes specified by ARG3, which should be in the range 0–15. @@ -7852,7 +7851,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> element of the concatenated vectors ARG1 and ARG2, with the word offset to its right1 specified by ARG3, which should be in the - range 0 - 3. + range 0–3. 1A shift left picks values from the right. @@ -8978,7 +8977,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> (octets). Result value: The result is the contents of ARG1, shifted right by the - number of bytes specified by bits 121 - 124 of ARG2. The bits + number of bytes specified by bits 121–124 of ARG2. The bits that are shifted out are replaced by zeros. @@ -9178,16 +9177,19 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> Result value: For each integer 1 ≤ i - ≤ 15, let X - i be the halfword formed by concatenating - elements i and i+1 of ARG1. Let X - 0 be the halfword formed by concatenating a - zero byte with element 0 of ARG1. Let S - i be the value in the three least-significant + ≤ 15, let + Xi + be the halfword formed by concatenating + elements i and i + 1 of ARG1. Let + X0 + be the halfword formed by concatenating a + zero byte with element 0 of ARG1. Let + Si + be the value in the three least-significant bits of element i of ARG2. Then element i of the result vector - contains the value formed from bits 8 - S - i through 15 - S - i. + contains the value formed from bits 8 – + Si through 15 – + Si. @@ -9588,7 +9590,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> beginning with 0. If ARG1 is a vector signed char vector or a vector unsigned char vector, then let m be 4. Otherwise, let m be 2. For each element n of the result vector, the value is obtained - by adding elements mn through mn+m-1 of ARG1 and element n of + by adding elements mn through mn + m – 1 of ARG1 and element n of ARG2 using saturated addition. @@ -10351,7 +10353,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> At least 0 and at most 16 bytes will be loaded. The length is specified by the least-significant byte of ARG2, as min (mod (ARG2, 256), 16). The behavior is undefined if the length - argument is outside of the range 0 - 255, or if it is not a + argument is outside of the range 0–255, or if it is not a multiple of the vector element size. @@ -10488,7 +10490,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> At least 0 and at most 16 bytes will be loaded. The length is specified by the least-significant byte of ARG2, as min (mod (ARG2, 256), 16). The behavior is undefined if the length - argument is outside of the range 0 - 255, or if it is not a + argument is outside of the range 0–255, or if it is not a multiple of the vector element size. @@ -10934,7 +10936,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> At least 0 and at most 16 bytes will be stored. The length is specified by the least-significant byte of ARG3, as min (mod (ARG3, 256), 16). The behavior is undefined if the length - argument is outside of the range 0 - 255, or if it is not a + argument is outside of the range 0–255, or if it is not a multiple of the vector element size. @@ -11069,7 +11071,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> At least 0 and at most 16 bytes will be stored. The length is specified by the least-significant byte of ARG3, as min (mod (ARG2, 256), 16). The behavior is undefined if the length - argument is outside of the range 0 - 255, or if it is not a + argument is outside of the range 0–255, or if it is not a multiple of the vector element size. diff --git a/specification/app_b.xml b/specification/app_b.xml index 19a7662..73154f6 100644 --- a/specification/app_b.xml +++ b/specification/app_b.xml @@ -17,8 +17,8 @@ xml:id="dbdoclet.50655245_pgfId-1450875" revisionflag="added"> Binary-coded decimal (BCD) values are compressed; each decimal digit and sign bit occupies 4 bits. Digits are ordered right-to-left in the order of significance. The final 4 bits encode the sign. A valid encoding must - have a value in the range 0 - 9 in each of its 31 digits, and a value in - the range 10 - 15 for the sign field. + have a value in the range 0–9 in each of its 31 digits, and a value in + the range 10–15 for the sign field. Source operands with sign codes of 0b1010, 0b1100, 0b1110, or 0b1111 are interpreted as positive values. Source operands with sign codes of 0b1011 or 0b1101 are interpreted as negative values. @@ -27,7 +27,7 @@ xml:id="dbdoclet.50655245_pgfId-1450875" revisionflag="added"> indicate positive values or zero, depending on the value of the positive sign (PS) bit. These built-in functions can operate on values of at most 31 digits. - BCD values are stored in memory as contiguous arrays of 1 - 16 + BCD values are stored in memory as contiguous arrays of 1–16 bytes. BCD built-in functions are valid only when -march or diff --git a/specification/bk_main.xml b/specification/bk_main.xml index ab47d6f..837da9b 100644 --- a/specification/bk_main.xml +++ b/specification/bk_main.xml @@ -98,7 +98,7 @@ - Revision 1.2b - initial conversion from framemaker + Revision 1.3b: initial conversion from framemaker @@ -108,7 +108,18 @@ - Version 1.2 - POWER8 erratum and POWER9 support. + Version 1.3: POWER9 support. + + + + + + + 2016-06-13 + + + + Version 1.2: POWER8 errata. @@ -119,7 +130,7 @@ - Version 1.1 - initial conversion from framemaker + Version 1.1: Incorporate errata. diff --git a/specification/ch_1.xml b/specification/ch_1.xml index 53ea7a8..88bcd27 100644 --- a/specification/ch_1.xml +++ b/specification/ch_1.xml @@ -99,8 +99,8 @@ - ISO/IEC TR 24732:2009 - Programming languages, their - environments and system software interfaces - Extension for the + ISO/IEC TR 24732:2009 – Programming languages, their + environments and system software interfaces – Extension for the programming language C to support decimal floating-point arithmetic, ISO/IEC, January 05, 2009. Available from ISO. diff --git a/specification/ch_2.xml b/specification/ch_2.xml index de87811..b674c86 100644 --- a/specification/ch_2.xml +++ b/specification/ch_2.xml @@ -2042,7 +2042,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> FPSCR Formats: As of Power ISA version 2.05, the FPSCR is extended from 32 bits to 64 bits. The fields of the original - 32-bit FPSCR are now held in bits 32 - 63 of the 64-bit FPSCR. The + 32-bit FPSCR are now held in bits 32–63 of the 64-bit FPSCR. The assembly instructions that operate upon the 64-bit FPSCR have either a W instruction field added to select the operative word for the instruction (for example, @@ -2558,7 +2558,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> Vector of 16 bytes with a value of either 0 or - 28- 1. + 28 – 1. @@ -2610,7 +2610,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> Vector of 8 halfwords with a value of either 0 or - 216- 1. + 216 – 1. @@ -2662,7 +2662,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> Vector of 4 words with a value of either 0 or - 232- 1. + 232 – 1. @@ -2721,7 +2721,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> Vector of 2 doublewords with a value of either 0 or - 264- 1. + 264 – 1. @@ -3147,7 +3147,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> IBM EXTENDED PRECISION form provides the same range as double - precision (about 10-308 to + precision (about 10–308 to 10308) but more precision (a variable amount, about 31 decimal digits or more). @@ -3328,9 +3328,9 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> union where the number of bits in the bit field is specified. In , a signed range goes from - -2w - 1 to - 2w - 1- 1 and an unsigned range goes from 0 to - 2w- 1. + –2w – 1 to + 2w – 1 – 1 and an unsigned range goes from 0 to + 2w – 1. Bit Field Types @@ -3365,7 +3365,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> signed char - 1 - 8 + 1–8 @@ -3378,7 +3378,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> signed short - 1 - 16 + 1–16 @@ -3391,7 +3391,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> signed int - 1 - 32 + 1–32 @@ -3409,7 +3409,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> signed long - 1 - 64 + 1–64 @@ -3432,7 +3432,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> signed __int128 - 1 - 128 + 1–128 @@ -4235,7 +4235,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> - r3 - r10 + r3–r10 Volatile @@ -4284,7 +4284,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> - r14 - r31 + r14–r31 If a function needs a frame pointer, assigning r31 to the role of the frame pointer is recommended. @@ -4343,7 +4343,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> - CR0 - CR1 + CR0–CR1 Volatile @@ -4354,7 +4354,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> - CR2 - CR4 + CR2–CR4 Nonvolatile @@ -4365,7 +4365,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> - CR5 - CR7 + CR5–CR7 Volatile @@ -4559,7 +4559,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> number, to refer to floating-point register N. For the purpose of function calls, the right half of VSX registers, corresponding to the classic floating-point registers (that - is, vsr0 - vsr31), is volatile. + is, vsr0–vsr31), is volatile.
Floating-Point Register Roles for Binary Floating-Point @@ -4601,7 +4601,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> </row> <row> <entry> - <para>f1 - f13</para> + <para>f1–f13</para> </entry> <entry> <para>Volatile</para> @@ -4613,7 +4613,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> </row> <row> <entry> - <para>f14 - f31</para> + <para>f14–f31</para> </entry> <entry> <para>Nonvolatile</para> @@ -4755,7 +4755,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> <tbody> <row> <entry> - <para>v0 - v1</para> + <para>v0–v1</para> </entry> <entry> <para>Volatile</para> @@ -4766,7 +4766,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> </row> <row> <entry> - <para>v2 - v13</para> + <para>v2–v13</para> </entry> <entry> <para>Volatile</para> @@ -4777,7 +4777,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> </row> <row> <entry> - <para>v14 - v19</para> + <para>v14–v19</para> </entry> <entry> <para>Volatile</para> @@ -4788,7 +4788,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> </row> <row> <entry> - <para>v20 - v31</para> + <para>v20–v31</para> </entry> <entry> <para>Nonvolatile</para> @@ -5198,7 +5198,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> general-purpose register save and restore functions are to be used, the general-purpose registers shall be saved in a contiguous range. General-purpose register rN is saved in the doubleword located 8 x - (32-N) bytes before the back-chain word of the previous frame, as shown + (32 – N) bytes before the back-chain word of the previous frame, as shown in <xref linkend="dbdoclet.50655240_97610" />.</para> <para>The General-Purpose Register Save Area is always doubleword @@ -5215,7 +5215,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> saved in arbitrary locations in the stack frame. If the system vector register save and restore functions are to be used, the vector registers shall be saved in a contiguous range. Vector register vN is - saved in the doubleword located 16 x (32-N) bytes before the + saved in the doubleword located 16 x (32 – N) bytes before the General-Purpose Register Save Areas plus alignment padding, as shown in <xref linkend="dbdoclet.50655240_97610" />.</para> @@ -5299,7 +5299,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> to the memory location of the next parameter. Therefore, regardless of type, variable arguments must always be in the same location so that they can be found at runtime. The first 8 doublewords are located in - general registers r3 - r10. Any additional doublewords are located in + general registers r3–r10. Any additional doublewords are located in the stack Parameter Save Area. Alignment requirements such as those for vector types may require the va_list pointer to first be aligned before accessing a value.</para> @@ -5469,25 +5469,24 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> <itemizedlist> <listitem> <para>Up to eight arguments can be passed in general-purpose - registers r3 - r10.</para> + registers r3–r10.</para> </listitem> <listitem> <para>Up to thirteen qualified floating-point arguments can be passed - in floating-point registers f1 - f13 or up to twelve in vector - registers v2 - v13.</para> + in floating-point registers f1–f13 or up to twelve in vector + registers v2–v13.</para> </listitem> <listitem> <para>Up to thirteen single-precision or double-precision decimal - floating-point arguments can be passed in floating-point registers f1 - - f13.</para> + floating-point arguments can be passed in floating-point registers + f1–f13.</para> </listitem> <listitem> <para>Up to six quad-precision decimal floating-point arguments can - be passed in even-odd floating-point register pairs f2 - f13.</para> + be passed in even-odd floating-point register pairs f2–f13.</para> </listitem> <listitem> - <para>Up to 12 qualified vector arguments can be passed in v2 - - v13.</para> + <para>Up to 12 qualified vector arguments can be passed in v2–v13.</para> </listitem> </itemizedlist> <para>A qualified floating-point argument corresponds to:</para> @@ -5595,7 +5594,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> <bridgehead>IEEE BINARY 128 EXTENDED PRECISION</bridgehead> <itemizedlist mark="none"> <listitem> - <para>Up to 12 quad-precision parameters can be passed in v2 - v13. + <para>Up to 12 quad-precision parameters can be passed in v2–v13. For the purpose of determining qualified floating-point and vector arguments, an IEEE 128b type shall be considered a "like" vector type, and a complex _Float128 shall be treated as two individual @@ -5620,7 +5619,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> frame. When this happens, only the minimum storage needed to contain all arguments (including allocating space for parameters passed in registers) needs to be allocated in the stack frame.</para> - <para>General-purpose registers r3 - r10 correspond to the allocation of + <para>General-purpose registers r3–r10 correspond to the allocation of parameters to the first 8 doublewords of the Parameter Save Areah. Specifically, this requires a suitable number of general-purpose registers to be skipped to correspond to parameters passed in @@ -5695,7 +5694,7 @@ unnamed parameter: goto mem_argument size = size_in_DW(argument) - reg_size = min(size, 11-gr) + reg_size = min(size, 11 – gr) pass (GPR, gr, first_n_DW (argument, reg_size)); if remaining_members @@ -5720,7 +5719,7 @@ aggregate: goto use_vrs; n_fregs = n_fregs_for_type(member_type(argument,0)) agg_size = members(argument) * n_fregs - reg_size = min(agg_size, 15-fr) + reg_size = min(agg_size, 15 – fr) pass(FPR,fr,first_n_DW(argument,reg_size) fr += reg_size; gr += size_in_DW (first_n_DW(argument,reg_size)) @@ -5734,7 +5733,7 @@ aggregate: if (homogeneous(argument,vector) and members(argument) <= 8) use_vrs: agg_size = members(argument) - reg_size = min(agg_size, 14-vr) + reg_size = min(agg_size, 14 – vr) if (gr&1 = 0) // align vector in memory gr++ pass(VR,vr,first_n_elements(argument,reg_size); @@ -5752,7 +5751,7 @@ aggregate: size = size_in_DW(argument) gpr_struct: - reg_size = min(size, 11-gr) + reg_size = min(size, 11 – gr) pass (GPR, gr, first_n_DW (argument, reg_size)); gr += size_in_DW (first_n_DW (argument, reg_size)) @@ -5855,15 +5854,15 @@ double ff, gg, hh; x = func(c, ff, d, ld, s, gg, t, e, hh); Parameter Register Offset in parameter save area -c r3 0-7 (not stored in parameter save area) -ff f1 8-15 (not stored) -d r5 16-23 (not stored) -ld f2,f3 24-39 (not stored) -s r8,r9 40-55 (not stored) -gg f4 56-63 (not stored) -t (none) 64-79 (stored in parameter save area) -e (none) 80-87 (stored) -hh f5 88-95 (not stored)</programlisting> +c r3 0–7 (not stored in parameter save area) +ff f1 8–15 (not stored) +d r5 16–23 (not stored) +ld f2,f3 24–39 (not stored) +s r8,r9 40–55 (not stored) +gg f4 56–63 (not stored) +t (none) 64–79 (stored in parameter save area) +e (none) 80–87 (stored) +hh f5 88–95 (not stored)</programlisting> </figure> <note> <para>If a prototype is not in scope:</para> @@ -6505,7 +6504,7 @@ or r0, r0, r1</programlisting> functions:</para> <itemizedlist> <listitem> - <para>Restore all registers and liminted-acces bits that wee saved + <para>Restore all registers and limited-access bits that we saved by the function's prologue.</para> </listitem> <listitem> @@ -6631,13 +6630,13 @@ or r0, r0, r1</programlisting> <section xml:id="dbdoclet.50655240_41483"> <title>GPR Save and Restore FunctionsEach _savegpr0_N routine saves the general registers from - rN- r31, inclusive. Each routine also saves the LR. + rN–r31, inclusive. Each routine also saves the LR. The stack frame must not have been allocated yet. When the routine is called, r1 contains the address of the word immediately beyond the end of the general register save area, and r0 must contain the value of the LR on function entry.The _restgpr0_N routines restore the general registers from - rN- r31, and then return to their caller's caller. + rN–r31, and then return to their caller's caller. The caller's stack frame must already have been deallocated. When the routine is called, r1 contains the address of the word immediately beyond the end of the general register save area, and the LR must @@ -6691,11 +6690,11 @@ or r0, r0, r1 ld r31,-8(r1) mtlr r0 blr - Each _savegpr1_N routine saves the general registers from rN - - r31, inclusive. When the routine is called, r12 contains the address of + Each _savegpr1_N routine saves the general registers from + rN–r31, inclusive. When the routine is called, r12 contains the address of the word just beyond the end of the general register save area. - The _restgpr1_N routines restore the general registers from rN - - r31. When the routine is called, r12 contains the address of the word + The _restgpr1_N routines restore the general registers from + rN–r31. When the routine is called, r12 contains the address of the word just beyond the end of the general register save area, superseding the normal use of r12 on a call. A sample implementation of _savegpr1_N and _restgpr1_N @@ -6743,13 +6742,13 @@ or r0, r0, r1
FPR Save and Restore Functions Each _savefpr_N routine saves the floating-point registers from - fN- f31, inclusive. When the routine is called, r1 + fN–f31, inclusive. When the routine is called, r1 contains the address of the word immediately beyond the end of the Floating-Point Register Save Area, which means that the stack frame must not have been allocated yet. Register r0 must contain the value of the LR on function entry. The _restfpr_N routines restore the floating-point registers - from fN- f31, inclusive. When the routine is called, r1 + from fN–f31, inclusive. When the routine is called, r1 contains the address of the word immediately beyond the end of the Floating-Point Register Save Area, which means that the stack frame must not have been allocated yet. @@ -6810,7 +6809,7 @@ or r0, r0, r1
Vector Save and Restore Functions - Each _savevr_M routine saves the vector registers from vM - v31 + Each _savevr_M routine saves the vector registers from vM–v31 inclusive. @@ -6821,7 +6820,7 @@ or r0, r0, r1 this function, r0 contains the address of the word just beyond the end of the Vector Register Save Area. The routines leave r0 undisturbed. They modify the value of r12. - The _restvr_M routines restore the vector registers from vM - v31 + The _restvr_M routines restore the vector registers from vM–v31 inclusive. On entry to this function, r0 contains the address of the word just beyond the end of the Vector Register Save Area. The routines leave r0 undisturbed. They modify the value of r12. The following code @@ -8080,9 +8079,9 @@ addi r3,r1,p ; R3 = new data area following parameter save area.. All instances of the Power Architecture use the mapping shown in for encoding registers into - DWARF. DWARF register numbers 32 - 63 and 77 - 108 are also used to - indicate the location of variables in VSX registers vsr0 - vsr31 and vsr32 - - vsr63, respectively, in DWARF debug information. + DWARF. DWARF register numbers 32–63 and 77–108 are also used to + indicate the location of variables in VSX registers vsr0–vsr31 and + vsr32–vsr63, respectively, in DWARF debug information.
Mappings of Common Registers @@ -8121,10 +8120,10 @@ addi r3,r1,p ; R3 = new data area following parameter save area.Reg - 0 - 31 + 0–31 - r0 - r31 + r0–r31 8 @@ -8135,10 +8134,10 @@ addi r3,r1,p ; R3 = new data area following parameter save area.Reg - 32 - 63 + 32–63 - f0 - f31 + f0–f31 8 @@ -8205,10 +8204,10 @@ addi r3,r1,p ; R3 = new data area following parameter save area.Reg - 68 - 75 + 68–75 - cr0 - cr7 + cr0–cr7 0.5 @@ -8237,10 +8236,10 @@ addi r3,r1,p ; R3 = new data area following parameter save area.Reg - 77 - 108 + 77–108 - vr0 - vr31 + vr0–vr31 16 diff --git a/specification/ch_3.xml b/specification/ch_3.xml index b737dbc..5845481 100644 --- a/specification/ch_3.xml +++ b/specification/ch_3.xml @@ -454,7 +454,7 @@ my_func: Functions called via symbols with an st_other value of 0 may be called without a valid TOC pointer in r2. Symbols of functions that require a local entry with a valid TOC pointer should generate a symbol - with an st_other field value of 2 - 6 and both local and global entry + with an st_other field value of 2–6 and both local and global entry points, even if the global entry point will not be used. (In such a case, the instructions of the global entry setup sequence may optionally be initialized with TRAP instructions.) @@ -716,7 +716,7 @@ my_func: In the following figure, word30 specifies a 30-bit field taking up - bits 0 - 29 of a word and maintaining 4-byte alignment unless otherwise + bits 0–29 of a word and maintaining 4-byte alignment unless otherwise indicated. @@ -965,7 +965,7 @@ my_func: In the following figure, low24 specifies a 24-bit field taking up - bits 6 - 29 of a word and maintaining 4-byte alignment. The other bits + bits 6–29 of a word and maintaining 4-byte alignment. The other bits remain unchanged. A call or unconditional branch instruction is an example of this field. @@ -1517,7 +1517,7 @@ my_func: In the following figure, low14 specifies a 14-bit field taking up - bits 16 - 29 and possibly bit 10 (the branch prediction bit) of a word + bits 16–29 and possibly bit 10 (the branch prediction bit) of a word and maintaining 4-byte alignment. The other bits remain unchanged. A conditional branch instruction is an example usage. @@ -2202,7 +2202,7 @@ my_func: - - + – Denotes 64-bit modulus subtraction. @@ -2231,7 +2231,7 @@ my_func: #hi(value) - Denotes bits 16 - 63 of the indicated value. That + Denotes bits 16–63 of the indicated value. That is: #hi(x) = x >> 16 @@ -2241,7 +2241,7 @@ my_func: #ha(value) - Denotes the high adjusted value: bits 16 - 63 of the + Denotes the high adjusted value: bits 16–63 of the indicated value, compensating for #lo( ) being treated as a signed number. That is: #ha(x) = (x + 0x8000) >> 16 @@ -2282,7 +2282,7 @@ my_func: Represents the base address of the TCB. - tcb = (tp - (TLS_TP_OFFSET + TCB_LENGTH)) + tcb = (tp – (TLS_TP_OFFSET + TCB_LENGTH)) @@ -2396,8 +2396,8 @@ my_func: fit in the allocated bits. - Relocations that refer to half16ds (56 - 66, 87 - 88, 91 - 92, - 95 - 96, and 101 - 102) are to be used to direct the linker to look + Relocations that refer to half16ds (56–66, 87–88, 91–92, + 95–96, and 101–102) are to be used to direct the linker to look at the underlying instruction and treat the field as a DS or DQ field. ABI-compliant tools should give an error for attempts to relocate an address to a value that is not divisible by 4. @@ -2571,7 +2571,7 @@ my_func: low24* - (S + A - P) >> 2 + (S + A – P) >> 2 @@ -2585,7 +2585,7 @@ my_func: low14* - (S + A - P) >> 2 + (S + A – P) >> 2 @@ -2741,7 +2741,7 @@ my_func: word32* - S + A - P + S + A – P @@ -2769,7 +2769,7 @@ my_func: word32* - L - P + L – P @@ -2881,7 +2881,7 @@ my_func: word30 - (S + A - P) >> 2 + (S + A – P) >> 2 @@ -2979,7 +2979,7 @@ my_func: doubleword64 - S + A - P + S + A – P @@ -3007,7 +3007,7 @@ my_func: doubleword64 - L - P + L – P @@ -3021,7 +3021,7 @@ my_func: half16* - S + A - .TOC. + S + A – .TOC. @@ -3035,7 +3035,7 @@ my_func: half16 - #lo(S + A - .TOC.) + #lo(S + A – .TOC.) @@ -3049,7 +3049,7 @@ my_func: half16* - #hi(S + A - .TOC.) + #hi(S + A – .TOC.) @@ -3063,7 +3063,7 @@ my_func: half16* - #ha(S + A - .TOC.) + #ha(S + A – .TOC.) @@ -3245,7 +3245,7 @@ my_func: half16ds* - (S + A - .TOC.) >> 2 + (S + A – .TOC.) >> 2 @@ -3259,7 +3259,7 @@ my_func: half16ds - #lo(S + A - .TOC.) >> 2 + #lo(S + A – .TOC.) >> 2 @@ -3987,7 +3987,7 @@ my_func: low24* - (S + A - P) >> 2 + (S + A – P) >> 2 @@ -4031,7 +4031,7 @@ my_func: half16* - S + A - P + S + A – P @@ -4045,7 +4045,7 @@ my_func: half16 - #lo(S + A - P) + #lo(S + A – P) @@ -4059,7 +4059,7 @@ my_func: half16* - #hi(S + A - P) + #hi(S + A – P) @@ -4073,7 +4073,7 @@ my_func: half16* - #ha(S + A - P) + #ha(S + A – P) @@ -4212,11 +4212,11 @@ ld r3,x@got@l(r3) the high adjusted, high, and low parts of the GOT offset. (For an explanation of the meaning of “high adjusted,” see ). SYMBOL@got@ha corresponds to - bits 32 - 63 of the offset within the global offset table with adjustment + bits 32–63 of the offset within the global offset table with adjustment for the sign extension of the low-order offset bits. SYMBOL@got@l corresponds to the 16 low-order bits of the offset within the global offset table. - The syntax SYMBOL@toc refers to the value (SYMBOL - .TOC.), where + The syntax SYMBOL@toc refers to the value (SYMBOL – .TOC.), where .TOC. represents the TOC base for the current object file. This provides the address of the variable whose name is SYMBOL as an offset from the TOC base. @@ -4433,8 +4433,8 @@ addi r4, r4, lower the TLS blocks for these are created consecutively and immediately follow the TCB. The offset of the TLS block of an initially available module from the TCB remains fixed after program start. - The tlsoffset(m) values for a module with index m, where m ranges 1 - - M, M being the total number of modules, are computed as follows: + The tlsoffset(m) values for a module with index m, where m ranges + from 1–M, M being the total number of modules, are computed as follows: tlsoffset(1) = round(16, align(1)) tlsoffset(m + 1) = round(tlsoffset(m) + tlssize(m), align(m + 1)) @@ -4447,8 +4447,8 @@ tlsoffset(m + 1) = round(tlsoffset(m) + tlssize(m), align(m + 1)) The function ceiling( ) returns the smallest integer greater - than or equal to its argument, where n is an integer satisfying: n - - 1 < x ≤ n: + than or equal to its argument, where n is an integer satisfying: + n – 1 < x ≤ n: ceiling(x) = n @@ -4467,7 +4467,8 @@ tlsoffset(m + 1) = round(tlsoffset(m) + tlssize(m), align(m + 1)) The thread pointer (TP) is held in r13 and is used to access the TCB. The TP is initialized to point 0x7000 bytes past the end of the TCB. - The TP offset allows for efficient addressing of the TCB and up to 4 KB - + The TP offset allows for efficient addressing of the TCB and up to 4 KB + – 8 B of other thread library information (placed before the TCB). shows the region of memory @@ -6861,8 +6862,8 @@ nop - The codes 0xf - 0xfa are reserved. The codes - 0xfb - 0xff are reserved for IBM. + The codes 0xf–0xfa are reserved. The codes + 0xfb–0xff are reserved for IBM. diff --git a/specification/ch_6.xml b/specification/ch_6.xml index 02cc5d7..18dcfdc 100644 --- a/specification/ch_6.xml +++ b/specification/ch_6.xml @@ -42,10 +42,10 @@ xml:id="dbdoclet.50655244_pgfId-1095944"> vector elements at a time in 128-bit registers. On a big-endian POWER platform, vector elements are loaded from memory into a register so that the 0th element occupies the high-order bits of the register, and the - (N-1)th element occupies the low-order bits of the register. This is + (N – 1)th element occupies the low-order bits of the register. This is referred to as big-endian element order. On a little-endian POWER platform, vector elements are loaded from memory such that the 0th element occupies - the low-order bits of the register, and the (N-1)th element occupies the + the low-order bits of the register, and the (N – 1)th element occupies the high-order bits. This is referred to as little-endian element order.
Vector Data Types @@ -102,7 +102,7 @@ register vector double vd = vec_splats(*double_ptr); pointers; these operators are also valid for pointers to vector types. The traditional C/C++ operators are defined on vector types with “do - all” semantics for unary and binary +, unary and binary -, binary *, binary + all” semantics for unary and binary +, unary and binary –, binary *, binary %, and binary / as well as the unary and binary logical and comparison operators. For unary operators, the specified operation is performed on the @@ -497,7 +497,7 @@ register vector double vd = vec_splats(*double_ptr); vspltb, vsplth, vspltw - Subtract the element number from N-1 for LE. + Subtract the element number from N – 1 for LE. @@ -557,7 +557,7 @@ register vector double vd = vec_splats(*double_ptr); For LE, the bytes are loaded left justified then shifted - right 16-cnt bytes or rotated left cnt bytes. Let “cnt” be the + right 16 – cnt bytes or rotated left cnt bytes. Let “cnt” be the number of bytes specified to be loaded by vec_xl_len_r. @@ -569,7 +569,7 @@ register vector double vd = vec_splats(*double_ptr); - For LE, the bytes are shifted left 16-cnt bytes or rotated + For LE, the bytes are shifted left 16 – cnt bytes or rotated right cnt bytes so they are left justified to be stored. Let “cnt” be the number of bytes specified to be stored by vec_xst_len_r.