diff --git a/specification/app_a.xml b/specification/app_a.xml index 6c6b5a1..504eb41 100644 --- a/specification/app_a.xml +++ b/specification/app_a.xml @@ -6768,7 +6768,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> The value of each element is set to the value of an input element of the concatenated vectors ARG1 and ARG2, with the word offset to its right - 1 specified by ARG3, which should be in the + 1 specified by ARG3, which should be in the range 0 - 3. 1. A shift left picks values from the right. @@ -6957,7 +6957,7 @@ xml:id="dbdoclet.50655245_pgfId-1138128"> The result is the contents of ARG1, shifted left by the number of bytes specified by the most-significant nibble of the least-significant byte - 1 of ARG2. The bits that are shifted out are + 1 of ARG2. The bits that are shifted out are replaced by zeros. 1. That is, by little-endian bits 7- 5 or big-endian bits 121 - 124. @@ -16719,8 +16719,7 @@ vec_xst_be(result,0, &le_result); - - + vector bool long long vec_sll (vector bool long long, @@ -16729,8 +16728,7 @@ vec_xst_be(result,0, &le_result); - - + vector bool long long vec_sll (vector bool long long, @@ -16739,8 +16737,7 @@ vec_xst_be(result,0, &le_result); - - + vector signed long long vec_sll (vector signed long long, @@ -16749,8 +16746,7 @@ vec_xst_be(result,0, &le_result); - - + vector signed long long vec_sll (vector signed long long, @@ -16759,8 +16755,7 @@ vec_xst_be(result,0, &le_result); - - + vector unsigned long long vec_sll (vector unsigned long @@ -16769,8 +16764,7 @@ vec_xst_be(result,0, &le_result); - - + vector unsigned long long vec_sll (vector unsigned long @@ -17002,8 +16996,7 @@ vec_xst_be(result,0, &le_result); - - + vector signed long long vec_srl (vector signed long long, @@ -17012,8 +17005,7 @@ vec_xst_be(result,0, &le_result); - - + vector signed long long vec_srl (vector signed long long, @@ -17022,8 +17014,7 @@ vec_xst_be(result,0, &le_result); - - + vector unsigned long long vec_srl (vector unsigned long @@ -17032,8 +17023,7 @@ vec_xst_be(result,0, &le_result); - - + vector unsigned long long vec_srl (vector unsigned long diff --git a/specification/app_b.xml b/specification/app_b.xml index f0088ac..d503cdc 100644 --- a/specification/app_b.xml +++ b/specification/app_b.xml @@ -182,8 +182,7 @@ xml:id="dbdoclet.50655245_pgfId-1450875" revisionflag="added"> int __ builtin_bcdsub_ofl (vector unsigned char, vector - unsigned char - ); + unsigned char); @@ -315,7 +314,7 @@ xml:id="dbdoclet.50655245_pgfId-1450875" revisionflag="added"> - BCD Load and Store + BCD Load and Store diff --git a/specification/ch_2.xml b/specification/ch_2.xml index 522fb05..9bd4824 100644 --- a/specification/ch_2.xml +++ b/specification/ch_2.xml @@ -57,8 +57,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> A specific OpenPOWER-compliant processor implementation must state which type of byte ordering is to be used. - MSR[LE - | SLE]: Although it may be possible to modify the + MSR[LE|SLE]: Although it may be possible to modify the active byte ordering of an application process that uses application-accessible configuration controls or that uses system calls on some systems, applications that change active byte ordering @@ -2547,7 +2546,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> Vector of 16 bytes with a value of either 0 or 2 - 8- 1. + 8- 1. @@ -2599,7 +2598,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> Vector of 8 halfwords with a value of either 0 or 2 - 16- 1. + 16- 1. @@ -2651,7 +2650,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> Vector of 4 words with a value of either 0 or 2 - 32- 1. + 32- 1. @@ -2713,7 +2712,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> Vector of 2 doublewords with a value of either 0 or 2 - 64- 1. + 64- 1. @@ -3141,8 +3140,8 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> IBM EXTENDED PRECISION form provides the same range as double precision (about 10 - -308 to 10 - 308) but more precision (a variable amount, + -308 to 10 + 308) but more precision (a variable amount, about 31 decimal digits or more). @@ -3322,9 +3321,9 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> union where the number of bits in the bit field is specified. In , a signed range goes from -2 - w - 1 to 2 - w - 1- 1 and an unsigned range goes from 0 to 2 - w- 1. + w - 1 to 2 + w - 1- 1 and an unsigned range goes from 0 to 2 + w- 1. Bit Field Types @@ -4060,7 +4059,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> functions use these conventions, except as documented for the register save and restore functions.The conventions given in this section are adhered to by C programs. - For more information about the implementation of C, See + For more information about the implementation of C, See https://apps.na.collabserv.com/meetings/join?id=2897-3986 . While it is recommended that all functions use the standard @@ -4479,7 +4478,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> This ABI requires OpenPOWER-compliant processors to implement mfocr instructions in a manner that initializes undefined bits of the RT result register of - mfocr instructions to one of the following + mfocr instructions to one of the following values: @@ -4498,23 +4497,23 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> mfocr instruction, the POWER8 processor does not implement the behavior described in the "Fixed-Point Invalid Forms and Undefined Conditions" section of - POWER8 Processor User's Manual for the Single-Chip - Module. Instead, it replicates the selected condition + POWER8 Processor User's Manual for the Single-Chip + Module. Instead, it replicates the selected condition register field within the byte that contains it rather than initializing to 0 the bits corresponding to the nonselected bits of the byte that contains it. When generating code to save two condition register fields that are stored in the same byte, the compiler must mask the value received from - mfocr to avoid corruption of the resulting + mfocr to avoid corruption of the resulting (partial) condition register word. This erratum does not apply to the POWER9 processor. For more information, see - Power ISA, version 3.0 and "Fixed-Point Invalid + Power ISA, version 3.0 and "Fixed-Point Invalid Forms and Undefined Conditions" in - POWER9 Processor User's Manual. + POWER9 Processor User's Manual. In OpenPOWER-compliant processors, floating-point and vector functions are @@ -4574,10 +4573,10 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> - ... + ... - ... + ... @@ -4646,10 +4645,10 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> - ... + ... - ... + ... @@ -4735,10 +4734,10 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> - ... + ... - ... + ... @@ -4792,10 +4791,10 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> - ... + ... - ... + ... @@ -5552,7 +5551,7 @@ xml:id="dbdoclet.50655240_pgfId-1156194"> caller to determine the called function's characteristics (for example, functions in C without a prototype in scope, in accordance with Brian Kernighan and Dennis Ritche, - The C Programming Language, 1st + The C Programming Language, 1st edition). @@ -6727,10 +6726,10 @@ addi r2, r2, .TOC.@l This ABI shall be used in conjunction with the Power Architecture that implements the - mfocrf architecture level. Further, + mfocrf architecture level. Further, OpenPOWER-compliant processors shall implement implementation-defined bits in a manner to allow the combination of multiple - mfocrf results with an OR instruction; for example, + mfocrf results with an OR instruction; for example, to yield a word in r0 including all three preserved CRs as follows: mfocrf r0, crf2 @@ -6741,7 +6740,7 @@ or r0, r0, r1 Specifically, this allows each OpenPOWER-compliant processor implementation to set each field to hold either 0 or the correct in-order value of the corresponding CR field at the point where the - mfocrf instruction is performed. + mfocrf instruction is performed.   Assembly Language Syntax for Defining Entry Points @@ -7522,7 +7521,7 @@ stw r0,0,(r7) If the instruction using symbol@got@ - l has a signed immediate operand (for example, + l has a signed immediate operand (for example, addi), use symbol@got@ ha(high adjusted) for the high part of the offset. If it has an unsigned immediate operand (for example, ori), use diff --git a/specification/ch_3.xml b/specification/ch_3.xml index 0745a03..a7b0ac0 100644 --- a/specification/ch_3.xml +++ b/specification/ch_3.xml @@ -4219,7 +4219,7 @@ ld r3,x@got@l(r3) - Note: If X is a variable stored in the TOC, + Note: If X is a variable stored in the TOC, then X@got is the offset within the TOC of a doubleword whose value is X@toc. @@ -4230,7 +4230,7 @@ ld r3,x@got@l(r3) addis 2,12,.TOC.-func@ha addi 2,2,.TOC.-func@l The syntax - SYMBOL@localentry refers to the value of the local + SYMBOL@localentry refers to the value of the local entry point associated with a function symbol. It can be used to initialize a memory word with the address of the local entry point as follows: @@ -4345,7 +4345,7 @@ addi r4, r4, lower
Thread Local Storage ABI The - ELF Handling for Thread-Local Storage document is the + ELF Handling for Thread-Local Storage document is the authoritative TLS ABI specification that defines the context in which information in the TLS section of this Power Architecture 64-bit ELF V2 ABI must be viewed. For information about how to access this document, see @@ -6754,11 +6754,11 @@ nop
Traceback Tables To support debuggers and exception handlers, the 64-bit - OpenPOWER ELF V2 ABI defines the use of descriptive + OpenPOWER ELF V2 ABI defines the use of descriptive debug and unwind information that enables flexible debugging and unwinding of optimized code (such as, for example, DWARF). To support legacy tooling, the - OpenPOWER ELF V2 ABI also specifies the use of a + OpenPOWER ELF V2 ABI also specifies the use of a traceback table that may provide additional information about functions. diff --git a/specification/ch_4.xml b/specification/ch_4.xml index 0e8cf19..e43571e 100644 --- a/specification/ch_4.xml +++ b/specification/ch_4.xml @@ -603,7 +603,7 @@ AT_SYSINFO_EHDR 33 /* In many architectures, the kernel If the AT_PHDR entry is present, entries of types AT_PHENT, AT_PHNUM, and AT_ENTRY must also be present. See the Program Header section in Chapter 5 of the - System V ABI for more information about the program + System V ABI for more information about the program header table. AT_PHENT The a_val member of this entry holds the size, in bytes, of one @@ -620,7 +620,7 @@ AT_SYSINFO_EHDR 33 /* In many architectures, the kernel The a_ptr member of this entry holds the base address at which the interpreter program was loaded into memory. See the Program Header section in Chapter 5 of the - System V ABI for more information about the base + System V ABI for more information about the base address. AT_FLAGS If present, the a_val member of this entry holds 1-bit flags. Bits diff --git a/specification/ch_5.xml b/specification/ch_5.xml index 218dcd6..4de0834 100644 --- a/specification/ch_5.xml +++ b/specification/ch_5.xml @@ -342,26 +342,12 @@ xml:id="dbdoclet.50655243_pgfId-1099317"> handles data streams that are detected by the hardware and defined by the software. For more information, see “Data Stream Control Overview, ABI, and API” at the following link: - - - - - - https://github.com/paflib/paflib/wiki/Data-Stream-Control-Overview,-ABI,-and-API - - + https://github.com/paflib/paflib/wiki/Data-Stream-Control-Overview,-ABI,-and-API The event-based branching facility generates exceptions when certain criteria are met. For more information, see the “Event Based Branching Overview, ABI, and API” section at the following link: - - - - - - https://github.com/paflib/paflib/wiki/Event-Based-Branching----Overview,-ABI,-and-API - - + https://github.com/paflib/paflib/wiki/Event-Based-Branching----Overview,-ABI,-and-API
diff --git a/specification/ch_6.xml b/specification/ch_6.xml index e34f665..f3bdabc 100644 --- a/specification/ch_6.xml +++ b/specification/ch_6.xml @@ -131,7 +131,7 @@ register vector double vd = vec_splats(*double_ptr); Consequently, the vector numbering schemes can be described as big-endian and little-endian vector layouts and vector element numberings. (The term “endian” comes from the endian debates presented in - Gulliver's Travels by Jonathan Swift.) + Gulliver's Travels by Jonathan Swift.) For internal consistency, in the ELF V2 ABI, the default vector layout and vector element ordering in big-endian environments shall be big endian, and the default vector layout and vector element ordering in @@ -573,7 +573,7 @@ register vector double vd = vec_splats(*double_ptr);
- Reminder: The assignment operator = is the + Reminder: The assignment operator = is the preferred way to assign values from one vector data type to another vector data type in accordance with the C and C++ programming languages. diff --git a/specification/pom.xml b/specification/pom.xml index 87066c0..62a8719 100644 --- a/specification/pom.xml +++ b/specification/pom.xml @@ -75,34 +75,45 @@ leabi - - - working - - - - - - workgroupSpecification - - + + + + foundationConfidential + + + + draft + +