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title: "Changing the Game: Accelerating Applications and Improving Performance For Greater Data Center Efficiency"
date: "2015-01-16"
- "blogs"

### Abstract

Planning for exascale, accelerating time to discovery and extracting results from massive data sets requires organizations to continually seek faster and more efficient solutions to provision I/O and accelerate applications.  New burst buffer technologies are being introduced to address the long-standing challenges associated with the overprovisioning of storage by decoupling I/O performance from capacity. Some of these solutions allow large datasets to be moved out of HDD storage and into memory quickly and efficiently. Then, data can be moved back to HDD storage once processing is complete much more efficiently with unique algorithms that align small and large writes into streams, thus enabling users to implement the largest, most economical HDDs to hold capacity.

This type of approach can significantly reduce power consumption, increase data center density and lower system cost. It can also boost data center efficiency by reducing hardware, power, floor space and the number of components to manage and maintain. Providing massive application acceleration can also greatly increase compute ROI by returning wasted processing cycles to compute that were previously managing storage activities or waiting for I/O from spinning disk.

This session will explain how the latest burst buffer cache and I/O accelerator applications can enable organizations to separate the provisioning of peak and sustained performance requirements with up to 70 percent greater operational efficiency and cost savings than utilizing exclusively disk-based parallel file systems via a non-vendor-captive software-based approach.

### Speaker Bio

[Jeff Sisilli](, senior director of product marketing at DataDirect Networks, has over 12 years experience creating and driving enterprise hardware, software and professional services offerings and effectively bringing them to market. Jeff is often quoted in storage industry publications for his expertise in software-defined storage and moving beyond traditional approaches to decouple performance from capacity.

### Speaker Organization

DataDirect Networks

### Presentation

<iframe src="" width="100%" height="450" frameborder="0"></iframe>

[Download Presentation](

[Back to Summit Details](javascript:history.back())

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title: "2018 OpenPOWER/CAPI and OpenCAPI Heterogeneous Computing Design Contest"
date: "2018-07-27"
- "press-releases"
- "blogs"

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# Build Your Own Super Processor

\[/vc\_column\_text\]\[vc\_column\_text\]Organized by IBM China, IPS (Inspur Power Commercial Systems), The OpenPOWER Foundation, the OpenCAPI Consortium and Fudan University Microelectronics College, 2018 CAPI/OpenCAPI heterogeneous computing design contest begins July 6th.

The objective of the contest is to encourage universities and scientific research institutions to understand the advanced technology of FPGA heterogeneous computing on the OpenPOWER system and prepare applications for technological innovation. The participants will have the opportunity to cooperate with members of the OpenPOWER Foundation, the OpenCAPI Consortium to develop  prototypes on a OpenPOWER platform while receiving technical guidance from from sponsor companies experts.

The contest is sponsored by OpenPOWER Foundation members Shenzhen Semptian data Limited., Mellanox Technologies, Nallatech (a Molex company) and Xilinx, Inc,\[/vc\_column\_text\]\[vc\_column\_text css=".vc\_custom\_1538077233210{margin-top: 20px !important;}"\]

## Background

Heterogeneous Computing is a system that uses more than one processor. This multi-core system not only enhances the performance of the processor core, but also incorporates specialized processing capabilities, such as GPU or FPGA, to work on specific tasks.

In recent years, as the silicon chip approaches physical and economic cost limits, Moores law is dead.  The rapid development of the Internet, the explosive growth of information and the popularization of AI technology have highly increased the demand for computing power. Heterogeneous computing, the focus is not only limited to the improvement of CPU performance, but to break the bottleneck of data transmission between CPU and peripherals, and to allow more hardware devices to participate in computing, such as using dedicated hardware to be responsible for intensive computing or peripherals management, which can significantly improve the performance of the whole system. There is no doubt that heterogeneous computing is the main direction of improving computing power.

Participants in the OpenCAPI heterogeneous computing design competition can achieve insight by utilizing and optimizing the most advanced technology available through OpenPOWER architecture. This competition will provide an opportunity to create breakthrough technologies and for enterprise and research workloads.\[/vc\_column\_text\]\[vc\_column\_text css=".vc\_custom\_1538077241426{margin-top: 20px !important;}"\]

## Contest Rules

The contest will begin on July 6th with submissions due by Nov. 23rd.   The winner will be announced publically at the OpenPOWER China Summit 2018 in December in Beijing.  Announcement date yet to be determined

In preliminaries, participants will submit a solution proposal of a FPGA accelerator based on CAPI/OpenCAPI technology on OpenPOWER systems. The accelerator can serve any workload that requires high computing power or big data transaction bandwidth.  Ten winners of preliminaries will be selected and awarded funds to support them moving on to the final.

In final, participants will develop a prototype of their solution proposed in real development environment. Sponsors will provide them with OpenPOWER systems + CAPI/OpenCAPI enabled FPGA cards as well as technical expects that will provide coding and debugging skills for the CAPI development framework.\[/vc\_column\_text\]\[vc\_column\_text css=".vc\_custom\_1538077250723{margin-top: 20px !important;}"\]

## Timeline

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### Schedule

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### Time

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### Content

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#### Preliminary

\[/vc\_column\_text\]\[/vc\_column\_inner\]\[vc\_column\_inner width="1/5"\]\[vc\_column\_text\]7/6-8/15\[/vc\_column\_text\]\[/vc\_column\_inner\]\[vc\_column\_inner width="3/5"\]\[vc\_column\_text\]Enroll and submit proposal\[/vc\_column\_text\]\[/vc\_column\_inner\]\[/vc\_row\_inner\]\[vc\_row\_inner row\_type="row" type="full\_width" text\_align="left" css\_animation=""\]\[vc\_column\_inner width="1/5"\]\[/vc\_column\_inner\]\[vc\_column\_inner width="1/5"\]\[vc\_column\_text\]8/16-8/26\[/vc\_column\_text\]\[/vc\_column\_inner\]\[vc\_column\_inner width="3/5"\]\[vc\_column\_text\]Expert Review\[/vc\_column\_text\]\[/vc\_column\_inner\]\[/vc\_row\_inner\]\[vc\_row\_inner row\_type="row" type="full\_width" text\_align="left" css\_animation="" css=".vc\_custom\_1538076119836{padding-bottom: 1px !important;}"\]\[vc\_column\_inner width="1/5"\]\[/vc\_column\_inner\]\[vc\_column\_inner width="1/5"\]\[vc\_column\_text\]8/27\[/vc\_column\_text\]\[/vc\_column\_inner\]\[vc\_column\_inner width="3/5"\]\[vc\_column\_text\]Announce Top 10 for Final\[/vc\_column\_text\]\[/vc\_column\_inner\]\[/vc\_row\_inner\]\[vc\_row\_inner row\_type="row" type="full\_width" text\_align="left" css\_animation=""\]\[vc\_column\_inner width="1/5"\]\[vc\_column\_text\]

#### Final

\[/vc\_column\_text\]\[/vc\_column\_inner\]\[vc\_column\_inner width="1/5"\]\[vc\_column\_text\]8/27-11/23\[/vc\_column\_text\]\[/vc\_column\_inner\]\[vc\_column\_inner width="3/5"\]\[vc\_column\_text\]Prototype development and submission for final\[/vc\_column\_text\]\[/vc\_column\_inner\]\[/vc\_row\_inner\]\[vc\_row\_inner row\_type="row" type="full\_width" text\_align="left" css\_animation=""\]\[vc\_column\_inner width="1/5"\]\[/vc\_column\_inner\]\[vc\_column\_inner width="1/5"\]\[vc\_column\_text\]11/24-11/29\[/vc\_column\_text\]\[/vc\_column\_inner\]\[vc\_column\_inner width="3/5"\]\[vc\_column\_text\]Expert Review\[/vc\_column\_text\]\[/vc\_column\_inner\]\[/vc\_row\_inner\]\[vc\_row\_inner row\_type="row" type="full\_width" text\_align="left" css\_animation="" css=".vc\_custom\_1538076138264{padding-bottom: 2px !important;}"\]\[vc\_column\_inner width="1/5"\]\[/vc\_column\_inner\]\[vc\_column\_inner width="1/5"\]\[vc\_column\_text\](TBD)\[/vc\_column\_text\]\[/vc\_column\_inner\]\[vc\_column\_inner width="3/5"\]\[vc\_column\_text\]Final Thesis Oral Defense and Award Ceremony\[/vc\_column\_text\]\[/vc\_column\_inner\]\[/vc\_row\_inner\]\[vc\_row\_inner row\_type="row" type="full\_width" text\_align="left" css\_animation="" css=".vc\_custom\_1538077273553{margin-top: 20px !important;}"\]\[vc\_column\_inner\]\[vc\_column\_text\]

## Audiences and Enroll

College students from China universities and research institutes, who are interested in the CAPI/OpenCAPI technology are welcome to join.  They are also welcome to join the OpenPOWER Foundation at the Associate or Academic Level for free ([](

Click [More information]( to get to know more of the contest.

Click [Enroll]( for enrollment\[/vc\_column\_text\]\[/vc\_column\_inner\]\[/vc\_row\_inner\]\[/vc\_column\]\[/vc\_row\]\[vc\_row css\_animation="" row\_type="row" use\_row\_as\_full\_screen\_section="no" type="full\_width" angled\_section="no" text\_align="left" background\_image\_as\_pattern="without\_pattern" css=".vc\_custom\_1538077266597{margin-top: 20px !important;}" z\_index=""\]\[vc\_column\]\[vc\_column\_text\]

## Messages from Organizers and Sponsors

\[/vc\_column\_text\]\[vc\_row\_inner row\_type="row" type="full\_width" text\_align="left" css\_animation="" css=".vc\_custom\_1538077331586{margin-top: 16px !important;}"\]\[vc\_column\_inner width="1/6"\]\[vc\_single\_image image="5636" img\_size="full" qode\_css\_animation=""\]\[vc\_column\_text css=".vc\_custom\_1538076393779{margin-top: 16px !important;}"\]Waiming Wu, General Manager, IBM OpenPOWER China\[/vc\_column\_text\]\[/vc\_column\_inner\]\[vc\_column\_inner width="5/6"\]\[vc\_column\_text\]With the ever increasing demand for computing power today, OpenPOWER based on IBM POWER processor and Linux technology has attracted more and more attention from customers, developers and business partners. OpenPOWER systems, with its excellent computing and processing capabilities are ideal for AI, big data and cloud platforms. The OpenCAPI technology used in OpenPOWER systems support heterogeneous computing such that innovation in accelerators could be quickly integrated with POWER processor to provide the next level of computing performance. The new concept of heterogeneous computing based on collaboration between CPU and accelerators heralds a new computing era.

We are pleased to see the announcement and roll out of “The OpenCAPI + OpenPOWER Heterogeneous Computing Contest” for universities and research institutions. The OpenPOWER Foundation & OpenCAPI Consortium, Fudan University and many members of OpenPOWER actively support this activity. This is the best demonstration of the support from academic and corporate community in technological innovation. In IBM we will also do our best to co-organize this event and to contribute developing talents and innovative solutions.

We are also grateful to the technical experts at IBM China System Lab. Under this Contest, they will share the leading technology to the competing teams through in-depth technology seminars, carefully prepared technical documents and the upcoming one-to-one expert support, and of course great technical mentorship.\[/vc\_column\_text\]\[/vc\_column\_inner\]\[/vc\_row\_inner\]\[vc\_separator type="normal" thickness="1" up="16" down="16"\]\[vc\_row\_inner row\_type="row" type="full\_width" text\_align="left" css\_animation=""\]\[vc\_column\_inner width="1/6"\]\[vc\_single\_image image="5637" img\_size="full" qode\_css\_animation=""\]\[vc\_column\_text css=".vc\_custom\_1538076518297{margin-top: 16px !important;}"\]Hugh Blemings, Executive Director, OpenPOWER Foundation\[/vc\_column\_text\]\[/vc\_column\_inner\]\[vc\_column\_inner width="5/6"\]\[vc\_column\_text\]At the OpenPOWER Foundation were delighted to see our members like Mellanox, Nallatech, Semptian, Xilinx and of course IBM working together in the “OpenCAPI + OpenPOWER Contest”. CAPI/OpenCAPI is a key part of the great Open system that OpenPOWER represents and a leading high speed interconnect for Accelerators and Interconnects alike.

Our Members, working with some great universities and research institutions in China will provide both an opportunity for people to learn about CAPI/OpenCAPI and to see solutions to real world problems solved faster using innovative OpenPOWER hardware and software.

Were looking forward to seeing what innovative ideas the contestants come up with and, of course, congratulating the winners at the OpenPOWER Summit in Beijing in December. We wish all involved the very best!\[/vc\_column\_text\]\[/vc\_column\_inner\]\[/vc\_row\_inner\]\[vc\_separator type="normal" thickness="1" up="16" down="16"\]\[vc\_row\_inner row\_type="row" type="full\_width" text\_align="left" css\_animation=""\]\[vc\_column\_inner width="1/6"\]\[vc\_single\_image image="5639" img\_size="full" qode\_css\_animation=""\]\[vc\_column\_text css=".vc\_custom\_1538076676628{margin-top: 16px !important;}"\]Yujing Jiang, Product and Marketing Director, Inspur Power Commercial Systems Co., Ltd\[/vc\_column\_text\]\[/vc\_column\_inner\]\[vc\_column\_inner width="5/6"\]\[vc\_column\_text\]Inspur Power Commercial Systems Co., Ltd. is a platinum member of the OpenPOWER Foundation, committed to co-build an open OpenPOWER ecosystem, developing servers based on open Power technology, improving server ecosystems, building a sustainable server business and providing users with advanced, differentiated and diverse computing platforms and solutions. Inspur Power Systems insist on openness and integration for continuous development of heterogeneous computing architecture based on CAPI. CAPI heterogeneous computing breaks the computing walls, enhances massive parallel data processing capabilities and provides more effective and powerful data resources for image and video, deep learning and database. CAPI heterogeneous computing also provides extremely high data transmission bandwidth, defines a more flexible data storage method, and greatly improves server IO capabilities.

Inspur Power Systems will provide OpenPOWER based datacenter server FP5280G2 as the platform for the contest to verify and test the works. It is the first P9 platform in China, designed for cloud computing, big data, deep learning optimization. It is optimized in performance, extension and storage. The standalone FP5280G2 provides the leading PCIe Gen4 (16Gbps) channel in the industry, and supports CAPI 2.0. We wish this new system will bring an effective support to the contest. And in the future, we can build more systems to enhance heterogeneous computing with more interconnection through CAPI technology between CPU to memory, network, I/O device etc and be widely applied to industry market.\[/vc\_column\_text\]\[/vc\_column\_inner\]\[/vc\_row\_inner\]\[vc\_separator type="normal" thickness="1" up="16" down="16"\]\[vc\_row\_inner row\_type="row" type="full\_width" text\_align="left" css\_animation=""\]\[vc\_column\_inner width="1/6"\]\[vc\_single\_image image="5640" img\_size="full" qode\_css\_animation=""\]\[vc\_column\_text css=".vc\_custom\_1538076774108{margin-top: 16px !important;}"\]Yibo Fan, Associate Professor, Fudan University Microelectronics College, China\[/vc\_column\_text\]\[/vc\_column\_inner\]\[vc\_column\_inner width="5/6"\]\[vc\_column\_text\]CAPI/OpenCAPI is an unique technology in OpenPOWER system, which provides a superior operating environment for FPGA heterogeneous computing design, especially eliminating the driver development process and providing the most convenient method for rapid chip IP prototype verification and the deployment of heterogeneous systems. Based on CAPI technology, our team launched a CAPI running example of open source H.265 video encoder. Through the technical cooperation in the project, we fully realized the innovative value of CAPI technology for heterogeneous computing. Hopefully by hosting this contest, we can contact more excellent teams and talents who study and master CAPI technology in peer universities, and promote CAPI/OpenCAPI technology further to universities and industries.\[/vc\_column\_text\]\[/vc\_column\_inner\]\[/vc\_row\_inner\]\[vc\_separator type="normal" thickness="1" up="16" down="16"\]\[vc\_row\_inner row\_type="row" type="full\_width" text\_align="left" css\_animation=""\]\[vc\_column\_inner width="1/6"\]\[vc\_single\_image image="5641" img\_size="full" qode\_css\_animation=""\]\[vc\_column\_text css=".vc\_custom\_1538076852620{margin-top: 16px !important;}"\]Qingchun Song, Mellanox Technologies, Asia & Pacific Marketing Director\[/vc\_column\_text\]\[/vc\_column\_inner\]\[vc\_column\_inner width="5/6"\]\[vc\_column\_text\]As a member of OpenPOWER, Mellanox is pleased to be involved in the optimization of OpenCAPI. As a provider of intelligent end-to-end network products, Mellanox has always worked closely with x86 and POWER processor platforms. Mellanox intelligent network products has always been the best choice for the POWER platform.

In June 2018, Summit Supercomputer from Oak Ridge National Laboratory, US, was released at the International Supercomputing Conference in Frankfurt, Germany, It use the POWER CPU plus Mellanoxs InfiniBand network and it is now the fastest supercomputer and artificial intelligence computer in the world.

Mellanox network products currently support 100 GHz per second. Products with a speed of 200 GHz per end will be released into market in the next quarter. Better network speed requires the support of faster internal buses, and high speed OpenCAPI and 200G network products are an excellent match.

I hope that this OpenCAPI optimization contest can efficiently improve the performance of CAPI, and can realize the integration with RDMA technology, which truly realize the matching of internal network buses and external buses and help the next-generation data center. Finally, I wish the contest going smoothly, thank you.\[/vc\_column\_text\]\[/vc\_column\_inner\]\[/vc\_row\_inner\]\[vc\_separator type="normal" thickness="1" up="16" down="16"\]\[vc\_row\_inner row\_type="row" type="full\_width" text\_align="left" css\_animation=""\]\[vc\_column\_inner width="1/6"\]\[vc\_single\_image image="5642" img\_size="full" qode\_css\_animation=""\]\[vc\_column\_text css=".vc\_custom\_1538076930931{margin-top: 16px !important;}"\]Hao Li, General Manager, Semptian Data Co., Ltd\[/vc\_column\_text\]\[/vc\_column\_inner\]\[vc\_column\_inner width="5/6"\]\[vc\_column\_text\]Many thanks to the organizers of the event for inviting Semptian to participate in 2018 OpenCAPI Heterogeneous Computing Design Contest. In recent years, the way of relying solely on CPU to improve computing performance has come to an end. At the same time, various applications, which are emerging rapidly, raise higher demand on computing ability and constantly challenge the performance limit. It has become a consensus in industry that through heterogeneous computing we can break the bottleneck of computing and data transmission.

As a senior corporation which has more than ten years of experience in the field of FPGA developing, Semptian believes that with the help of FPGAs advantage of high performance, low power consumption, flexibility and ease of use, combined with the special technical advantage of CAPI technology in OpenPOWER systems, processing specific computing through FPGA + CAPI + CPU is the best way to optimize computing performance, reduce acquisition and operation costs and meet the requirements of applications and power consumptions.

We are very glad to participate in this contest together with other members of the OpenPOWER alliance to expand the development of the alliances ecosystem. Hopefully through this contest, we can explore more application scenarios, like artificial intelligence inference, image and video acceleration and gene computing acceleration, to expand the application of heterogeneous computing.\[/vc\_column\_text\]\[/vc\_column\_inner\]\[/vc\_row\_inner\]\[vc\_separator type="normal" thickness="1" up="16" down="16"\]\[vc\_row\_inner row\_type="row" type="full\_width" text\_align="left" css\_animation=""\]\[vc\_column\_inner width="1/6"\]\[vc\_single\_image image="5643" img\_size="full" qode\_css\_animation=""\]\[vc\_column\_text css=".vc\_custom\_1538077009696{margin-top: 16px !important;}"\]Fan Kui, Account Sales Manager Nallatech\[/vc\_column\_text\]\[/vc\_column\_inner\]\[vc\_column\_inner width="5/6"\]\[vc\_column\_text\]Nallatech and IBM have worked closely through the OpenPOWER Foundation to enable heterogeneous computing by way of CAPI1.0 & CAPI2.0 based FPGA Accelerators. Nallatechs 250S FPGA Accelerator supports CAPI1.0 and the 250S+ supports CAPI2.0. Additionally the OpenPOWER Accelerator Workgroups ”CAPI SNAP Acceleration Framework”, is also supported on these cards. CAPI SNAP eases the development of Accelerator Function Units, AFUs, within the FPGA in OpenPOWER systems. As you may very well know, FPGA computing is one of the leading technologies in the development of AI and Deep learning and is one of the most exciting advancements that will affect in how we live our lives.

We are all proud to sponsor such an aspirational and academic event with students of China that will boast amazing innovations in FPGA technology for future generations to come. Thank you for the opportunity of sponsoring your event. We wish you great fortune in this contest, as well as your career in FPGA Acceleration.\[/vc\_column\_text\]\[/vc\_column\_inner\]\[/vc\_row\_inner\]\[/vc\_column\]\[/vc\_row\]\[vc\_row css\_animation="" row\_type="row" use\_row\_as\_full\_screen\_section="no" type="full\_width" angled\_section="no" text\_align="left" background\_image\_as\_pattern="without\_pattern"\]\[vc\_column\]\[vc\_empty\_space\]\[/vc\_column\]\[/vc\_row\]

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title: "2019 OpenPOWER + OpenCAPI Heterogeneous Computing Design Contest"
date: "2019-09-24"
- "blogs"
- "openpower"
- "openpower-foundation"
- "opencapi"
- "opencapi-contest"

After the success of the 2018 OpenPOWER/CAPI and OpenCAPI Heterogeneous Computing Design Contest, we're excited to see its return in 2019! Groups from research institutions or universities in China are welcome to apply. You can find more information on the contest from our OpenPOWER ecosystem friends in China below. Good luck to all of the participants!


# 2019 OpenPOWER + OpenCAPI异构计算大赛









回顾2018 OpenPOWER/CAPI + OpenCAPI异构计算大赛








## 大赛介绍

2019 OpenPOWER + OpenCAPI异构计算大赛由OpenPOWER基金会、OpenCAPI联盟主办IBM中国承办浪潮商用机器有限公司协办多家OpenPOWER基金会成员支持旨在鼓励大学和科研机构了解和实践异构计算利用OpenPOWER系统上FPGA异构计算的先进技术开拓视野、积极创新、加速推动科技创新实际应用。









## 大赛主体单位









Alpha Data




## 竞赛背景

异构计算Heterogeneous Computing是指使用一种以上处理器的系统。这种多核心的系统不仅通过增加处理器内核提升性能还纳入专门的处理能力例如GPU或FPGA来应对特定的任务。



## 竞赛对象


- 每支队伍由一名以上学生及一位指导老师组成。指导老师是参赛队所属高校的正式教师,一位老师可以指导多支参赛队
- 允许一个学校有多只代表队
- 报名时应具备在校学籍
- 参赛队员应保证报名信息准确有效

## 竞赛奖励


一等奖   1支团队  奖金人民币2.5万元

二等奖   1支团队  奖金人民币2万元

三等奖   1支团队  奖金人民币 1.5万元

鼓励奖   进入复赛的其他7支队伍 奖金人民币5千元

## 赛程和赛制

本次竞赛分初赛和复赛两个阶段。初赛采用网上评审方式,复赛采用公开项目答辩的评审方式。 赛程安排如下:


<table><tbody><tr><td width="88">赛程</td><td width="205">时间</td><td width="293">内容</td></tr><tr><td rowspan="3" width="88">初赛</td><td width="205">9/24-10/25</td><td width="293">初赛方案设计及提交</td></tr><tr><td width="205">10/26-11/06</td><td width="293">初赛专家评审</td></tr><tr><td width="205">11/07</td><td width="293">公布复赛入围的10支团队的名单</td></tr><tr><td rowspan="3" width="88">复赛</td><td width="205">11/08-03/06/2020</td><td width="293">复赛作品开发及提交</td></tr><tr><td width="205">03/07/2020-03/14/2020</td><td width="293">复赛专家评审</td></tr><tr><td width="205">03/18/2020</td><td width="293">复赛答辩及颁奖典礼</td></tr></tbody></table>





- 解决计算能力瓶颈:大规模并行数据处理能力可以应用于神经网络,图像视频,密码学,网络安全,数据库、以及广泛领域中的数据计算(金融,地质,生物、材料、物理等)。
- 解决数据传输瓶颈超高的数据传输带宽可以应用于网络传输定义更灵活的数据存储方式并且利用FPGA在数据传输过程中顺便进行数据处理极大地减轻服务器端的CPU压力。




- 开发环境为主办单位和合作单位提供包括OpenPOWER服务器和支持CAPI接口的FPGA板卡搭建的远程环境。主要工作包括软件/硬件开发、调试、记录和分析测试结果。
- 具体开发过程中,企业导师一对一辅导,协助参赛者把设计实现成原型。复赛作品要求以论文形式提交原型开发报告和分析测试结果。



## 更多详情


CAPI的全称是Coherent Acceleration Processor Interface它是允许外部设备I/O Device和处理器CPU共享内存的接口技术。以FPGA为例作为现场可编程门阵列硬件它有令人惊叹的并行处理能力并完全可以自由定制但它连在系统中时仍然是个外部设备。它要参与到异构计算中和CPU协同工作不能共享内存怎么行呢从技术上看用CAPI接口连接FPGA作为异构计算平台有以下好处

- 它是带一致性的加速接口FPGA可以直接像CPU一样直接访问内存。避免软硬件协同设计中的地址转换操作大大简化编程思路进而降低研发开销缩短开发周期。
- 主机端程序完全工作在用户态无须编写PCIE设备驱动程序。
- FPGA作为I/O设备和主机通讯的延时更短。
- 在FPGA处理能力增加的场景下带宽瓶颈日益凸显。它是业内最领先的PCIE Gen4 (16Gbps) 和OpenCAPI (25Gbps) 通道,妥妥的大带宽!
- OpenCAPI还支持I/O通道的内存扩展由此探索存储级内存SCM对大数据应用的加速。



**Power Systems和OpenPOWER**


在全球众多最大型的集群中,都能看到 Power Systems 高性能计算服务器的身影。Power Enterprise 服务器专为数据设计,可为企业实现终极的弹性、可用性、安全性等性能,被广泛应用于银行、政府、航空、能源等企业的核心业务中,为要求苛刻的工作负载(例如,基因、金融、计算化学、石油和天然气勘探以及高性能数据分析)提供极致。


2013年IBM开放Power服务器架构成立OpenPOWER基金会(目前已经有来自34个国家和地区的340多家公司加入核心会员有IBM、Google、Nvidia、Redhat、CanonicalUbuntu、Hitachi、浪潮、Wistron等共同建设开放的OpenPOWER生态。对比传统Power系统基于 Linux 的OpenPOWER系统主要由联盟成员设计生产价格优势明显同时也能够实现出色的性能和投资回报率适用于计算密集型和数据密集型应用。这些服务器提供您所需的灵活性能够快速集成创新技术解决方案避免被供应商的专有技术所“套牢”并加速实现业务结果。


2018年初IBM 宣布推出POWER9处理器。全新POWER9芯片为计算密集型人工智能工作负载而设计是首批嵌入PCI-Express 4.0、新一代NVIDIA NVLink及OpenCAPI的处理器基于该处理器的系统可以大幅提升Chainer、TensorFlow及Caffe等各大人工智能框架的性能并加速Kinetica等数据库。提供超越过往所有设计的高速信号总线带宽。如此一来数据科学家能够实现以更快的速度构建包括科研范畴的深度学习洞察、实时欺诈检测和信用风险分析等范围的应用。POWER9是美国能源部Summit及Sierra超级计算机的核心这两台超级计算机是当今世界上性能最强的数据密集型超级计算机。

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title: Blogs
- html
- rss
- json
date: 2022-01-31
draft: false

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title: "A Better Way to Compress Big Data"
date: "2018-03-08"
- "blogs"
- "openpower"
- "center-for-genome-research-and-biocomputing"
- "oregon-state-university"
- "ibm-power-systems"

## **Wasting CPU hours on compression**

The Center for Genome Research and Biocomputing (CGRB) has a large computing resource that supports researchers at Oregon State University by providing processing power, file storage service and more. This computational resource is also used to capture all data generated from the CGRB Core Laboratory facility that processes biological samples used in High Throughput Sequencing (HTS) and other data rich tools.

Currently, the CGRB Core Lab generates between 4TB and 8TB of data per day which directly lands on the biocomputing resource and is made immediately available to researchers.  Because of this, the CGRB has over 4PB of usable space within our biocomputing facility and continues to add space monthly. Since individual labs must purchase file space needed to accomplish their research, there is always pressure from the lab managers to have users clean up and reduce space allowing for new experiments to be done without the need to purchase more space. This process leads to many users taking CPU time to compress data needed for later use but limiting the labs current available space. Since we like to use processing machines for processing data and not just compressing, we needed to find a solution allowing GZIP work to be done without tying up our CPU hours.

## **More computing, faster**

To reduce loads on the processing machines and computational time devoted to compressing data, we started considering FPGA cards.

Specifically, we evaluated offloading compression processes directly onto a peripheral FPGA card. Offloading compression would increase our output and help manage file space usage so groups do not have to purchase more space to start new experiments.

The new IBM Power Systems POWER8 machines include an interface used to increase speed from CPUs to FPGAs in expansion slots. The Coherent Accelerator Processor Interface (CAPI) connects the expansion bus and allows users to access resources external to the main CPU and memory with up to 238 GB/sec bus speed, thus overcoming a key limitation when working with large data sets.

Our users do take advantage of the capabilities of the FPGA card, they not only complete their tasks more quickly, but also free up additional CPU hours for other researchers on the cluster. The solution has provided a net benefit in resource utilization and thus has allowed _all_ users to do more computing, faster.

## **The GZIP coprocessor success story**

Initial tests showed compressing a small job with a 22-gigabyte file using the CPU would take over 9 minutes of time versus running on the FPGA card the same file would finish in 19 seconds. These tests were changed to massively increase the data being compressed and found that a job that would take 67 hours on the CPU would only take 50 minutes on the FPGA.

The FPGA GZIP coprocessor has allowed our researchers and staff to quickly recover valuable file space, while speeding up analytics and processing. The coprocessor has its own queue allowing users to submit jobs that can access the gzip card rather than wait to use it interactively. As the coprocessor can only be utilized by a single process at any given time, using the queuing system allows for a mechanism where multiple users can submit jobs to use the card without over-loaded card since the queue waits for one job to finished before beginning the next.

We have seen as much as a 100-fold increase in the rate at which we can compress and decompress data to and from our storage cluster. These data largely consist of text-based strings (e.g., A, C, T and G nucleotides), meaning they are highly compressible.

The compression ratio achieved with the gzip card is inferior to that obtained by running gzip directly through the main processor. Our observations indicate that the gzip card yields approximately 80% of the compression obtained using standard methods. This was within an acceptable range for our users since the speed of both compression and decompression is so much greater than those achieved by the standard methods.

<table><tbody><tr><td>15 GB .fastq sequence file</td><td><strong>Compressed</strong></td><td><strong>Runtime</strong></td><td><strong>Compression ratio</strong></td><td><strong>Compression</strong><strong>?</strong><strong> rate (GB/s)</strong></td></tr><tr><td>CPU gzip</td><td>3.1 GB</td><td>28m 53s</td><td>5.16</td><td>0.006</td></tr><tr><td>CPU gzip -9</td><td>2.9 GB</td><td>133M 36s</td><td>5.17</td><td>0.001</td></tr><tr><td>Power/CAPI Genwqe_gzip</td><td>4.2 GB</td><td>71 seconds</td><td>3.57</td><td>0.152</td></tr></tbody></table>

**Table-1:** Compression ratio comparison between CPU and FPGA of a 15GB fastq DNA sequence file.

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title: "A Deep Dive into A2I and A2O"
date: "2020-12-21"
- "blogs"
- "openpower"
- "ibm"
- "power"
- "openpower-foundation"
- "open-source"
- "a2i"
- "a2o"
- "open-hardware"
- "developer-community"
- "isa"
- "power-processor-core"

**By [Abhishek Jadhav,]( Lead Open Hardware Developer Community (India) and Freelance Tech Journalist**

After the opening of the [POWER instruction set architecture (ISA)]( last August, there have been many developments from IBM and its community.

Some major contributions include OpenPOWERs A2I and A2O POWER processor core.

The OpenPOWER Foundation, which is under the umbrella of the Linux Foundation, works on the advocacy of POWER Instruction Set Architecture and its usage in the industry.

## **What is A2I the core?**

[A2I core]( was created as a high-frequency four-threaded design, optimized for throughput and targeted for 3 GHz in 45nm technology. It was created to provide high streaming throughput, balancing performance and power.


_“With a strong foundation of the open POWER ISA and now the A2I core, the open source hardware movement is poised to accelerate faster than ever,” said James Kulina, Executive Director, OpenPOWER Foundation._

A2I was developed as a processor for customization and embedded use in system-on-chip (SoC) devices, however, it's not limited to that— it can be seen in supercomputers with appropriate accelerators. There is a diverse range of applications associated with the core including streaming, network processing, data analysis.

We have an [Open Hardware Developer Community]( and contributors across India working on A2I in multiple use cases. where there has been an increasing contribution from the open source community.

If you want a headstart on A2I core, check out this short [tutorial]( on how to get started.

## **The launch of A2O**

A couple of months after the A2I cores release at [OpenPOWER Summit 2020](, the OpenPOWER Foundation announced the A2O POWER processor core, an out-of-order follow-up to the A2I core. The A2O processor core is now open-source as a POWER ISA core for embedded use in SoC designs. The A2O offers better single-threaded performance, supports PowerISA 2.07, and has a modular design.


Potential A2O POWER processor core applications include artificial intelligence, autonomous driving, and secure computing.

If you want to get started with A2O POWER processor core, watch this short [tutorial](

The A2O reference manual is available [here](


Join the [Open Hardware Developer Community]( to engage in exciting projects on A2I and A2O processor core.

_Source: All the images were taken from the_ [_Github Repo_]( _and_ [_OpenPOWER Summit North America 2020_](

@ -0,0 +1,38 @@
title: "A POWERFUL Birthday Gift to Moore's Law"
date: "2015-04-12"
- "blogs"
- "featured"

By Bradley McCredie

President, OpenPOWER Foundation

As we prepare to join the computing world in celebrating the 50th anniversary of Moores Law, we cant help but notice how the aging process has slowed it down. In fact, in a [recent interview]( with IEEE Spectrum, Moore said, “I guess I see Moores Law dying here in the next decade or so.”  But we have not come to bury Moores Law.  Quite the contrary, we need the economic advancements that are derived from the scaling Moores law describes to survive -- and they will -- if it adapts yet again to changing times.

It is clear, as the next generation of warehouse scale computing comes of age, sole reliance on the “tick tock” approach to microprocessor development is no longer viable.  As I told the participants at our first OpenPOWER Foundation summit last month in San Jose, the era of relying solely on the generation to generation improvements of the general-purpose processor is over.  The advancement of the general purpose processor is being outpaced by the disruptive and surging demands being placed on todays infrastructure.  At the same time, the need for the cost/performance advancement and computational growth rates that Moores law used to deliver has never been greater.   OpenPOWER is a way to bridge that gap and keep Moores Law alive through customized processors, systems, accelerators, and software solutions.  At our San Jose summit, some of our more than 100 Foundation members, spanning 22 countries and six continents, unveiled the first of what we know will be a growing number of OpenPOWER solutions, developed collaboratively, and built upon the non-proprietary IBM POWER architecture. These solutions include:

Prototype of IBMs first OpenPOWER high performance computing server on the path to exascale

- First commercially available OpenPOWER server, the TYAN TN71-BP012
- First GPU-accelerated OpenPOWER developer platform, the Cirrascale RM4950
- Rackspace open server specification and motherboard mock-up combining OpenPOWER, Open Compute and OpenStack

Together, we are reimagining the data center, and our open innovation business model is leading historic transformation in our industry.

The OpenPOWER business model is built upon a foundation of a large ecosystem that drives innovations and shares the profits from those innovations. We are at a point in time where business model innovation is just as important to our industry as technology innovation.

You dont have to look any further than OpenPOWER Chairman, Gordon MacKeans company, Google to see an example of what I mean. While the technology that Google creates and uses is leading in our industry, Google would not be even be a shadow of the company it is today without its extremely innovative business model. Google gives away all of its advanced technology for free and monetizes it through other means.

In fact if you think about it, most all of the fastest growing “new companies” in our industry are built on innovative technology ideas, but the most successful ones are all leveraging business model innovations as well.

The early successes of the OpenPower approach confirm what we all know to expedite innovation, we must move beyond a processor and technology-only design ecosystem to an ecosystem that takes into account system bottlenecks, system software, and most importantly, the benefits of an open, collaborative ecosystem.

This is about how organizations, companies and even countries can address disruptions and technology shifts to create a fundamentally new competitive approach.

No one company alone can spark the magnitude or diversity of the type of innovation we are going to need for the growing number of hyper-scale data centers. In short, we must collaborate not only to survive…we must collaborate to innovate, differentiate and thrive.

The OpenPOWER Foundation, our global team of rivals, is modeling what we IBMers like to call “co-opetition” competing when it is in the best interest of our companies and cooperating with each other when it helps us all.  This combination of breakthrough technologies and unprecedented collaboration is putting us in the forefront of the next great wave of computing innovation.  Which takes us back to Moores Law.  In 1965, when Gordon Moore gave us a challenge and a roadmap to the future, there were no smartphones or laptops, and wide-scale enterprise computing was still a dream.  None of those technology breakthroughs would have been possible without the vision of one man who shared it with the world.  OpenPOWER is a bridge we share to a new era. Who knows what breakthroughs it will spawn in our increasingly technology-driven and connected world.  As Moores Law has shown us, the future is wide open.

@ -0,0 +1,31 @@
title: "A2I POWER Processor Core Contributed to OpenPOWER Community to Advance Open Hardware Collaboration"
date: "2020-06-30"
- "blogs"
- "openpower"
- "ibm"
- "openpower-foundation"
- "linux-foundation"
- "power-isa"
- "open-source"
- "ibm-a2i"
- "a2i-power-processor"
- "open-source-hardware"
- "open-source-summit"

At The Linux Foundation Open Source Summit today, the OpenPOWER Foundation announced a major contribution to the open source ecosystem: the IBM A2I POWER processor core design and associated FPGA environment. Following the [opening of the POWER Instruction Set Architecture (ISA)]( last August, todays announcement further enables the OpenPOWER Foundation to cultivate an ecosystem of open hardware development.

![A2I POWER Processor Core](images/A2I-POWER-Processor-Core-1024x583.png)

The A2I core is an in-order multi-threaded 64-bit POWER ISA core that was developed as a processor for customization and embedded use in system-on-chip (SoC) devices. It was designed to provide high streaming throughput while balancing performance and power. Originally the “wire-speed processor” of the Edge-of-Network SoC called PowerEN, it was later selected as the general purpose processor used in IBMs BlueGene/Q family of systems, which helped to advance scientific discovery over the last decade. Built for modularity, A2I has the ability to add an Auxiliary Execution Unit (AXU) that is tightly-coupled to the core, enabling many possibilities for special-purpose designs for new markets tackling the challenges of modern workloads.

“A2I has demonstrated its durability over the last decade - its a powerful technology with a wide range of capabilities,” said Mendy Furmanek, President, OpenPOWER Foundation and Director, POWER Open Hardware Business Development, IBM. “Were excited to see what the open source community can do to modernize A2I with todays open POWER ISA and to adapt the technology to new markets and diverse use cases.”

“With a strong foundation of the open POWER ISA and now the A2I core, the open source hardware movement is poised to accelerate faster than ever,” said [James Kulina](, Executive Director, OpenPOWER Foundation. “A2I gives the community a great starting point and further enables developers to take an idea from paper to silicon.”

The A2I core is available on GitHub and [can be accessed here](

[Register for OpenPOWER Summit North America 2020]( - a free, virtual experience - to learn more about the A2I core and other developments across the OpenPOWER ecosystem.

@ -0,0 +1,27 @@
title: "Academic and Industry Experts Share Expertise During OpenPOWER and AI Workshop at Loyola Institute of Technology"
date: "2019-03-07"
- "blogs"

By [Dr. Sujatha Jamuna Anand](, Principal, Loyola Institute of Technology


We recently held the OpenPOWER and AI training workshop in Chennai, India. In addition to faculty and students from [Loyola Institute of Technology](, we were joined by academic and industry experts from [IBM](, [Open Computing Singapore](, [Indian Institute of Technology Madras](, [University of Engineering and Management Kolkata]( and [Object Automation](

Attendees learned from a number of sessions:

- [Ganesan Narayanasamy](, IBM shared insight on AI, deep learning inferencing and edge computing. As part of his presentation, he shared several use cases which have been deployed in multiple industries around the world.
- [Jayaram Kizhekke Pakkathillam](, IIT Madras gave a brief introduction about unmanned aerial vehicles (UAVs) and the projects hes worked on as part of IIT Madras Aerospace Engineering department. He also discussed how UAVs are effectively used for military and agricultural purposes with examples of different AI systems.
- [Wilson Josup](, Open Computing Singapore spoke about the difference between CPUs and GPUs, different types and use cases of GPUs and how OpenPOWER architecture innovations contribute to improved performance from applications.
- [Gayathri Venkataramanan](, Object Automation and [Prince Barai](, University of Engineering and Management Kolkata delivered various AI use cases with excellent examples.

Beyond features of AI, several presentations and demonstrations answered how data-driven innovation can be brought to life, and what steps are needed to move AI out of the lab and into mainstream business.

The OpenPOWER and AI Workshop provided opportunities for young students to initiate their own AI-related projects and collaborations.



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title: "Accelerated Photodynamic Cancer Therapy Planning with FullMonte on OpenPOWER"
date: "2015-01-19"
- "blogs"

### Abstract

Photodynamic therapy (PDT) is a minimally-invasive cancer therapy which uses a light-activated drug (photosensitizer/PS). When the photosensitizer absorbs a photon, it excites tissue oxygen into a reactive state which causes very localized cell damage. The light field distribution inside the tissue is therefore one of the critical parameters determining the treatment's safety and efficacy. While FDA-approved and used for superficial indications, PDT has yet to be widely adopted for interstitial use for larger tumours using light delivered by optical fibres due to a lack of simulation and planning optimization software. Because tissue at optical wavelengths has a very high scattering coefficient, extensive Monte Carlo modeling of light transport is required to simulate the light distribution for a given treatment plan. To enable PDT planning, we demonstrate here our “FullMonte” system which uses a CAPI-enabled FPGA to simulate light propagation 4x faster and 67x more power-efficiently than a highly-tuned multicore CPU implementation. With coherent low-latency access to host memory, we are not limited by the size of on-chip memory and are able to transfer results to and from the accelerator rapidly, which will be support our iterative planning flow. Potential advantages of interstitial PDT include less invasiveness and potential post-operative complications than surgery, better damage targeting and confinement than radiation therapy, and no systemic toxicity unlike chemotherapy. While attractive for developed markets for better outcomes, PDT is doubly attractive in emerging regions because it offers the possibility of a single-shot treatment with very low-cost and even portable equipment supported by remotely-provided computing services for planning.

### Bios

Jeffrey Cassidy, MASc, PEng is a PhD candidate in Electrical and Computer Engineering at the University of Toronto. Lothar Lilge, PhD is a senior scientist at the Princess Margaret Cancer Centre and a professor of Medical Biophysics at the University of Toronto. Vaughn Betz, PhD is the NSERC-Altera Chair in Programmable Silicon at the University of Toronto.

### Acknowledgements

The work is supported by the Canadian Institutes of Health Research, the Canadian Natural Sciences and Engineering Research Council, IBM, Altera, Bluespec, and the Southern Ontario Smart Computing Innovation Platform.

### Presentation

<iframe src="" width="100%" height="450" frameborder="0"></iframe>

[Download Presentation](

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title: "Accelerating Key-value Stores (KVS) with FPGAs and OpenPOWER"
date: "2015-11-13"
- "blogs"
- "capi"
- "fpga"
- "xilinx"
- "kvs"

_By Michaela Blott, Principal Engineer, Xilinx Research_

First, a bit of background-- I lead a research team in the European headquarters of Xilinx where we look into FPGA-based solutions for data centers. We experiment with the most advanced platforms and tool flows, hence our interest in OpenPOWER. If you haven't worked with an FPGA yet, its a fully programmable piece of silicon that allows you to create the perfect hardware circuit for your application thereby achieving best-in-class performance through customized data-flow architectures, as well as substantial power savings.  That means we can investigate how to make data center applications faster, smarter and greener while scrutinizing silicon features and tools flows. Our first application deep-dive was, and still is, key-value stores.

Key-value stores (KVS) are a fundamental part of todays data center functionality. Facebook, Twitter, YouTube, flickr and many others use key-value stores to implement a tier of distributed caches for their web content to alleviate access bottlenecks on relational databases that dont scale well. Up to 30% of data center servers implement key-value stores. But data centers are hitting a wall with performance requirements that drive trade-offs between high DRAM costs (in-memory KVS), bandwidth, and latency.

Weve been investigating KVS stores such as memcached since 2013 \[1,2\]. Initially the focus was on pure acceleration and power reduction. Our work demonstrated a substantial 35x performance/power versus the fastest x86 results published at the time. The trick was to completely transform the multithreaded software implementation into a data-flow architecture inside an FPGA as shown below.

\[caption id="attachment\_2117" align="aligncenter" width="693"\]![Fig 1](images/Fig-1.jpg) Figure 1: 10Gbps memcached with FPGAs\[/caption\]

However, there were a number of limitations: First, we were not happy with the constrained amount of DRAM that can be attached to an FPGA -- capacity is really important in the KVS context. Secondly, we were concerned about supporting more functionality.   For example, for protocols like Redis with its 200 commands, things can get complicated. Thirdly, we worried about ease-of-use, which is a typical adoption barrier for FPGAs. Finally, things become even more interesting once you add intelligence on top of your data: data analytics, object recognition, encryption, you name it. For this we really need a combination of compute resources that coherently shares memory. Thats exactly why OpenPOWER presented a unique and most timely opportunity to experiment with coherent interfaces.

**Benchmarking CAPI**

CAPI, the Coherent Accelerator Processor Interface, enables high performance and simple programming models for attaching FPGAs to POWER8 systems. First, we benchmarked PCI-E and CAPI acceleration against x86 in-memory models to determine the latency of PCI-E and CAPI. The results are explained below:

\[caption id="attachment\_2118" align="aligncenter" width="619"\]![Figure2_new](images/Figure2_new.jpg) Figure 2: System level latency OpenPower with FPGA vs x86\[/caption\]


PCI-E DMA Engines and CAPI perform significantly better than typical x86 implementations. At 1.45 microseconds, CAPI operations are so low-latency that overall system-level impact is next to negligible.  Typical x86 installations service memcached requests within a range of 100s to 1000s of microseconds. Our OpenPower CAPI installation services the same requests in 3 to 5 microseconds, as illustrated in Figure 2 (which uses a logarithmic scale).

\[caption id="attachment\_2119" align="aligncenter" width="698"\]![Figure3_new](images/Figure3_new.jpg) Figure 3: PCIe vs CAPI Bandwidth over transfer sizes\[/caption\]


Figure 3 shows measured bandwidth vs. transfer size for CAPI in comparison to a generic PCIe DMA. The numbers shown are actual measurements \[4\] and are representative in that PCIe performance is typically very low for small transfer sizes and next to optimal for large transfer sizes. So for small granular access, CAPI far outperforms PCIe. Because of this, CAPI provides a perfect fit for the small transfer sizes as required in the KVS scenario. For implementing object storage in host memory, we are really only interested in using CAPI in the range of transfer sizes of 128 bytes to 1kbyte. Smaller objects can be easily accommodated in FPGA-attached DRAM; larger objects can be accommodated in Flash (see also our HotStorage 2015 publication \[3\]).

**FPGA Design**

Given the promising benchmarking results, we proceeded to integrate the host memory via CAPI. For this we created a hybrid memory controller which routes and merges requests and responses between the various storage types, handles reordering, and provides a gearbox for varying access speeds and bandwidths. With these simple changes, we now have up to 1 Terabyte of coherent memory space at our disposal without loss of performance! Figure 4 shows the full implementation inside the FPGA.

\[caption id="attachment\_2120" align="aligncenter" width="748"\]![Figure4](images/Figure4.jpg) Figure 4: Memcached Implementation with OpenPower and FPGA\[/caption\]

**Ease of Use**

Our next biggest concern was ease of use for both FPGA design entry as well as with respect to hostaccelerator integration. In regards to the latter, OpenPOWER exceeded our expectations. Using the provided API from IBM (libcxl) as well as the POWER Service Layer IP that resides within the FPGA (PSL), we completed system integration within a matter of weeks while saving huge amounts of code: 800 lines of code to be precise for x86 driver, memory allocation, and pinning, and 13.5k fewer instructions executed!

Regarding the FPGA design, it was of utmost importance to ensure that it is possible to create a fully functional and high-performing design through a high-level design flow (C/C++ at minimum), in the first instance using Xilinxs high-level synthesis tool, Vivado HLS. The good news was that we fully succeeded in doing this and the resulting application design was fully described in C/C++, achieving a 60% reduction in lines of code (11359 RTL vs 4069 HLS lines). The surprising bonus was that we even got a resource reduction for FPGA-savvy readers: 22% in LUTs & 30% in FFs. And let me add, just in case you are wondering, the RTL designers were at the top of their class!

The only low-level aspects left in the design flow are the basic infrastructure IP, such as memory controllers and network interfaces, which are still manually integrated. In the future, this will be fully automated through SDAccel. In other words, a full development environment that requires no further RTL development is on the horizon.


\[caption id="attachment\_2121" align="aligncenter" width="693"\]![Figure5](images/Figure5.jpg) Figure 5: Demonstration at the OpenPower Summit 2015\[/caption\]

We demonstrated the first operational prototype of this design at Impact in April 2014 and then demonstrated the fully operational demo vehicle (shown in Figure 5) including fully CAPI-enabled access to host memory at the OpenPOWER Summit in March 2015. The work is now fully integrated with [IBMs SuperVessel]( In the live demonstration, the OpenPOWER system outperforms an x86 implementation by 20x (see Figure 6)!

\[caption id="attachment\_2122" align="aligncenter" width="625"\]![kvs_comparison](images/kvs_comparison-1024x577.jpg) Figure 6: Screenshot of network tester showing response traffic rates from OpenPower with FPGA acceleration versus x86 software solution\[/caption\]


The Xilinx demo architecture enables key-value stores that can operate at **60Gbps with 2TB value-store capacity** that fits within a 2U OpenPOWER Server. The architecture can be easily extended. We are actively investigating using Flash to expand value storage even further for large granular access. But most of all, we are really excited about the opportunities for this architecture when combining this basic functionality with new capabilities such as encryption, compression, data analytics, and face & object recognition!

**Getting Started**

- Visit [Xilinx at SC15](! November 15-19, Austin, TX.
- Learn more about [POWER8 CAPI](
- Purchase a CAPI developer kit from [Nallatech]( or [AlphaData](
- License this technology through [Xilinx]( today.  We work directly with customers and data centers to scale performance/watt in existing deployments with hardware based KVS accelerators. If you are interested in this technology, please contact us.



_\[1\] M.Blott, K.Vissers, K.Karras, L.Liu, Z. Istvan, G.Alonso: HotCloud 2013; Achieving 10Gbps line-rate key-value stores with FPGAs_

_\[2\] M.Blott, K. Vissers: HotChips14; Dataflow Architectures for 10Gbps Line-rate Key-value-Stores._

_\[3\] M.Blott, K.Vissers, L.Liu: HotStorage 2015; Scaling out to a Single-Node 80Gbps Memcached Server with 40Terabytes of Memory_

_\[4\] PCIe bandwidth reference numbers were kindly provided by Noa Zilberman & Andrew Moore from Cambridge University_

* * *

**_About Michaela Blott_**

![Michaela Blott](images/Michaela-Blott.png)

Michaela Blott graduated from the University of Kaiserslautern in Germany. She worked in both research institutions (ETH and Bell Labs) as well as development organizations and was deeply involved in large scale international collaborations such as NetFPGA-10G. Today, she works as a principal engineer at the Xilinx labs in Dublin heading a team of international researchers, investigating reconfigurable computing for data centers and other new application domains. Her expertise includes data centers, high-speed networking, emerging memory technologies and distributed computing systems, with an emphasis on building complete implementations.

@ -0,0 +1,31 @@
title: "Accelerator Opportunities with OpenPower"
date: "2015-01-16"
- "blogs"

### Abstract

The OpenPower architecture provides unique capabilities which will enable highly effective and differentiated acceleration solutions.   The OpenPower Accelerator Workgroup is chartered to develop both hardware the software standards which provide vendors the ability to develop these solutions.  The presentation will cover an overview of the benefits of the OpenPower architecture for acceleration solutions.   We will provide an overview of the Accelerator Workgroups plans and standards roadmap.   We will give an overview of the OpenPower CAPI development kit.   We will also walk through an example of a CAPI attached acceleration solution.

### Presentation agenda

- Overview of opportunity for OpenPower acceleration solutions
- OpenPower Accelerator workgroup charter and standards roadmap
- OpenPower CAPI Development Kit
- CAPI attached acceleration solution example

### Bio

[Nick Finamore](, Altera Corporation Product Marketing Manager for Software Development Tools  Chairperson,  OpenPower Foundation Accelerator Workgroup

For the past 3 years Nick has been leading Alteras computing acceleration initiative and the marketing  of Alteras SDK for OpenCL.  Previously Nick was in several leadership positions at early stage computing and networking technology companies including Netronome, Ember(SiLabs) and Calxeda.   Nick also had an 18 year career at Intel where he held several management positioning including general manager of the network processor division.

### Presentation

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@ -0,0 +1,30 @@
title: "Singapore's A*CRC Joins the OpenPOWER Foundation to Accelerate HPC Research"
date: "2016-03-17"
- "blogs"
- "featured"

_By Ganesan Narayanasamy, Senior Manager, IBM Systems_

Singapores Agency for Science, Technology and Research (A\*STAR) is the largest government funded research organization in Singapore, with over 5,300 personnel in 14 research institutes across the country.

[![A STAR Computational Resource Centre](images/A-STAR-Computational-Resource-Centre.png)](

A\*STAR Computational Resource Centre (A\*CRC) provides high performance computational (HPC) resources to the entire A\*STAR research community. Currently A\*CRC supports HPC needs of an 800 member user community and manages several high-end computers, including an IBM 822LC system with NVIDIA K80 GPU Cards and Mellanox EDR switch to port and optimize the HPC applications. It is also responsible for very rapidly growing data storage resources.

A\*CRC will work with IBM and the OpenPOWER Foundation to hasten its path to develop applications on OpenPOWER Systems leveraging the Foundations ecosystem of technology.

Experts it A\*CRC will explore the range of scientific applications that leverage the Power architecture as well as NVIDIAs GPU and Mellanoxs 100 GB/sec Infiniband switches. The switches are designed to work with IBM's Coherent Application Processor Interface (CAPI), an OpenPOWER technology that allows attached accelerators to connect with the Power chip at a deep level.

A\*CRC also will work with the OpenPOWER Foundation on evolving programming models such as OpenMP, the open multiprocessing API designed to support multi-platform shared memory.

“We need to anticipate the rise of new high performance computing architectures that bring us closer to exascale and prepare our communities,” A\*CRC CEO Marek Michalewicz noted in a statement.


This week, A\*STAR is hosting the [Singapore Supercomputing Frontiers Conference]( To learn more about their work, take part in our OpenPOWER workshop on March 18 and stay tuned for additional updates.

@ -0,0 +1,24 @@
title: "Advancing the Human Brain Project with OpenPOWER"
date: "2016-10-27"
- "blogs"
- "featured"

_By Dr. Dirk Pleiter, Research Group Leader, Jülich Supercomputing Centre_

![Human Brain Project and OpenPOWER members NVIDIA, IBM](images/HBP_Primary_RGB-1-1024x698.png)

The [Human Brain Project]( (HBP), a flagship project [funded by the European Commission](, has set itself an ambitious goal: Unifying our understanding of the human brain. To achieve it, researchers need a High-Performance Analytics and Compute Platform comprised of supercomputers with features that are currently not available, but OpenPOWER is working to make them a reality.

Through a Pre-Commercial Procurement (PCP) the HBP initiated the necessary R&D, and turned to the OpenPOWER Foundation for help. During three consecutive phases, a consortium of [IBM and NVIDIA has successfully been awarded with R&D contracts]( As part of this effort, a pilot system called [JURON]( (a combination of Jülich and neuron) has been installed at Jülich Supercomputing Centre (JSC). It is based on the [new IBM S822LC for HPC servers](, each equipped with two POWER8 processors and four NVIDIA P100 GPUs.

Marcel Huysegoms, a scientist from [the Institute for Neuroscience and Medicine](, with support from the JSC could demonstrate soon after deployment the usability of the system for his brain image registration application. Exploiting the processing capabilities of the GPUs without further tuning, could achieve a significant speed-up compared to the currently used production system based on Haswell x86 processors and K80 GPUs.

Not only do the improved compute capabilities matter for brain research, but also by designing and implementing the Global Sharing Layer (GSL), the non-volatile memory cards mounted on all nodes became a byte addressable, globally accessible memory resource. Using JURON it could be shown that data can be read at a rate that is only limited by network performance. These new technologies will open new opportunities for enabling data-intensive workflows in brain research, including data visualization.

The pilot system will be the first system based on POWER processors where graphics support is being brought to the HPC node. In combination with the GSL it will be possible to visualize large data volumes that are, as an example, generated by brain model simulations. Flexible allocation of resources to compute applications, data analytics and visualization pipelines will be facilitated through another new component, namely the dynamic resource management. It allows for suspension of execution of parallel jobs for a later restart with a different number of processes.

JURON clearly demonstrates the potential of a technology ecosystem settled around a processor architecture with interfaces that facilitate efficient integration of various devices for efficient processing, moving and storing of data. In other words, it demonstrates the collaborative potential of OpenPOWER.

@ -0,0 +1,22 @@
title: "Advancing the OpenPOWER vision"
date: "2015-01-16"
- "blogs"

### Abstract

Its been nearly a year since the public launch of OpenPower and the community of technology leaders that make up our community have made significant progress towards our original goals. While growth of the membership is a critical factor, our success will come from the technology provided through the open model and the value solutions that are enabled by leveraging that technology. Please join us as we highlight the key components that our member community have contributed to that open model and spotlight some examples of high value solutions enabled through members leveraging our combined capabilities and strengths.

### Speaker

[Gordon MacKean]( is a Sr. Director with the Hardware Platforms team at Google. He leads the team responsible for the design and development of the server and storage products used to power Google data centers. Prior to Google, Gordon held management and design roles at several networking companies including Matisse Networks, Extreme Networks, and Nortel Networks. Gordon is a founder of OpenPOWER Foundation and serves as the Chairman of the Board of Directors. Gordon holds a Bachelors degree in Electrical Engineering from Carleton University.

### Presentation

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@ -0,0 +1,24 @@
title: "AI to Improve Rural Healthcare Discussed at OpenPOWER Summit Europe"
date: "2018-10-18"
- "blogs"
- "featured"

By Dr. Praveen Kumar B.A. M.B.B.S, M.D., professor, Department of Community Medicine, PES Institute of Medical Sciences and Research

It was great to attend the [OpenPOWER Summit Europe]( in Amsterdam earlier this month. As an academia member from a medical background, it was the first completely technical forum I had attended at an international level.

The [PES Institute of Medical Sciences](, India has been working with IBM and the OpenPOWER community recently on developing AI solutions for patient care in our rural facility. We are a tertiary care teaching institute catering to a rural population of around one million. I attended the OpenPOWER Summit Europe to discuss the need and opportunity for deploying AI solutions in our work.

<iframe style="border: 1px solid #CCC; border-width: 1px; margin-bottom: 5px; max-width: 100%;" src="//" width="595" height="485" frameborder="0" marginwidth="0" marginheight="0" scrolling="no" allowfullscreen="allowfullscreen"></iframe>

**[Artificial Intelligence in Healthcare at OpenPOWER Summit Europe](// "Artificial Intelligence in Healthcare at OpenPOWER Summit Europe")** from **[OpenPOWERorg](**

AI in health care was a featured theme throughout the OpenPOWER Summit Europe. Professor Florin Manaila demonstrated solutions he has worked on for breast cancer diagnosis and grading using image processing. And Professor Antonio Liotta spoke about machine learning and AI-related research in his lab.

The AI4Good Hackathon invited researchers from across the world to find solutions for health challenges particularly in cancer care. I was glad to see students from India and Europe participating.

I look forward to networking with other academic and industry teams to work on further developing model training and implementation. Through collaboration, institutions can partner together to secure funding and innovate toward a brighter future.

@ -0,0 +1,39 @@
title: "Algo-Logic Systems launches CAPI enabled Order Book running on IBM® POWER8™ server"
date: "2015-03-18"
- "press-releases"
- "blogs"

SANTA CLARA, Calif., March 16, 2015 /PRNewswire/ -- Algo-Logic Systems, a recognized leader in providing hardware-accelerated, deterministic, ultra-low-latency products, systems and solutions for accelerated finance, packet processing and embedded system industries, announced today availability of their new Coherent Accelerator Processor Interface (CAPI) enabled Full Order Book solution on IBM® POWER8™ systems. The CAPI enabled Order Book performs all feed processing and book building in logic inside a single Stratix V FPGA on the Nallatech P385 card. The system enables software to directly receive order book snapshots in the coherent shared memory with the least possible latency. The low latency Order Book is designed using the on-chip memory for customer book sizes with many thousands of open orders, up to 24 symbols, and reporting of six L-2 book levels. For use cases where millions of open orders and full market depth need to be tracked, the scalable CAPI enabled Order Book is still implemented with a single FPGA but stores data in off-chip memory.

Photo - [](

The CAPI Order Book building process includes (i) receiving parsed market data feed messages, (ii) building and maintaining L-3 order-level replica of the exchange's displayable book, (iii) building L-2 books for each symbol with the market depth and weight summary of all open orders, (iv) reporting locally generated copy of the top-of-book with configurable amount of market depth (L-2 snapshots) as well as the last trade information when orders execute. By using the IBM POWER8 server, algorithms can run on the highest number of cores and seamlessly integrate with the Order Book hardware accelerator by means of the coherent shared memory. Through simple memory-mapped IO (MMIO) address space, all the parameters are configurable and statistics can be easily read from software. Algo-Logic's CAPI enabled Full Order Book achieves deterministic, ultra-low-latency without jitter regardless of the number of tracked symbols at data rates of up to 10 Gbps. Key features include:

- Accelerated Function Unit (AFU) is implemented on FPGA under CAPI
- Full Order Book with a L-2 default size of 6 price-levels per symbol, fully scalable to larger sizes
- By default L-2 snapshots are generated for each symbol
- The number of symbols in use and their respective snapshots are user configurable
- L-2 snapshot generation frequency is also user configurable on an event basis or at a customizable interval
- Full Order Book with a L-2 default size of 6 price-levels per symbol, fully scalable to larger sizes
- By default L-2 snapshots are generated for each symbol
- The number of symbols in use and their respective snapshots are user configurable
- L-2 snapshot generation frequency is also user configurable on an event basis or at a customizable interval
- Full Order Book output logic seamlessly connects to customer's proprietary algorithmic trading strategies
- Trader has access to the latest market depth (L-2 snapshots) in coherent shared memory
- L-3 Book updates complete with processing latency of less than 230 nanoseconds
- L-2 Book updates complete with processing latency of less than 120 nanoseconds

The CAPI Order Book can be seamlessly integrated with other components of Algo-Logic's Low Latency Application Library, including pre-built protocol parsing libraries, market data filters, and TCP/IP endpoints to deploy complete tick-to-trade applications within a single Stratix V FPGA platform.

Algo-Logic's world-class hardware accelerated systems and solutions are used by banks, trading firms, market makers, hedge-funds, and financial institutions to accelerate their network processing for protocol parsing, symbol filtering, Risk-Checks (sec 15c 3-5), order book processing, order injection, proprietary trading strategies, high frequency trading, financial surveillance systems, and algorithmic trading.

Availability: The CAPI Order Book solution is currently shipping, for additional information please contact []( or visit our website at: [](

About Algo-Logic Systems Algo-Logic Systems, Inc., is the recognized leader and developer of Gateware Defined Networking® (GDN) for Field Programmable Gate Array (FPGA) devices. Algo-Logic IP-Cores are used for accelerated finance, packet processing and classification in datacenters, and real-time data acquisition and processing in embedded hardware systems. The company has extensive experience in building complete network processing system solutions in FPGA logic.

To view the original version on PR Newswire, visit:[](

SOURCE Algo-Logic Systems

@ -0,0 +1,9 @@
title: "Altera Brings FPGA-based Acceleration to IBM Power Systems and Announces Support for OpenPOWER Consortium"
date: "2014-11-18"
- "press-releases"
- "blogs"

San Jose, Calif., November 18, 2013—Altera Corporation (NASDAQ: ALTR) today announced the latest release of the Altera SDK for OpenCL supports IBM Power Systems servers as an OpenCL system host. Customers are now able to develop OpenCL code that targets IBM Power Systems CPUs and accelerator boards with Altera FPGAs as a high-performance compute solution. FPGA accelerated systems can achieve a 5-20X performance boost over standard CPU based servers. Altera will showcase the performance advantage of using FPGAs to accelerate IBM Power Systems, as well as other OpenCL-focused demonstrations, this week at SuperComputing 2013 in booth #4332.

@ -0,0 +1,9 @@
title: "Altera Joins IBM OpenPOWER Foundation to Enable the Development of Next-Generation Data Centers"
date: "2014-03-24"
- "press-releases"
- "blogs"

San Jose, Calif., March 24, 2014 Altera Corporation (Nasdaq: ALTR) today announced it joined the IBM OpenPOWER Foundation, an open development alliance based on IBM's POWER microprocessor architecture. Altera will collaborate with IBM and other OpenPOWER Foundation members to develop high-performance compute solutions that integrate IBM POWER CPUs with Alteras FPGA-based acceleration technologies for use in next-generation data centers.

@ -0,0 +1,35 @@
title: "American Megatrends Custom Built Server Management Platform for OpenPOWER"
date: "2015-11-13"
- "blogs"
- "power8"
- "ami"

**_By Christine M. Follett, Marketing Communications Manager, American Megatrends, Inc._**

As one of the newest members of the OpenPOWER Foundation, we at American Megatrends, Inc. (AMI) are very excited get started and contribute to the mission and goals of the Foundation. Our President and CEO, Subramonian Shankar, who founded the company thirty years ago, shares his thoughts on joining the Foundation:

“Participating in OpenPOWER with partners such as IBM and TYAN will allow AMI to more rapidly engage as our market continues to grow, and will ensure our customers receive the industrys most reliable and feature-rich platform management technologies. As a market leader for core server firmware and management technologies, we are eager to assist industry leaders in enabling next generation data centers as they rethink their approach to systems design.”

![MegaRAC_SPX_logo_1500x1200](images/MegaRAC_SPX_logo_1500x1200-300x240.png) The primary technology that AMI is currently focusing on relative to its participation in the OpenPOWER Foundation is a full-featured server management solution called MegaRAC® SPX, in particular a custom version of this product developed for POWER8-based platforms. MegaRAC SPX for POWER8 is a powerful development framework for server management solutions composed of firmware and software components based on industry standards like IPMI 2.0, SMASH, Serial over LAN (SOL). It offers key serviceability features including remote presence, CIM profiles and advanced automation.

MegaRAC SPX for POWER8 also features a high level of modularity, with the ability to easily configure and build firmware images by selecting features through an intuitive graphical development tool chain. These features are available in independently maintained packages for superior manageability of the firmware stack. You can learn more about MegaRAC SPX at our website dedicated to AMI remote management technology [here](

![AMI dashboard](images/AMI-dashboard.png)

Foundation founding member TYAN has been an early adopter of MegaRAC SPX for POWER8, adopting it for one of their recent platforms. According to Albert Mu, Vice President of MITAC Computing Technology Corporations TYAN Business Unit, “AMI has been a critical partner in the development of our POWER8-based platform, the TN71-BP012, which is based on the POWER8 Architecture and provides tremendous memory capacity as well as outstanding performance that fits in datacenter, Big Data or HPC environments. We are excited that AMI has strengthened its commitment to the POWER8 ecosystem by joining the OpenPOWER Foundation.”

Founded in 1985, AMI is known worldwide for its AMIBIOS® firmware. From our start as the industrys original independent BIOS vendor, we have evolved to become a key supplier of state-of-the-art hardware, software and utilities to top-tier manufacturers of desktop, server, mobile and embedded computing systems.

With AMIs extensive product lines, we are uniquely positioned to provide all of the fundamental components to help OpenPOWER innovate across the system stack, providing performance, manageability, and availability for today's modern data centers. AMI prides itself on its unique position as the only company in the industry that offers products and services based on all of these core technologies.

AMI is extremely proud to join our fellow OpenPOWER member organizations working collaboratively to build advanced server, networking, storage and acceleration technology as well as industry-leading open source software. Together we can deliver more choice, control and flexibility to developers of next-generation hyperscale and cloud data centers.

* * *

**_About Christine M. Follett_**

_![Christine Follett](images/Christine-Follett.png)Christine M. Follett is Marketing Communications Manager for American Megatrends, Inc. (AMI). Together with the global sales and marketing team of AMI, which spans seven countries, she works to expand brand awareness and market share for the companys diverse line of OEM, B2B/Channel and B2C technology products, including AMI's industry leading Aptio® V UEFI BIOS firmware, innovative StorTrends® Network Storage hardware and software products, MegaRAC® remote server management tools and unique solutions based on the popular Android™ and Linux® operating systems._

@ -0,0 +1,9 @@
title: "AMI Joins OpenPOWER"
date: "2015-06-03"
- "press-releases"
- "blogs"

@ -0,0 +1,11 @@
title: "As Computing Tasks Evolve, Infrastructure Must Adapt"
date: "2014-06-11"
- "industry-coverage"
- "blogs"

The litany of computing buzzwords has been repeated so often that weve almost glazed over: mobile, social, cloud, crowd, big data, analytics.  After a while they almost lose their meaning.

Taken together, though, they describe the evolution of computing from its most recent incarnation — single user, sitting at a desk, typing on a keyboard, watching a screen, local machine doing all the work — to a much more amorphous activity that involves a whole new set of systems, relationships, and actions.

@ -0,0 +1,67 @@
title: "Were Attending the OpenPOWER Developer Congress — Heres Why You Should, Too. Insights from Nimbix, Mellanox, and Xilinx"
date: "2017-05-12"
- "blogs"
- "mellanox"
- "xilinx"
- "openpower-foundation"
- "openpower-foundation-developer-congress"
- "opfdevcon17"
- "nimbix"

Prominent OpenPOWER Foundation members have provided the reasons theyre taking time out of their busy days to support the [OpenPOWER Developer Congress]( and send their experts and team members.

This is why YOU should attend too!

## **Nimbix Enables On-Demand Cloud for Developers**

### **Why [Nimbix]( is Participating in the OpenPOWER Developer Congress**

As the leading public cloud provider for OpenPOWER and Power systems, Nimbix has embraced its role as a member in the OpenPOWER Foundation. Nimbix enables ISVs to get their applications ported and running on the Power architecture, and feels a responsibility to help the OpenPOWER community. This is what the company signed up for when it became a Silver-level member of the OpenPOWER Foundation.

Nimbix works to grow the Power ecosystem for application software and broaden the software portfolio on OpenPOWER. It facilitates this by:

- Providing ISVs and developers a Continuous Integration / Continuous Deployment (CI/CD) pipeline to deploy their source code on Power.
- Providing the ability to not just port, but to test at scale, on a supercomputer in the cloud that runs on OpenPOWER technology.
- Enabling ISVs that decide to go to market with their applications in the cloud to sell those applications directly in the Nimbix cloud.

### **What is Nimbix Bringing to the Developer Congress?**

“Nimbix is proud to support the OpenPOWER Developer Congress by providing resources to support Congress activities,” said Leo Reiter, CTO of Nimbix. “Through our support, we will be enabling the on-demand cloud infrastructure for the Congress so that all of the sessions and tracks can do their development in the cloud on the OpenPOWER platform.”

Leo will be part of the team instructing cloud development and porting to Power tracks at the Congress. "As an OpenPOWER Foundation member,” Leo said,, “I will be working with participants to get their applications running on Power in the cloud and providing them with tips and tools they can use to continue developing OpenPOWER applications post-conference.”

\[caption id="attachment\_4790" align="aligncenter" width="880"\][![OpenPOWER Developer Congress](images/OPDC-Web-Banner.jpg)]( [Click here to register for the OpenPOWER Developer Congress]( - May 22-25 in San Francisco.\[/caption\]

## **Mellanox Educates on Caffe, Chainer, and TensorFlow**

### **Why [Mellanox]( is Participating in the OpenPOWER Developer Congress**

Mellanox is not only a founding member of the OpenPOWER Foundation, but also a founding member of its Machine Learning Work Group.  AI / cognitive computing will improve our quality of life, drive emerging markets, and surely play a leading role in global economics. But to achieve real scalable performance with AI, being able to leverage cutting-edge interconnect capabilities is paramount. Typical vanilla networking just doesnt scale, so its important that developers are aware of the additional performance that can be achieved by understanding the critical role of the network.

Because Deep Learning applications are well-suited to exploit the POWER architecture, it is also extremely important to have an advanced network that unlocks the scalable performance of deep learning systems, and that is where the Mellanox interconnect comes in. The benefits of RDMA, ultra-low latency, and In-Network Computing deliver an optimal environment for data-ingest at the critical performance levels required by POWER-based systems.

Mellanox is committed to working with the industrys thought leaders to drive technologies in the most open way. Its core audience has always been end users — understanding their challenges and working with them to deliver real solutions. Today, more than ever, the developers, data-centric architects, and data scientists are the new generation of end users that drive the data center. They are defining the requirements of the data center, establishing its performance metrics, and delivering the fastest time to solution by exploiting the capabilities of the OpenPOWER architecture.  Mellanox believes that participating in the OpenPOWER Developer Congress gives the company an opportunity to educate developers on its state-of-art-networking and also demonstrates its commitment to innovation with open development and open standards.

### **What is Mellanox Bringing to the Developer Congress?**

Mellanox will provide on-site expertise to discuss the capabilities of Mellanox Interconnect Solutions. Dror Goldenberg, VP of Software Architecture at Mellanox, will be present to further dive into areas of machine learning acceleration and the frameworks that already take advantage of Mellanox capabilities, such as Caffe, Chainer, TensorFlow, and others.

Mellanox is the interconnect leader in AI / cognitive computing data centers, and already accelerates machine learning frameworks to achieve from 2x to 18x speedup for image recognition, NLP, voice recognition, and more. The companys goal is to assist developers with their applications to achieve maximum scalability on POWER-based systems.

## **Xilinx Offers Experts in FPGAs and Machine Learning Algorithms**

### **Why [Xilinx]( is Participating in the OpenPOWER Developer Congress?**

Xilinx, as a Platinum-level member of the OpenPOWER Foundation, looks forward to supporting the Foundations outreach activities. The company particularly likes the format of the upcoming OpenPOWER Developer Congress, because its focused on developers and provides many benefits developers will find helpful.

Xilinx appreciates the unique nature of the Congress, in that it provides developers the opportunity to get up close to the technology and in some cases, work on it directly. It also allows developers to make good connections with other companies who participate in the Congress — something that can be very beneficial as they return to their day-to-day work.

Companies that choose to participate by providing instruction at the Congress get an opportunity to talk with developers first hand, and receive feedback on their product offerings. Conversely, the developers have an opportunity to provide feedback on products and influence what platforms (everything OpenPOWER) are going to look like as they mature.

### **What is Xilinx bringing to the Developer Congress?**

Xilinx will be bringing system architects and solution architects who will work hands-on with developers to create solutions and solve problems. These experts understand both FPGAs and machine learning algorithms, which fits nicely with the OpenPOWER Developer Congress agenda.

@ -0,0 +1,33 @@
title: "Avnet Joins OpenPOWER Foundation"
date: "2015-01-15"
- "press-releases"
- "blogs"

PHOENIX, Jan 15, 2015 (BUSINESS WIRE) -- [Avnet, Inc]( (NYSE: [AVT](, a leading global technology distributor, today announced that it has joined the OpenPOWER Foundation, an open development alliance based on IBMs POWER microprocessor architecture. Working with the OpenPOWER Foundation, Avnet will help partners and customers innovate across the full hardware and software stack to build customized server, networking and storage hardware solutions best suited to the high-performance Power architecture.

The OpenPOWER Foundation was established in 2013 as an open technical membership organization that provides a framework for open innovation at both the hardware and software levels. IBMs POWER8 processor serves as the hardware foundation, while the system software structure embraces key open source technologies including KVM, Linux and OpenStack.

“Working with the OpenPOWER Foundation complements Avnets long-standing relationship with IBM across the enterprise, from the components level to the data center,” said Tony Madden, Avnet senior vice president, global supplier business executive. “With the accelerated pace of change in technology, membership in the OpenPOWER Foundation provides an excellent avenue for us to work alongside other market leaders to deploy open Power technology, providing customers and partners with the technology infrastructure they need to evolve and grow their businesses.”

As an OpenPOWER Foundation member, Avnet will provide channel distribution and integration services for OpenPOWER compatible offerings, enabling its partners and customers to focus on innovation, optimizing operational efficiency and enhancing profitability.

[Click to Tweet]( .@Avnet joins #OpenPOWER Foundation [](

Follow Avnet on Twitter: [@Avnet](

Connect with Avnet on LinkedIn or Facebook:[]( or [](

Read more about Avnet on its blogs: [](

**About Avnet, Inc.**

Avnet, Inc. (NYSE: [AVT](, a Fortune 500 company, is one of the largest distributors of electronic components, computer products and embedded technology serving customers globally. Avnet accelerates its partners success by connecting the worlds leading technology suppliers with a broad base of customers by providing cost-effective, value-added services and solutions. For the fiscal year ended June 28, 2014, Avnet generated revenue of $27.5 billion. For more information, visit[](

All brands and trade names are trademarks or registered trademarks, and are the properties of their respective owners. Avnet disclaims any proprietary interest in marks other than its own.

SOURCE: Avnet, Inc.

Avnet, Inc. Joal Redmond, +1 480-643-5528 []( or Brodeur Partners, for Avnet, Inc. Marcia Chapman, +1 480-308-0284 [](

@ -0,0 +1,22 @@
title: "Barcelona Supercomputing Center Adds HPC Expertise to OpenPOWER"
date: "2016-10-27"
- "blogs"
- "featured"

_Eduard Ayguadé, Computer Sciences Associate Director at BSC_

![Barcelona Supercomputing Center joins OpenPOWER](images/BSC-blue-large-1024x255.jpg)

The [Barcelona Supercomputing Center]( (BSC) is Spains National Supercomputing facility. Our mission is to investigate, develop and manage information technologies to facilitate scientific progress. It was officially constituted in April 2005 with four scientific departments: Computer Sciences, Computer Applications in Science and Engineering, Earth Sciences and Life Sciences. In addition, the Centers Operations department manages MareNostrum, one of the most powerful supercomputers in Europe. The activities in these departments are complementary to each other and very tightly related, setting up a multidisciplinary loop: computer architecture, programming models, runtime systems and resource managers, performance analysis tools, algorithms and applications in the above mentioned scientific and engineering areas.

Joining the OpenPOWER foundation will allow BSC to advance its mission, improving the way we contribute to the scientific and technological HPC community, and at the end, serve society. BSC plans to actively participate in the different working groups in OpenPOWER with the objective of sharing our research results, prototyping implementations and know-how with the other members to influence the design of future systems based on the POWER architecture. As member of OpenPOWER, BSC hopes to gain visibility and opportunities to collaborate with other leading institutions in high performance architectures, programming models and applications.

In the framework of the current [IBM-BSC Deep Learning Center]( initiative, BSC and IBM will collaborate in research and development projects on the Deep Learning domain, an essential component of cognitive computing, with focus on the development of new algorithms to improve and expand the cognitive capabilities of deep learning systems. Additionally, the center will also do research on flexible computing architectures fundamental for big data workloads like data centric systems and applications.

Researchers at BSC have been working on policies to optimally manage the hardware resources available in POWER-based systems from the runtime system, including prefetching, multithreading degree and energy-securing. These policies are driven by the information provided by the per-task (performance and power) counters available in POWER architectures and control knobs. Researchers at BSC have also been collaborating with the compiler teams at IBM in the implementation and evolution of the [OpenMP programming model]( to support accelerators, evaluating new SKV (Scalable Key-Value) storage capabilities on top of novel memory and storage technologies, including bug reporting and fixing, using Smufin, one of the key applications at BSC to support personalized medicine, or exploring NUMA aware placement strategies in POWER architectures to deploy containers based on the workloads characteristics and system state.

Today, during the [OpenPOWER Summit Europe]( in Barcelona, the director of BSC, Prof. Mateo Valero, will present the mission and main activities of the Center and the different departments at the national, European and international level. After that, he will present the work that BSC is conducting with different OpenPOWER members, including IBM, NVIDIA, Samsung, and Xilinx, with a special focus on the BSC and IBM research collaboration in the last 15 years.

@ -0,0 +1,50 @@
title: "Barreleye G2 and Zaius Motherboard Samples Showcased at the OpenPOWER Summit"
date: "2018-05-14"
- "blogs"
- "google"
- "rackspace"
- "openpower-summit"
- "barreleye"
- "zaius"
- "openpower-foundation"

By Adi Gangidi

\[caption id="attachment\_5438" align="aligncenter" width="267"\][![Barreleye G2 Accelerator server](images/barreleye-267x300.jpg)]( Barreleye G2 Accelerator server\[/caption\]

Rackspace showcased brand new Zaius PVT motherboard samples and Barreleye G2 servers at the [OpenPOWER Summit](, demonstrating industry leading capabilities.

## **Collaboration between Google and Rackspace**

The Zaius/Barreleye G2 OpenPOWER platform was originally [announced]( at the OpenPOWER Summit in 2016 as a collaborative effort between Google and Rackspace. Since then, we have made steady progress on the development of this platform. Weve navigated through engineering validation and test (EVT), design validation and test (DVT) and made various optimizations to the design resulting in refined solution.

We continue to [qualify]( various OpenCAPI/NVLink 2.0 adapters and play with frameworks ([SNAP]([PowerAI]( that enable easy adoption of these adapters.

## **Zaius motherboard**

Our Zaius motherboard has just entered the production validation and test stage, which reflects our confidence in this design and our continued effort to bring OpenCAPI/NVLink 2.0/PCIe Gen4 accelerators to datacenters via this server housing IBM Power9 processors.

\[caption id="attachment\_5439" align="aligncenter" width="625"\][![PVT Zaius Motherboard](images/PVT-1024x651.png)]( PVT Zaius Motherboard\[/caption\]

## **CPU-GPU NVLink 2.0 Interposer Board**

Also at the OpenPOWER Summit, Rackspace displayed our unique, disaggregated implementation of CPU-GPU NVLink 2.0 interposer board. This board is ideal for artificial intelligence and deep learning applications.

Further, when combined with PCIe Gen4, we believe the Interposer Board will provide reference in the server industry for solving two bottlenecks:

1. The slow CPU-GPU link
2. Slow server-to-server network speed

Both bottlenecks are commonplace today in PCIe Gen3 servers.

\[caption id="attachment\_5440" align="aligncenter" width="625"\][![SlimSAS to SXM2 Interposer for support Volta GPU and FPGA HBM2 Card](images/SlimSAS-1024x445.jpg)]( SlimSAS to SXM2 Interposer for support Volta GPU and FPGA HBM2 Card\[/caption\]

Conference attendees also saw first-in-industry technology demos from Rackspace, including a demo of the worlds first production-ready PCIe Gen4 NVM Express System. You can read about that [here](

Rackspace expects to do limited access customer betas later this year, based on Barreleye G2 Accelerator servers.

Customers interested in participating, please reach out by emailing [](

@ -0,0 +1,50 @@
title: "Big Data and AI: Collaborative Research and Teaching Initiatives with OpenPOWER"
date: "2020-02-13"
- "blogs"
- "ibm"
- "power"
- "hpc"
- "big-data"
- "summit"
- "ai"
- "oak-ridge-national-laboratory"

[Arghya Kusum Das](, Ph.D., Asst. Professor, UW-Platteville


In the Department of Computer Science and Software Engineering (CSSE) at the University of Wisconsin at Platteville, I work closely with hardware system designers to improve the quality of the institutes research and teaching.

Recently, I have engaged with the OpenPOWER community to improve research efforts and also to help build collaborative education platforms.

## **Accelerating Research on POWER**

As a collaborative academic partner with the OpenPOWER Foundation, I have participated and led sessions at various OpenPOWER Academic workshops. These workshops gave me an opportunity to learn about various features around OpenPOWER and also provided great networking opportunities with many research organizations and customers.

As part of this, I submitted a research proposal to [Oak Ridge National Laboratory]( for allocation in the Summit supercomputing cluster to accelerate my research. With this allocation, I focus on accurate, de novo assembly and binning of metagenomic sequences, which can become quite complex with multiple genomes in mixed sequence reads. The computation process is also challenged by the huge volume of the datasets.

Our assembly pipeline involves two major steps. First, a de Bruijn graph-based de novo assembly and second, binning the whole genomes to operational taxonomic units utilizing deep learning techniques. In conjunction with large data sets, these deep learning technologies and scientific methods for big data genome analysis demand more compute cycles per processor than ever before. Extreme I/O performance is also required.

The final goal of this project is to accurately assemble terabyte-scale metagenomic leveraging IBM Power9 technology along with Nvidia GPU and NVLink.

## **Building a Collaborative Future**

One of our collaborative visions is to spread the HPC education to meet the worldwide need for experts in corresponding fields. As a part of this vision, I recognized the importance of online education and started working on a pilot project to develop an innovative, online course curriculum for these cutting-edge domains of technology.

To further facilitate these visions, Im also working on developing a collaborative, online education platform where students can receive lectures and deepen their theoretical knowledge, but also get hands-on experience in cutting edge infrastructure.

Im interested in collaboration with bright minds including faculties, students and professionals to materialize this online education goal.

## **Future Workshops and Hackathons**

As a part of this collaborative initiative, I plan to organize big data workshops and hackathons, which will provide a forum for disseminating the latest research, as well as provide a platform for students to get hands-on learning and engage in practical discussion about big data and AI-based technologies.

The first of these planned events is the OpenPOWER Big Data and AI workshop taking place on April 7th, 2020. Attendees will hear about IBM and OpenPOWER partnerships, cutting-edge research on big data, AI, and HPC, including outreach, industry research, and other initiatives.

You can register for the workshop [**here**](

Cant wait to see you there!

@ -0,0 +1,10 @@
title: "Blog | IT powers new business models"
date: "2014-07-02"
- "blogs"

People and businesses today are rapidly adopting new technologies and devices that are transforming the way they interact with each other and their data.

This digital transformation generates 2.5 quintillion bytes of data associated with the proliferation of mobile devices, social media and cloud computing, and drives tremendous growth opportunity.

@ -0,0 +1,16 @@
title: "Members can now request early access to Tyan reference board"
date: "2014-07-10"
- "blogs"
- "openpower"
- "power8"
- "tyan"
- "atx"
- "debian"

![Tyan reference Board](images/Tyan-reference-Board-300x180.jpg) We are excited with the progress that the OpenPOWER Foundation member companies have made since our public launch in San Francisco back in April. Members can now request early access to the Tyan reference board shown below by emailing [Bernice Tsai]( at Tyan. This is a single socket, ATX form factor, Power8 Motherboard that can members can bring up an [Debian Linux Distribution]( (Little Endian) to start innovating with. We look forward to seeing the great ideas that will be generated by working together!


@ -0,0 +1,24 @@
title: "New OpenPOWER Member Brocade Showcases Work at Mobile World Congress"
date: "2016-02-19"
- "blogs"
- "featured"

_By Brian Larsen, Director, Partner Business Development, Brocade![logo-brocade-black-red-rgb](images/logo-brocade-black-red-rgb.jpg)_

In my 32 year career in the IT industry there has never been a better time to embrace the partnership needed to meet client requirements, needs and expectations.  Brocade has built its business on partnering with suppliers who deliver enterprise class infrastructure in all the major markets. This collaborative mindset is what led us to the OpenPOWER Foundation, where an eco-system of over 180 vendors, suppliers, and researchers can build new options for client solutions.

Brocade recognizes that OpenPOWER platforms are providing choice and with that choice comes the need to enable those platforms with the same networking capabilities that users are familiar with.  If you have been in a cave for the last eight years, you may not know that Brocade has broken out of its mold of being a fibre channel switch vendor and now supports a portfolio of IP networking platforms along with innovative solutions in Software Defined Networking (SDN) and Network Function Virtualization (NFV). Our work will allow our OpenPOWER partners to design end to end solutions that include both storage and IP networked solutions.  Use cases for specific industries can be developed for high-speed network infrastructure for M2M communication or compute to storage requirements.  As target use cases evolve, networking functionality could transform from a physical infrastructure to a virtual architecture where the compute platform is a critical & necessary component.

![OpenPOWER Venn Diagram](images/OpenPOWER-Venn-Diagram.jpg)

The OpenPOWER Foundations [membership has exploded]( since its inception and is clearly making a mark on new data center options for users who expect peak performance to meet todays demanding IT needs.  As Brocades SVP and GM of Software Networking, Kelly Herrell says, “OpenPOWER processors provide innovation that powers datacenter and cloud workloads”.  Enterprise Datacenters and Service Providers (SP) markets are key areas of focus for Brocade and by delivering on its [promise of the “New IP”]( businesses will be able to transition to more automation, accelerated service delivery and new revenue opportunities.

Brocade will be at [Mobile World Congress]( in Barcelona and [IBMs InterConnect Conference]( in Las Vegas from February 22-25th, come see us and let us show you the advantages of being an eco-system partner with us.

* * *

_![Brian Larsen Brocade](images/Brian-Larsen-Brocade-150x150.jpg)Brian Larsen joined Brocade in July 1991 and has more than 29 years of professional experience in high-end processing, storage, disaster recovery, Cloud, virtualization and networking environments. Larsen is the Director of Partner Business Development Executive responsible for solution and business development within all IBM divisions. For the last 5 years, he has focused on both service provider and enterprise markets with specific focus areas in: Cloud, Virtualization, Software Defined Networking (SDN), Network Function Virtualization (NFV), Software Defined Storage (SDS) and Analytics solutions._

@ -0,0 +1,8 @@
title: "Canonical Supporting IBM POWER8 for Ubuntu Cloud, Big Data"
date: "2014-06-27"
- "blogs"

If Ubuntu Linux is to prove truly competitive in theOpenStack cloud and Big Data worlds, it needs to run on more than x86 hardware. And that's whatCanonical achieved this month, with the announcement of full support for IBM POWER8machines on Ubuntu Cloud and Ubuntu Server.

@ -0,0 +1,81 @@
title: "Using CAPI and Flash for larger, faster NoSQL and analytics"
date: "2015-09-25"
- "blogs"
- "openpower"
- "power8"
- "featured"
- "capi"
- "big-data"
- "databases"
- "ubuntu"
- "redis-labs"
- "capi-series"

_By Brad Brech, Distinguished Engineer, IBM Power Systems Solutions_

## [![CAPI Flash Benefits Infographic](images/CAPI_Flash_Infographic-475x1024.jpg)]( Challenge

Suppose youre a game developer with a release coming up. If things go well, your user base could go from zero to hundreds of thousands in no time. And these gamers expect your app to capture and store their data, so the game always knows who's playing and their progress in the game, no matter where they log in. Youre implementing an underlying database to serve these needs.

Oh—and youve got to do that without adding costly DRAM to existing systems, and without much of a budget to build a brand-new large shared memory or distributed multi-node database solution. Dont forget that you cant let your performance get bogged down with IO latency from a traditionally attached flash storage array.

More and more, companies are choosing NoSQL over traditional relational databases. NoSQL offers simple data models, scalability, and exceptionally speedy access to in-memory data. Of particular interest to companies running complex workloads is NoSQL's high availability for key value stores (KVS) like [Redis]( and MemcacheDB, document stores such as mongoDB and couchDB, and column stores Cassandra and BigTable.

## Computing Challenge

NoSQL isn't headache-free.

Running NoSQL workloads fast enough to get actionable insights from them is expensive and complex. That requires your business either to invest heavily in a shared-memory system or to set up a multi-node networked solution that adds complexity and latency when accessing your valuable data.

Back to our game developer and their demanding gamers. As the world moves to the cloud, developers need to offer users rapid access to online content, often tagged with metadata. Metadata needs low response times as it is constantly being accessed by users. NoSQL provides flexibility for content-driven applications to not only provide fast access to data but also store diverse data sets. That makes our game developer an excellent candidate for using CAPI-attached Flash to power a NoSQL database.

## The Solution

Here's where CAPI comes in. Because CAPI allows you to attach devices with memory coherency at incredibly low latency, you can use CAPI to affix flash storage that functions more like extended block system memory for larger, faster NoSQL. Coming together, OpenPOWER Foundation technology innovators including [Redis Labs](, [Canonical](, and [IBM]( created this brilliant new deployment model, and they built [Data Engine for NoSQL](—one of the first commercially available CAPI solutions.

CAPI-attached flash enables great things. By CAPI-attaching a 56 TB flash storage array to the POWER8 CPU via an FPGA, the application gets direct access to a large flash array with reduced I/O latency and overhead compared to standard I/O-attached flash. End-users can:

- _Create a fast path to a vast store of memory_
- _Reduce latency by cutting the number of code instructions to retrieve data from 20,000 to as low as 2000, by eliminating I/O overhead[1](#_ftn1)_
- _Increase performance by increasing bandwidth by up to 5X on a per-thread basis[1](#_ftn1)_
- _Lower deployment costs by 3X through massive infrastructure consolidation[2](#_ftn2)_
- _Cut TCO with infrastructure consolidation by shrinking the number of nodes needed from 24 to 1[2](#_ftn2)_

<iframe src=";showinfo=0" width="560" height="315" frameborder="0" allowfullscreen="allowfullscreen"></iframe>

## Get Started with Data Engine for NoSQL

Getting started is easy, and our goal is to provide you with the resources you need to begin. This living list will continue to evolve as we provide you with more guidance, information, and use cases, so keep coming back to be sure you can stay up to date.

### Learn more about the Data Engine for NoSQL:

- [Data Engine for NoSQL Solution Brief](
- [Data Engine for NoSQL Whitepaper](

### Deploy Data Engine for NoSQL:

- [Contact IBM about Data Engine for NoSQL]( to build the Data Engine for NoSQL configuration for you
- [Get community support]( for your solutions and share results with your peers on the [CAPI Developer Community](
- Reach out to the OpenPOWER Foundation community on [Twitter](, [Facebook](, and [LinkedIn]( along the way

Keep coming to see blog posts from IBM and other OpenPOWER Foundation partners on how you can use CAPI to accelerate computing, networking and storage.

- [CAPI Series 1: Accelerating Business Applications in the Data-Driven Enterprise with CAPI](
- [CAPI Series 3: Interconnect Your Future with Mellanox 100Gb EDR Interconnects and CAPI](
- [CAPI Series 4: Accelerating Key-value Stores (KVS) with FPGAs and OpenPOWER](


* * *

**_![BradBrech](images/BradBrech.jpg)About Brad Brech_**

_Brad Brech is a Distinguished Engineer and the CTO of POWER Solutions in the IBM Systems Division. He is currently focused on POWER and OpenPOWER and solutions and is the Chief Engineer for the CAPI attached Flash solution enabler. His responsibilities include technical strategy, solution identification, and working delivery strategies with solutions teams. Brad is an IBM Distinguished Engineer, a member of the IBM Academy of Technology and past Board member of The Green Grid._

[\[1\]](#_ftnref1)Based on performance analysis comparing typical I/O Model flow (PCIe) to CAPI Attached Coherent Model flow.

[\[2\]](#_ftnref2) Based on competitive system configuration cost comparisons by IBM and Redis Labs.

@ -0,0 +1,75 @@
title: "Accelerating Business Applications in the Data-Driven Enterprise with CAPI"
date: "2015-09-10"
- "blogs"
- "openpower"
- "power"
- "featured"
- "capi"
- "acceleration"
- "fpga"
- "performance"
- "capi-series"

_By Sumit Gupta, VP, HPC & OpenPOWER Operations at IBM_ _This blog is part of a series:_ _[Pt 2: Using CAPI and Flash for larger, faster NoSQL and analytics]( _[Pt 3: Interconnect Your Future with Mellanox 100Gb EDR Interconnects and CAPI]( _[Pt 4: Accelerating Key-value Stores (KVS) with FPGAs and OpenPOWER](

Every 48 hours, the world generates as much data as it did from the beginning of recorded history through 2003.

The monumental increase in the flow of data represents an untapped source of insight for data-driven enterprises, and drives increasing pressure on computing systems to endure and analyze it. But today, just raising processor speeds isn't enough. The data-driven economy demands a computing model that delivers equally data-driven insights and breakthroughs at the speed the market demands.

[![CAPI Logo](images/CAPITechnology_Color_Gradient_Stacked_-300x182.png)]( architecture includes a technology called Coherent Accelerator Processor Interface (CAPI) that enables systems to crunch through the high volume of data by bringing compute and data closer together. CAPI is an interface that enables close integration of devices with the POWER CPU and gives coherent access to system memory. CAPI allows system architects to deploy acceleration in novel ways for an application and allow them to rethink traditional system designs.

\[caption id="attachment\_1982" align="aligncenter" width="625"\][![CAPI-attached vs. traditional acceleration](images/IBMNR_OPF_CAPI_BlogPost1_Image-02-1024x531.jpg)]( CAPI allows attached accelerators to deeply integrate with POWER CPUs\[/caption\]

CAPI-attached acceleration has three pillars: accelerated computing, accelerated storage, and accelerated networking. Connected coherently to a POWER CPU to give them direct access to the CPUs system memory, these techniques leverage accelerators like FPGAs and GPUs, storage devices like flash, and networking devices like Infiniband.   These devices, connected via CAPI, are programmable using simple library calls that enable developers to modify their applications to more easily take advantage of accelerators, storage, and networking devices. The CAPI interface is available to members of the OpenPOWER foundation and other interested developers, and enables a rich ecosystem of data center technology providers to integrate tightly with POWER CPUs to accelerate applications.

## **What can CAPI do?**

CAPI has had an immediate effect in all kinds of industries and for all kinds of clients:

- **[Healthcare](** Create customized cancer treatment plans personalized to an individuals unique genetic make-up.
- **Image and video processing:** Facial expression recognition that allows retailers to analyze the facial reactions their shoppers have to their products.
- [**Database acceleration and fast storage**](**:** accelerate the performance of flash storage to allow users to search databases in near real-time for a fraction of the cost.
- **[Risk Analysis in Finance](** Allow financial firms to monitor their risk in real-time with greater accuracy.

## **The CAPI Advantage**

CAPI can be used to:

- **Accelerate Compute** by leveraging a CAPI-attached FPGA to run, for example, Monte Carlo analysis or perform Vision Processing. The access to the IBM POWER CPUs memory address space is a programmer's dream.
- **Accelerate Storage** by using CAPI to attach flash that can be written to as a massive memory space instead of storage---a process that slashes latency compared to traditional storage IO.
- **Accelerate Networking** by deploying CAPI-attached network accelerators for faster, lower latency edge-of-network analytics.

The intelligent and close integration enabled by CAPI with IBM POWER CPUs removes much of the latency associated with the I/O bus on other platforms (PCI-E). It also makes the accelerator a peer to the POWER CPU cores, allowing it to access the accelerator natively.  Consequently, a very small investment can help your system perform better than ever.\_aHRo

## **Supported by the OpenPOWER Foundation Community**

We often see breakthroughs when businesses open their products to developers, inviting them to innovate. To this end IBM helped create the OpenPOWER Foundation, now with 150 members, dedicated to innovating around the POWER CPU architecture.

IBM and many of our Foundation partners are committed to developing unique, differentiated solutions leveraging CAPI. Many more general and industry-specific solutions are on the horizon. By bringing together brilliant minds from our community of innovators, the possibilities for customers utilizing CAPI technology are endless.

## **Get Started with CAPI**

Getting started with CAPI is easy, and our goal is to provide you with the resources you need to begin. This living list will continue to evolve as we provide you with more guidance, information, and use cases, so keep coming back to be sure you can stay up to date.

1. Learn more about CAPI:
- [Coherent Accelerator Processor Interface (CAPI) for POWER8 Systems](
2. Get the developer kits:
- [Alpha Data CAPI Developer Kit](
- [Nallatech CAPI Developer Kit](
3. Get support for your solutions and share results with your peers on the [CAPI Developer Community](

Along the way reach out to us on [Twitter](, [Facebook](, and [LinkedIn](

_This blog is part of a series:_ _[Pt 2: Using CAPI and Flash for larger, faster NoSQL and analytics]( _[Pt 3: Interconnect Your Future with Mellanox 100Gb EDR Interconnects and CAPI]( _[Pt 4: Accelerating Key-value Stores (KVS) with FPGAs and OpenPOWER](

* * *

**_[![Sumit Gupta](images/sumit-headshot.png)]( Sumit Gupta_**

_Sumit Gupta is Vice President, High Performance Computing (HPC) Business Line Executive and OpenPOWER Operations. With more than 20 years of experience, Sumit is a recognized industry expert in the fields of HPC and enterprise data center computing. He is responsible for business management of IBM's HPC business and for operations of IBM's OpenPOWER initiative._

@ -0,0 +1,74 @@
title: "CAPI SNAP: The Simplest Way for Developers to Adopt CAPI"
date: "2016-11-03"
- "capi-series"
- "blogs"
- "featured"

_By Bruce Wile, CAPI Chief Engineer and Distinguished Engineer, IBM Power Systems_

Last week at OpenPOWER Summit Europe, [we announced a brand-new Framework]( designed to make it easy for developers to begin using CAPI to accelerate their applications. The CAPI Storage, Network, and Analytics Programming Framework, or CAPI SNAP, was developed through a multi-company effort from OpenPOWER members and is now in alpha testing with multiple early adopter partners.

But what exactly puts the “snap” in CAPI SNAP? To answer that, I wanted to give you all a deeper look into the magic behind CAPI SNAP.  The framework extends the CAPI technology through the simplification of both the API (call to the accelerated function) and the coding of the accelerated function.  By using CAPI SNAP, your application gains performance through FPGA acceleration and because the compute resources are closer to the vast amounts of data.

## A Simple API

ISVs will be particularly interested in the programming enablement in the framework. The framework API makes it a snap for an application to call for an accelerated function. The innovative FPGA framework logic implements all the computer engineering interface logic, data movement, caching, and pre-fetching work—leaving the programmer to focus only on the accelerator functionality.

Without the framework, an application writer must create a runtime acceleration library to perform the tasks shown in Figure 1.

\[caption id="attachment\_4299" align="aligncenter" width="762"\]![Figure 1: Calling an accelerator using the base CAPI hardware primitives](images/CAPI-SNAP-1.png) Figure 1: Calling an accelerator using the base CAPI hardware primitives\[/caption\]

But now with CAPI SNAP, an application merely needs to make a function call as shown in Figure 2. This simple API has the source data (address/location), the specific accelerated action to be performed, and the destination (address/location) to send the resulting data.

\[caption id="attachment\_4300" align="aligncenter" width="485"\]![Figure 2: Accelerated function call with CAPI SNAP](images/CAPI-SNAP-2.png) Figure 2: Accelerated function call with CAPI SNAP\[/caption\]

The framework takes care of moving the data to the accelerator and putting away the results.

## Moving the Compute Closer to the Data

The simplicity of the API parameters is elegant and powerful. Not only can source and destination addresses be coherent system memory locations, but they can also be attached storage, network, or memory addresses. For example, if a framework card has attached storage, the application could source a large block (or many blocks) of data from storage, perform an action such as a search, intersection, or merge function on the data in the FPGA, and send the search results to a specified destination address in main system memory. This method has large performance advantages compared to the standard software method as shown in Figure 3.

\[caption id="attachment\_4301" align="aligncenter" width="625"\]![Figure 3: Application search function in software (no acceleration framework)](images/CAPI-SNAP-3-1024x538.png) Figure 3: Application search function in software (no acceleration framework)\[/caption\]

Figure 4 shows how the source data flows into the accelerator card via the QSFP+ port, where the FPGA performs the search function. The framework then forwards the search results to system memory.

\[caption id="attachment\_4302" align="aligncenter" width="625"\]![Figure 4: Application with accelerated framework search engine](images/CAPI-SNAP-4-1024x563.png) Figure 4: Application with accelerated framework search engine\[/caption\]

The performance advantages of the framework are twofold:

1. By moving the compute (in this case, search) closer to the data, the FPGA has a higher bandwidth access to storage.
2. The accelerated search on the FPGA is faster than the software search.

Table 1 shows a 3x performance improvement between the two methods. By moving the compute closer to the data, the FPGA has a much higher ingress (or egress) rate versus moving the entire data set into system memory.

\[table id=19 /\]

## Simplified Programming of Acceleration Actions

The programming API isnt the only simplification in CAPI SNAP. The framework also makes it easy to program the “action code” on the FPGA. The framework takes care of retrieving the source data (whether its in system memory, storage, networking, etc) as well as sending the results to the specified destination. The programmer, writing in a high-level language such as C/C++ or Go, needs only to focus on their data transform, or “action.” Framework compatible compilers translate the high-level language to Verilog, which in turn gets synthesized using Xilinxs Vivado toolset.

With CAPI SNAP, the accelerated search code (searching for one occurrence) is this simple:

for(i=0; i < Search.text\_size; i++){