A tiny Open POWER ISA softcore written in VHDL 2008
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Paul Mackerras fa77a6f683 core: Implement the mcrxrx instruction
This also removes OP_MCRXR, as the mcrxr instruction was removed in
version 3.0B of the Power ISA, having been phased-out for the server
architecture since v2.02.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
.github/workflows Create github artifacts for ECP5 devices 4 years ago
constraints
fpga corefile/nexys_video: Parameter fixes 4 years ago
hello_world Enhance hello_world 4 years ago
include syscon: Add flag to indicate the timebase frequency 4 years ago
lib console: Add support for the 16550 UART 4 years ago
litedram Merge pull request #213 from ozbenh/uart16550 4 years ago
liteeth liteeth: Hook up LiteX LiteEth ethernet controller 4 years ago
media
micropython tests: Add updated micropython build with 16550 support 4 years ago
openocd flash-arty: update error message (#203) 5 years ago
rust_lib_demo console: Cleanup console API 4 years ago
scripts core: Implement the mcrxrx instruction 4 years ago
sim-unisim
tests tests: Add tests for the PVR 4 years ago
uart16550 Add uart16550 files from fusesoc 4 years ago
verilator
.gitignore Add yosys builds files to gitignore 4 years ago
LICENSE
Makefile Add PLL for ECP5 device 4 years ago
README.md
cache_ram.vhdl
common.vhdl core: Implement the TAR register and the bctar instruction 4 years ago
control.vhdl execute1: Do forwarding of the CR result to the next instruction 4 years ago
core.vhdl core: Don't generate logic for log data when LOG_LENGTH = 0 4 years ago
core_debug.vhdl Make LOG_LENGTH configurable per FPGA variant 5 years ago
core_dram_tb.vhdl soc: Rename wb_dram_ctrl to wb_ext_io and rework decoding 5 years ago
core_flash_tb.vhdl soc: Don't require dram wishbones signals to be wired by toplevel 5 years ago
core_tb.vhdl soc: Don't require dram wishbones signals to be wired by toplevel 5 years ago
countzero.vhdl countzero: Faster algorithm for count leading/trailing zeroes 4 years ago
countzero_tb.vhdl
cr_file.vhdl core: Don't generate logic for log data when LOG_LENGTH = 0 4 years ago
cr_hazard.vhdl execute1: Do forwarding of the CR result to the next instruction 4 years ago
crhelpers.vhdl
dcache.vhdl dcache: Ease timing on wishbone data and byte selects 4 years ago
dcache_tb.vhdl
decode1.vhdl core: Implement the mcrxrx instruction 4 years ago
decode2.vhdl core: Don't generate logic for log data when LOG_LENGTH = 0 4 years ago
decode_types.vhdl core: Implement the mcrxrx instruction 4 years ago
divider.vhdl
divider_tb.vhdl
dmi_dtm_dummy.vhdl
dmi_dtm_tb.vhdl
dmi_dtm_xilinx.vhdl dmi: Add ASYNC_REG attribute on synchronizers (#200) 5 years ago
dram_tb.vhdl litedram: Improve dram_tb error output 5 years ago
execute1.vhdl core: Implement the mcrxrx instruction 4 years ago
fetch1.vhdl core: Implement CFAR register 4 years ago
glibc_random.vhdl
glibc_random_helpers.vhdl
gpr_hazard.vhdl core: Use a busy signal rather than a stall 5 years ago
helpers.vhdl
icache.vhdl core: Don't generate logic for log data when LOG_LENGTH = 0 4 years ago
icache_tb.vhdl core: Remove fetch2 pipeline stage 5 years ago
icache_test.bin
insn_helpers.vhdl
loadstore1.vhdl loadstore1: Better expression for store data formatting 4 years ago
logical.vhdl logical: Only do output inversion for OP_AND, OP_OR and OP_XOR 4 years ago
microwatt.core corefile/nexys_video: Parameter fixes 4 years ago
mmu.vhdl loadstore1: Generate busy signal earlier 4 years ago
multiply.vhdl execute1: Take an extra cycle for OE=1 multiply instructions 4 years ago
multiply_tb.vhdl multiplier: Generalize interface to the multiplier 4 years ago
plru.vhdl
plru_tb.vhdl
ppc_fx_insns.vhdl core: Implement a simple branch predictor 5 years ago
register_file.vhdl core: Don't generate logic for log data when LOG_LENGTH = 0 4 years ago
rotator.vhdl
rotator_tb.vhdl
sim_16550_uart.vhdl uart: Add a simulation model for the 16550 compatible UART 4 years ago
sim_bram.vhdl
sim_bram_helpers.vhdl
sim_bram_helpers_c.c
sim_console.vhdl
sim_console_c.c sim_console: Fix polling to check for POLLIN 4 years ago
sim_jtag.vhdl
sim_jtag_socket.vhdl
sim_jtag_socket_c.c
sim_no_flash.vhdl spi: Add simulation support 5 years ago
sim_pp_uart.vhdl uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl 4 years ago
sim_vhpi_c.c
sim_vhpi_c.h
soc.vhdl uart: Make 16550 the default 4 years ago
spi_flash_ctrl.vhdl spi: Send dummy clocks at boot 4 years ago
spi_rxtx.vhdl spi: Add SPI Flash controller 5 years ago
sync_fifo.vhdl litedram: Add an L2 cache with store queue 5 years ago
syscon.vhdl syscon: Add flag to indicate the timebase frequency 4 years ago
utils.vhdl
wishbone_arbiter.vhdl
wishbone_bram_tb.bin
wishbone_bram_tb.vhdl
wishbone_bram_wrapper.vhdl
wishbone_debug_master.vhdl
wishbone_types.vhdl soc: Don't require dram wishbones signals to be wired by toplevel 5 years ago
writeback.vhdl core: Use a busy signal rather than a stall 5 years ago
xics.vhdl xics: Add support for reduced priority field size 4 years ago
xilinx-mult.vhdl execute1: Take an extra cycle for OE=1 multiply instructions 4 years ago

README.md

Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

    If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.

  • Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)