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Benjamin Herrenschmidt 573b6b4bc4 soc: Rework interconnect ... This changes the SoC interconnect such that the main 64-bit wishbone out of the processor is first split between only 3 slaves (BRAM, DRAM and a general "IO" bus) instead of all the slaves in the SoC. The IO bus leg is then latched and down-converted to 32 bits data width, before going through a second address decoder for the various IO devices. This significantly reduces routing and timing pressure on the main bus, allowing to get rid of frequent timing violations when synthetizing on small'ish FPGAs such as the Artix-7 35T found on the original Arty board. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		5 years ago
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sdram_init	soc: Rework interconnect	5 years ago
arty.yml	litedram: Update to new LiteX/LiteDRAM version	5 years ago
generate.py	litedram: Update to new LiteX/LiteDRAM version	5 years ago
nexys-video.yml	litedram: Update to new LiteX/LiteDRAM version	5 years ago
wrapper-mw-init.vhdl	soc: Rework interconnect	5 years ago
wrapper-self-init.vhdl	soc: Rework interconnect	5 years ago