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fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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microwatt/scripts
History
Benjamin Herrenschmidt 8e0389b973 ram: Rework main RAM interface 
This replaces the simple_ram_behavioural and mw_soc_memory modules
with a common wishbone_bram_wrapper.vhdl that interfaces the
pipelined WB with a lower-level RAM module, along with an FPGA
and a sim variants of the latter.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 		5 years ago
..
mw_debug New C based JTAG debug tool 5 years ago
dependencies.py
…
gen_icache_tb.py icache_tb: Improve test and include test file 5 years ago
hash.py
…
run_test.sh ram: Rework main RAM interface 5 years ago
test_micropython.py ram: Rework main RAM interface 5 years ago
test_micropython_long.py ram: Rework main RAM interface 5 years ago
verific.sh Fix verific script with new VHDL files 5 years ago