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bedc9c0085
litedram ignores a couple of signals of his "pseudo-axi" port, this adds a bit of documentation around it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
4 years ago | |
|---|---|---|
| .. | ||
| fusesoc-add-files.py | ||
| litedram-wrapper-l2.vhdl | 4 years ago | |
| sim_dram_verilate.mk | ||
| sim_litedram.vhdl | ||
| sim_litedram_c.cpp | ||
| wave.gtkw | ||
| wave.opt | ||
| wave_tb.gtkw | 4 years ago | |