A tiny Open POWER ISA softcore written in VHDL 2008
 
 
 
 
 
 
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Jonathan Balkind d9bda521aa Minor refactor of icache to make less dependent on wishbone
Signed-off-by: Jonathan Balkind <jbalkind@princeton.edu>
.github/workflows Move from travis to github workflow
constraints Initial support for ghdl synthesis
fpga uart: Remove combinational loops on ack and stall signal
hello_world Makefile: Improve clean a bit
include spi: Add booting from flash to litedram init
lib sw: Properly mask syscon register fields
litedram spi: Add booting from flash to litedram init
media Add title image
micropython Update micropython
openocd flash-arty: update error message ()
rust_lib_demo console: Move console files
scripts mw_debug: Add "save" function to save memory to a file
sim-unisim Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs
tests Merge pull request from shawnanastasio/addpcis
verilator Pass clock frequency to UART sim wrapper
.gitignore gitignore: Add more exlusions
LICENSE Initial import of microwatt
Makefile spi: Add simulation support
README.md Add Makefile command line variables to enable docker and podman
cache_ram.vhdl dcache: Rework RAM wrapper to synthetize better on Xilinx
common.vhdl irq: Simplify xics->core irq input
control.vhdl core: Improve core reset
core.vhdl icache: Fix icbi potentially clobbering the icache ()
core_debug.vhdl debug: Provide a way to examine GPRs, fast SPRs and MSR
core_dram_tb.vhdl spi: Add simulation support
core_flash_tb.vhdl spi: Add simulation support
core_tb.vhdl spi: Add SPI Flash controller
countzero.vhdl countzero: Add a register to help make timing
countzero_tb.vhdl Exit cleanly from testbench on success
cr_file.vhdl Dump CTR, LR and CR on sim termination, and update our tests
cr_hazard.vhdl sprs: Store common SPRs in register file
crhelpers.vhdl crhelpers: Constraint "crnum" integer
dcache.vhdl dcache: Rework RAM wrapper to synthetize better on Xilinx
dcache_tb.vhdl Exit cleanly from testbench on success
decode1.vhdl decode1: Reformat to 4-space indentation
decode2.vhdl decode2: Reformat to 4-space indentation
decode_types.vhdl core: Do addpcis using the main adder ()
divider.vhdl execute1: Remember dest GPR, RC, OE, XER for slow operations
divider_tb.vhdl Exit cleanly from testbench on success
dmi_dtm_dummy.vhdl Fix build issue in dmi_dtm_dummy.vhdl
dmi_dtm_tb.vhdl ram: Rework main RAM interface
dmi_dtm_xilinx.vhdl dmi: Add ASYNC_REG attribute on synchronizers ()
dram_tb.vhdl litedram: Improve dram_tb error output
execute1.vhdl core: Do addpcis using the main adder ()
fetch1.vhdl Merge branch 'mmu'
fetch2.vhdl Merge branch 'mmu'
glibc_random.vhdl Reformat glibc_random
glibc_random_helpers.vhdl Reformat glibc_random
gpr_hazard.vhdl execute: Implement bypass from output of execute1 to input
helpers.vhdl execute: Copy XER[SO] to CR for cmp[i] and cmpl[i] instructions
icache.vhdl Minor refactor of icache to make less dependent on wishbone
icache_tb.vhdl icache: Fix icbi potentially clobbering the icache ()
icache_test.bin icache_tb: Improve test and include test file
insn_helpers.vhdl Implement the addpcis instruction
loadstore1.vhdl MMU: Implement reading of the process table
logical.vhdl execute: Move popcnt and prty instructions into the logical unit
microwatt.core spi: Add SPI Flash controller
mmu.vhdl MMU: Implement reading of the process table
multiply.vhdl execute1: Remember dest GPR, RC, OE, XER for slow operations
multiply_tb.vhdl Exit cleanly from testbench on success
plru.vhdl plru: Improve sensitivity list
plru_tb.vhdl Exit cleanly from testbench on success
ppc_fx_insns.vhdl sprs: Store common SPRs in register file
register_file.vhdl debug: Provide a way to examine GPRs, fast SPRs and MSR
rotator.vhdl Implement the extswsli instruction
rotator_tb.vhdl Exit cleanly from testbench on success
sim_bram.vhdl ram: Rework main RAM interface
sim_bram_helpers.vhdl ram: Rework main RAM interface
sim_bram_helpers_c.c Consolidate VHPI code
sim_console.vhdl Reformat sim_console
sim_console_c.c Consolidate VHPI code
sim_jtag.vhdl Add jtag support in simulation via a socket
sim_jtag_socket.vhdl Add jtag support in simulation via a socket
sim_jtag_socket_c.c Consolidate VHPI code
sim_no_flash.vhdl spi: Add simulation support
sim_uart.vhdl Wire up sim uart TX interrupt
sim_vhpi_c.c Consolidate VHPI code
sim_vhpi_c.h Consolidate VHPI code
soc.vhdl bram: Remove combinational loop on stall
spi_flash_ctrl.vhdl spi: Add SPI Flash controller
spi_rxtx.vhdl spi: Add SPI Flash controller
sync_fifo.vhdl litedram: Add an L2 cache with store queue
syscon.vhdl syscon: Remove combinational loop on ack and stall
utils.vhdl litedram: Add support for booting without BRAM
wishbone_arbiter.vhdl wb_arbiter: Early master selection
wishbone_bram_tb.bin ram: Rework main RAM interface
wishbone_bram_tb.vhdl Exit cleanly from testbench on success
wishbone_bram_wrapper.vhdl Add log2ceil and use it in bram code
wishbone_debug_master.vhdl wishbone_debug_master: Fix address auto-increment for memory writes
wishbone_types.vhdl soc: Rework interconnect
writeback.vhdl execute1: Simplify the interrupt logic a little
xics.vhdl irq: Simplify xics->core irq input

README.md

Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

    If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.

  • Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)