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microwatt/fpga
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Benjamin Herrenschmidt d2762e70e5 Add option to not flatten hierarchy 
Vivado by default tries to flatten the module hierarchy to improve
placement and timing. However this makes debugging timing issues
really hard as the net names in the timing report can be pretty
bogus.

This adds a generic that can be used to control attributes to stop
vivado from flattening the main core components. The resulting design
will have worst timing overall but it will be easier to understand
what the worst timing path are and address them.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
..
LICENSE Initial import of microwatt
arty_a7.xdc fpga: Arty A7's don't need multiple filesets
clk_gen_bypass.vhd Fix clk_gen_bypass
clk_gen_mcmm.vhd Improve PLL/MMCM clocks configuration
clk_gen_plle2.vhd Improve PLL/MMCM clocks configuration
cmod_a7-35.xdc Cmod A7-35 support
firmware.hex Add a few more FPGA related files
hello_world.hex Rebuild hello world assuming a 50MHz clock
mw_soc_memory.vhdl fpga/bram: Generate stall signal
nexys-video.xdc Rename a few reset signals
nexys_a7.xdc Merge pull request from antonblanchard/reset-rework2
pp_fifo.vhd fifo: Reformat
pp_soc_uart.vhd pp_uart: reformat
pp_utilities.vhd Initial import of microwatt
soc_reset.vhdl Rework SOC reset
soc_reset_tb.vhdl Rework SOC reset
toplevel.vhdl Add option to not flatten hierarchy