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Benjamin Herrenschmidt b0e15f2fb5 litedram: Make the L2 twice as tall ... This increases the number of L2 lines from 32 to 64. The BRAM usage is the same as they were only half used. There's an increase in LUTs and registers due to the extra tags and valid bits, but none of it should be in a space constrained or critical timing path. We could make it wider instead (256 bytes lines) which would reduce usage instead, but this increases the latency by 8 cycles. Something to consider once the L2 is capable of early response on miss and starting reloads from any point in a line. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		5 years ago
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fusesoc-add-files.py	litedram: Remove old "VexRiscV" based initializations	5 years ago
litedram-wrapper-l2.vhdl	litedram: Make the L2 twice as tall	5 years ago
sim_dram_verilate.mk	litedram: Add simulation support	5 years ago
sim_litedram.vhdl	litedram: Add simulation support	5 years ago
sim_litedram_c.cpp	litedram: Add simulation support	5 years ago
wave.gtkw	litedram: Add an L2 cache with store queue	5 years ago
wave.opt	litedram: Add an L2 cache with store queue	5 years ago
wave_tb.gtkw	litedram: Test bench	5 years ago