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A tiny Open POWER ISA softcore written in VHDL 2008
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Paul Mackerras b80e81e123 loadstore1: Separate address calculation for MMU to ease timing 
This computes the address sent to the MMU separately from that sent
to the dcache.  This means that the address sent to the MMU doesn't
have the delay through the lsu_sum adder, making it available earlier.
The path through the lsu_sum adder and through the MMU to the MMU
done and err outputs showed up as a critical path on some builds.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
.github/workflows Create github artifacts for ECP5 devices
constraints Initial support for ghdl synthesis
fpga corefile/nexys_video: Parameter fixes
hello_world Send line feed if we get a carriage return in hello world.
include syscon: Add flag to indicate the timebase frequency
lib console: Add support for the 16550 UART
litedram Merge pull request from ozbenh/uart16550
liteeth liteeth: Hook up LiteX LiteEth ethernet controller
media Add title image
micropython tests: Add updated micropython build with 16550 support
openocd flash-arty: update error message ()
rust_lib_demo console: Cleanup console API
scripts uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl
sim-unisim Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs
tests tests: Add tests for the PVR
uart16550 Add uart16550 files from fusesoc
verilator Pass clock frequency to UART sim wrapper
.gitignore Add yosys builds files to gitignore
LICENSE Initial import of microwatt
Makefile Add PLL for ECP5 device
README.md Add Makefile command line variables to enable docker and podman
cache_ram.vhdl dcache: Rework RAM wrapper to synthetize better on Xilinx
common.vhdl loadstore1: Generate busy signal earlier
control.vhdl execute1: Do forwarding of the CR result to the next instruction
core.vhdl core: Don't generate logic for log data when LOG_LENGTH = 0
core_debug.vhdl Make LOG_LENGTH configurable per FPGA variant
core_dram_tb.vhdl soc: Rename wb_dram_ctrl to wb_ext_io and rework decoding
core_flash_tb.vhdl soc: Don't require dram wishbones signals to be wired by toplevel
core_tb.vhdl soc: Don't require dram wishbones signals to be wired by toplevel
countzero.vhdl countzero: Faster algorithm for count leading/trailing zeroes
countzero_tb.vhdl Exit cleanly from testbench on success
cr_file.vhdl core: Don't generate logic for log data when LOG_LENGTH = 0
cr_hazard.vhdl execute1: Do forwarding of the CR result to the next instruction
crhelpers.vhdl crhelpers: Constraint "crnum" integer
dcache.vhdl dcache: Output separate done-without-error and error-done signals
dcache_tb.vhdl Exit cleanly from testbench on success
decode1.vhdl core: Don't generate logic for log data when LOG_LENGTH = 0
decode2.vhdl core: Don't generate logic for log data when LOG_LENGTH = 0
decode_types.vhdl core: Do addpcis using the main adder ()
divider.vhdl execute1: Remember dest GPR, RC, OE, XER for slow operations
divider_tb.vhdl Exit cleanly from testbench on success
dmi_dtm_dummy.vhdl Fix build issue in dmi_dtm_dummy.vhdl
dmi_dtm_tb.vhdl ram: Rework main RAM interface
dmi_dtm_xilinx.vhdl dmi: Add ASYNC_REG attribute on synchronizers ()
dram_tb.vhdl litedram: Improve dram_tb error output
execute1.vhdl core: Don't generate logic for log data when LOG_LENGTH = 0
fetch1.vhdl core: Implement CFAR register
glibc_random.vhdl Reformat glibc_random
glibc_random_helpers.vhdl Reformat glibc_random
gpr_hazard.vhdl core: Use a busy signal rather than a stall
helpers.vhdl execute: Copy XER[SO] to CR for cmp[i] and cmpl[i] instructions
icache.vhdl core: Don't generate logic for log data when LOG_LENGTH = 0
icache_tb.vhdl core: Remove fetch2 pipeline stage
icache_test.bin icache_tb: Improve test and include test file
insn_helpers.vhdl Implement the addpcis instruction
loadstore1.vhdl loadstore1: Separate address calculation for MMU to ease timing
logical.vhdl logical: Only do output inversion for OP_AND, OP_OR and OP_XOR
microwatt.core corefile/nexys_video: Parameter fixes
mmu.vhdl loadstore1: Generate busy signal earlier
multiply.vhdl multiply: Move selection of result bits into execute1
multiply_tb.vhdl multiply: Move selection of result bits into execute1
plru.vhdl plru: Improve sensitivity list
plru_tb.vhdl Exit cleanly from testbench on success
ppc_fx_insns.vhdl core: Implement a simple branch predictor
register_file.vhdl core: Don't generate logic for log data when LOG_LENGTH = 0
rotator.vhdl Implement the extswsli instruction
rotator_tb.vhdl Exit cleanly from testbench on success
sim_16550_uart.vhdl uart: Add a simulation model for the 16550 compatible UART
sim_bram.vhdl ram: Rework main RAM interface
sim_bram_helpers.vhdl ram: Rework main RAM interface
sim_bram_helpers_c.c Consolidate VHPI code
sim_console.vhdl Reformat sim_console
sim_console_c.c sim_console: Fix polling to check for POLLIN
sim_jtag.vhdl Add jtag support in simulation via a socket
sim_jtag_socket.vhdl Add jtag support in simulation via a socket
sim_jtag_socket_c.c Consolidate VHPI code
sim_no_flash.vhdl spi: Add simulation support
sim_pp_uart.vhdl uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl
sim_vhpi_c.c Consolidate VHPI code
sim_vhpi_c.h Consolidate VHPI code
soc.vhdl uart: Make 16550 the default
spi_flash_ctrl.vhdl spi: Send dummy clocks at boot
spi_rxtx.vhdl spi: Add SPI Flash controller
sync_fifo.vhdl litedram: Add an L2 cache with store queue
syscon.vhdl syscon: Add flag to indicate the timebase frequency
utils.vhdl litedram: Add support for booting without BRAM
wishbone_arbiter.vhdl wb_arbiter: Early master selection
wishbone_bram_tb.bin ram: Rework main RAM interface
wishbone_bram_tb.vhdl Exit cleanly from testbench on success
wishbone_bram_wrapper.vhdl Add log2ceil and use it in bram code
wishbone_debug_master.vhdl wishbone_debug_master: Fix address auto-increment for memory writes
wishbone_types.vhdl soc: Don't require dram wishbones signals to be wired by toplevel
writeback.vhdl core: Use a busy signal rather than a stall
xics.vhdl xics: Add support for reduced priority field size
xilinx-mult.vhdl multiply: Use DSP48 slices for multiplication on Xilinx FPGAs

README.md

Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

    If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.

  • Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)