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fpu-init
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loadstore-pmu-init
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log2ceil-issue
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microwatt/litedram
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Benjamin Herrenschmidt b23fd6c5f1 litedram: Defer clearing of tags & valids to improve timing 
Currently, there's a huge mux gathering the output of all the PLRUs
to select the victim way on cache miss. This is fed combinationally
into the clearing of the valid and tags.

In order to help timing, let's store it instead and perform the
clearing on the next cycle. The L2 doesn't respond to requests
when not in IDLE state so this should have no negative effects.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 		4 years ago
..
extras litedram: Defer clearing of tags & valids to improve timing 4 years ago
gen-src litedram: Fix DRAM init mem using too many address bits 5 years ago
generated litedram: Fix DRAM init mem using too many address bits 5 years ago
litedram.core litedram: Add basic support for LiteX LiteDRAM 5 years ago