microwatt

A tiny Open POWER ISA softcore written in VHDL 2008

You cannot select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

Go to file

Tom Vijlbrief ae55f5efbd Add Rust demo Signed-off-by: Tom Vijlbrief <tvijlbrief@gmail.com>		5 years ago
constraints	Initial support for ghdl synthesis	5 years ago
fpga	Add a few FFs on the RX input to avoid metastability issues	5 years ago
hello_world	hello_world: Use ldcix/stdcix to access UART	5 years ago
media	Add title image	5 years ago
micropython	Update micropython	5 years ago
openocd	Initial support for ghdl synthesis	5 years ago
rust_lib_demo	Add Rust demo	5 years ago
scripts	Add test cases for new exceptions and supervisor state	5 years ago
sim-unisim	Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs	5 years ago
tests	Merge pull request #158 from paulusmack/excpath	5 years ago
.gitignore	Add test cases for new exceptions and supervisor state	5 years ago
.travis.yml	Allow a full make check on Travis	5 years ago
LICENSE	Initial import of microwatt	5 years ago
Makefile	Add test cases for new exceptions and supervisor state	5 years ago
Makefile.synth	make the sources volume mount SELinux friendly	5 years ago
README.md	README: hello world needs 16KB of RAM	5 years ago
cache_ram.vhdl	dcache: Introduce an extra cycle latency to make timing	5 years ago
common.vhdl	Give exceptions a separate path to writeback	5 years ago
control.vhdl	execute: Implement bypass from output of execute1 to input	5 years ago
core.vhdl	loadstore1: Move logic from dcache to loadstore1	5 years ago
core_debug.vhdl	fetch/icache: Fit icache in BRAM	5 years ago
core_tb.vhdl	Reduce simulated and default FPGA RAM to 384kB	5 years ago
countzero.vhdl	countzero: Add a register to help make timing	5 years ago
countzero_tb.vhdl	countzero: Add a register to help make timing	5 years ago
cr_file.vhdl	Dump CTR, LR and CR on sim termination, and update our tests	5 years ago
cr_hazard.vhdl	sprs: Store common SPRs in register file	5 years ago
crhelpers.vhdl	crhelpers: Constraint "crnum" integer	5 years ago
dcache.vhdl	loadstore1: Move logic from dcache to loadstore1	5 years ago
dcache_tb.vhdl	loadstore1: Move logic from dcache to loadstore1	5 years ago
decode1.vhdl	Decode attn in the major opcode decode table	5 years ago
decode2.vhdl	dcache: Implement load-reserve and store-conditional instructions	5 years ago
decode_types.vhdl	Remove sim_config instruction	5 years ago
divider.vhdl	execute1: Remember dest GPR, RC, OE, XER for slow operations	5 years ago
divider_tb.vhdl	execute1: Remember dest GPR, RC, OE, XER for slow operations	5 years ago
dmi_dtm_dummy.vhdl	Fix build issue in dmi_dtm_dummy.vhdl	5 years ago
dmi_dtm_tb.vhdl	ram: Rework main RAM interface	5 years ago
dmi_dtm_xilinx.vhdl	Don't reset JTAG request register asynchronously	5 years ago
execute1.vhdl	Decode attn in the major opcode decode table	5 years ago
fetch1.vhdl	fetch/icache: Fit icache in BRAM	5 years ago
fetch2.vhdl	fetch2: Remove blank line	5 years ago
glibc_random.vhdl	Reformat glibc_random	5 years ago
glibc_random_helpers.vhdl	Reformat glibc_random	5 years ago
gpr_hazard.vhdl	execute: Implement bypass from output of execute1 to input	5 years ago
helpers.vhdl	execute: Copy XER[SO] to CR for cmp[i] and cmpl[i] instructions	5 years ago
icache.vhdl	Fix a ghdlsynth issue in icache	5 years ago
icache_tb.vhdl	ram: Rework main RAM interface	5 years ago
icache_test.bin	icache_tb: Improve test and include test file	5 years ago
insn_helpers.vhdl	Implement CRNOR and friends	5 years ago
loadstore1.vhdl	loadstore1: Add support for cache-inhibited load and store instructions	5 years ago
logical.vhdl	execute: Move popcnt and prty instructions into the logical unit	5 years ago
microwatt.core	Set default RAM to be 16K in microwatt.core	5 years ago
multiply.vhdl	execute1: Remember dest GPR, RC, OE, XER for slow operations	5 years ago
multiply_tb.vhdl	execute1: Remember dest GPR, RC, OE, XER for slow operations	5 years ago
plru.vhdl	plru: Improve sensitivity list	5 years ago
plru_tb.vhdl	plru: Add a simple PLRU module	5 years ago
ppc_fx_insns.vhdl	sprs: Store common SPRs in register file	5 years ago
register_file.vhdl	Fix ghdlsynth issue in register file	5 years ago
rotator.vhdl	Add a rotate/mask/shift unit and use it in execute1	5 years ago
rotator_tb.vhdl	Add a rotate/mask/shift unit and use it in execute1	5 years ago
sim_bram.vhdl	ram: Rework main RAM interface	5 years ago
sim_bram_helpers.vhdl	ram: Rework main RAM interface	5 years ago
sim_bram_helpers_c.c	Consolidate VHPI code	5 years ago
sim_console.vhdl	Reformat sim_console	5 years ago
sim_console_c.c	Consolidate VHPI code	5 years ago
sim_jtag.vhdl	Add jtag support in simulation via a socket	5 years ago
sim_jtag_socket.vhdl	Add jtag support in simulation via a socket	5 years ago
sim_jtag_socket_c.c	Consolidate VHPI code	5 years ago
sim_uart.vhdl	Share soc.vhdl between FPGA and sim	5 years ago
sim_vhpi_c.c	Consolidate VHPI code	5 years ago
sim_vhpi_c.h	Consolidate VHPI code	5 years ago
soc.vhdl	Removed unused core_terminated signal	5 years ago
utils.vhdl	Add log2ceil and use it in bram code	5 years ago
wishbone_arbiter.vhdl	wb_arbiter: Early master selection	5 years ago
wishbone_bram_tb.bin	ram: Rework main RAM interface	5 years ago
wishbone_bram_tb.vhdl	ram: Rework main RAM interface	5 years ago
wishbone_bram_wrapper.vhdl	Add log2ceil and use it in bram code	5 years ago
wishbone_debug_master.vhdl	wb_debug: Add wishbone pipelining support	5 years ago
wishbone_types.vhdl	wb_arbiter: Make arbiter size parametric	5 years ago
writeback.vhdl	execute1: Simplify the interrupt logic a little	5 years ago

README.md

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com

git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or podman images. Read through the Makefile for details.
Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

Link in the micropython image:

ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin

Now run microwatt, sending debug output to /dev/null:

./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

Install Vivado (I'm using the free 2019.1 webpack edition).
Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh

Install FuseSoC:

pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc

Create a working directory and point FuseSoC at microwatt:

mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/

Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):

fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):

fusesoc run --target=nexys_video microwatt

Testing

A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:

make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

There are a few instructions still to be implemented
Need to add caches and bypassing (in progress)
Need to add supervisor state (in progress)