You cannot select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

Benjamin Herrenschmidt 8e0389b973 ram: Rework main RAM interface ... This replaces the simple_ram_behavioural and mw_soc_memory modules with a common wishbone_bram_wrapper.vhdl that interfaces the pipelined WB with a lower-level RAM module, along with an FPGA and a sim variants of the latter. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		5 years ago
..
LICENSE	Initial import of microwatt	5 years ago
arty_a7.xdc	fpga: Arty A7's don't need multiple filesets	5 years ago
clk_gen_bypass.vhd	Fix clk_gen_bypass	5 years ago
clk_gen_mcmm.vhd	Improve PLL/MMCM clocks configuration	5 years ago
clk_gen_plle2.vhd	Improve PLL/MMCM clocks configuration	5 years ago
cmod_a7-35.xdc	Cmod A7-35 support	5 years ago
firmware.hex	Add a few more FPGA related files	5 years ago
hello_world.hex	Rebuild hello world assuming a 50MHz clock	5 years ago
main_bram.vhdl	ram: Rework main RAM interface	5 years ago
nexys-video.xdc	Rename a few reset signals	5 years ago
nexys_a7.xdc	Merge pull request #20 from antonblanchard/reset-rework2	5 years ago
pp_fifo.vhd	fifo: Reformat	5 years ago
pp_soc_uart.vhd	pp_uart: reformat	5 years ago
pp_utilities.vhd	Initial import of microwatt	5 years ago
soc_reset.vhdl	Rework SOC reset	5 years ago
soc_reset_tb.vhdl	Rework SOC reset	5 years ago
toplevel.vhdl	Add option to not flatten hierarchy	5 years ago