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366 lines
14 KiB
VHDL
366 lines
14 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.decode_types.all;
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entity pmu is
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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p_in : in Execute1ToPMUType;
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p_out : out PMUToExecute1Type
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);
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end entity pmu;
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architecture behaviour of pmu is
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-- MMCR0 bit numbers
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constant MMCR0_FC : integer := 63 - 32;
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constant MMCR0_FCS : integer := 63 - 33;
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constant MMCR0_FCP : integer := 63 - 34;
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constant MMCR0_FCM1 : integer := 63 - 35;
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constant MMCR0_FCM0 : integer := 63 - 36;
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constant MMCR0_PMAE : integer := 63 - 37;
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constant MMCR0_FCECE : integer := 63 - 38;
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constant MMCR0_TBSEL : integer := 63 - 40;
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constant MMCR0_TBEE : integer := 63 - 41;
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constant MMCR0_BHRBA : integer := 63 - 42;
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constant MMCR0_EBE : integer := 63 - 43;
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constant MMCR0_PMCC : integer := 63 - 45;
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constant MMCR0_PMC1CE : integer := 63 - 48;
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constant MMCR0_PMCjCE : integer := 63 - 49;
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constant MMCR0_TRIGGER : integer := 63 - 50;
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constant MMCR0_FCPC : integer := 63 - 51;
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constant MMCR0_PMAQ : integer := 63 - 52;
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constant MMCR0_PMCCEXT : integer := 63 - 54;
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constant MMCR0_CC56RUN : integer := 63 - 55;
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constant MMCR0_PMAO : integer := 63 - 56;
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constant MMCR0_FC1_4 : integer := 63 - 58;
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constant MMCR0_FC5_6 : integer := 63 - 59;
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constant MMCR0_FC1_4W : integer := 63 - 62;
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-- MMCR2 bit numbers
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constant MMCR2_FC0S : integer := 63 - 0;
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constant MMCR2_FC0P0 : integer := 63 - 1;
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constant MMCR2_FC0M1 : integer := 63 - 3;
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constant MMCR2_FC0M0 : integer := 63 - 4;
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constant MMCR2_FC0WAIT : integer := 63 - 5;
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constant MMCR2_FC1S : integer := 54 - 0;
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constant MMCR2_FC1P0 : integer := 54 - 1;
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constant MMCR2_FC1M1 : integer := 54 - 3;
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constant MMCR2_FC1M0 : integer := 54 - 4;
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constant MMCR2_FC1WAIT : integer := 54 - 5;
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constant MMCR2_FC2S : integer := 45 - 0;
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constant MMCR2_FC2P0 : integer := 45 - 1;
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constant MMCR2_FC2M1 : integer := 45 - 3;
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constant MMCR2_FC2M0 : integer := 45 - 4;
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constant MMCR2_FC2WAIT : integer := 45 - 5;
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constant MMCR2_FC3S : integer := 36 - 0;
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constant MMCR2_FC3P0 : integer := 36 - 1;
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constant MMCR2_FC3M1 : integer := 36 - 3;
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constant MMCR2_FC3M0 : integer := 36 - 4;
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constant MMCR2_FC3WAIT : integer := 36 - 5;
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constant MMCR2_FC4S : integer := 27 - 0;
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constant MMCR2_FC4P0 : integer := 27 - 1;
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constant MMCR2_FC4M1 : integer := 27 - 3;
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constant MMCR2_FC4M0 : integer := 27 - 4;
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constant MMCR2_FC4WAIT : integer := 27 - 5;
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constant MMCR2_FC5S : integer := 18 - 0;
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constant MMCR2_FC5P0 : integer := 18 - 1;
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constant MMCR2_FC5M1 : integer := 18 - 3;
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constant MMCR2_FC5M0 : integer := 18 - 4;
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constant MMCR2_FC5WAIT : integer := 18 - 5;
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constant MMCR2_FC6S : integer := 9 - 0;
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constant MMCR2_FC6P0 : integer := 9 - 1;
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constant MMCR2_FC6M1 : integer := 9 - 3;
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constant MMCR2_FC6M0 : integer := 9 - 4;
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constant MMCR2_FC6WAIT : integer := 9 - 5;
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-- MMCRA bit numbers
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constant MMCRA_TECX : integer := 63 - 36;
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constant MMCRA_TECM : integer := 63 - 44;
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constant MMCRA_TECE : integer := 63 - 47;
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constant MMCRA_TS : integer := 63 - 51;
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constant MMCRA_TE : integer := 63 - 55;
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constant MMCRA_ES : integer := 63 - 59;
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constant MMCRA_SM : integer := 63 - 62;
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constant MMCRA_SE : integer := 63 - 63;
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-- SIER bit numbers
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constant SIER_SAMPPR : integer := 63 - 38;
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constant SIER_SIARV : integer := 63 - 41;
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constant SIER_SDARV : integer := 63 - 42;
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constant SIER_TE : integer := 63 - 43;
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constant SIER_SITYPE : integer := 63 - 48;
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constant SIER_SICACHE : integer := 63 - 51;
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constant SIER_SITAKBR : integer := 63 - 52;
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constant SIER_SIMISPR : integer := 63 - 53;
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constant SIER_SIMISPRI : integer := 63 - 55;
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constant SIER_SIDERAT : integer := 63 - 56;
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constant SIER_SIDAXL : integer := 63 - 59;
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constant SIER_SIDSAI : integer := 63 - 62;
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constant SIER_SICMPL : integer := 63 - 63;
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type pmc_array is array(1 to 6) of std_ulogic_vector(31 downto 0);
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signal pmcs : pmc_array;
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signal mmcr0 : std_ulogic_vector(31 downto 0);
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signal mmcr1 : std_ulogic_vector(63 downto 0);
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signal mmcr2 : std_ulogic_vector(63 downto 0);
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signal mmcra : std_ulogic_vector(63 downto 0);
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signal siar : std_ulogic_vector(63 downto 0);
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signal sdar : std_ulogic_vector(63 downto 0);
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signal sier : std_ulogic_vector(63 downto 0);
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signal doinc : std_ulogic_vector(1 to 6);
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signal doalert : std_ulogic;
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signal doevent : std_ulogic;
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signal prev_tb : std_ulogic_vector(3 downto 0);
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begin
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-- mfspr mux
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with p_in.spr_num(3 downto 0) select p_out.spr_val <=
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32x"0" & pmcs(1) when "0011",
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32x"0" & pmcs(2) when "0100",
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32x"0" & pmcs(3) when "0101",
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32x"0" & pmcs(4) when "0110",
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32x"0" & pmcs(5) when "0111",
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32x"0" & pmcs(6) when "1000",
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32x"0" & mmcr0 when "1011",
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mmcr1 when "1110",
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mmcr2 when "0001",
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mmcra when "0010",
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siar when "1100",
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sdar when "1101",
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sier when "0000",
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64x"0" when others;
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p_out.intr <= mmcr0(MMCR0_PMAO);
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pmu_1: process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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mmcr0 <= 32x"80000000";
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else
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for i in 1 to 6 loop
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if p_in.mtspr = '1' and to_integer(unsigned(p_in.spr_num(3 downto 0))) = i + 2 then
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pmcs(i) <= p_in.spr_val(31 downto 0);
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elsif doinc(i) = '1' then
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pmcs(i) <= std_ulogic_vector(unsigned(pmcs(i)) + 1);
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end if;
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end loop;
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if p_in.mtspr = '1' and p_in.spr_num(3 downto 0) = "1011" then
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mmcr0 <= p_in.spr_val(31 downto 0);
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mmcr0(MMCR0_BHRBA) <= '0'; -- no BHRB yet
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mmcr0(MMCR0_EBE) <= '0'; -- no EBBs yet
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else
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if doalert = '1' then
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mmcr0(MMCR0_PMAE) <= '0';
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mmcr0(MMCR0_PMAO) <= '1';
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mmcr0(MMCR0_PMAQ) <= '0';
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end if;
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if doevent = '1' and mmcr0(MMCR0_FCECE) = '1' and mmcr0(MMCR0_TRIGGER) = '0' then
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mmcr0(MMCR0_FC) <= '1';
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end if;
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if (doevent = '1' or pmcs(1)(31) = '1') and mmcr0(MMCR0_TRIGGER) = '1' then
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mmcr0(MMCR0_TRIGGER) <= '0';
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end if;
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end if;
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if p_in.mtspr = '1' and p_in.spr_num(3 downto 0) = "1110" then
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mmcr1 <= p_in.spr_val;
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end if;
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if p_in.mtspr = '1' and p_in.spr_num(3 downto 0) = "0001" then
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mmcr2 <= p_in.spr_val;
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end if;
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if p_in.mtspr = '1' and p_in.spr_num(3 downto 0) = "0010" then
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mmcra <= p_in.spr_val;
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-- we don't support random sampling yet
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mmcra(MMCRA_SE) <= '0';
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end if;
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if p_in.mtspr = '1' and p_in.spr_num(3 downto 0) = "1100" then
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siar <= p_in.spr_val;
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elsif doalert = '1' then
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siar <= p_in.nia;
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end if;
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if p_in.mtspr = '1' and p_in.spr_num(3 downto 0) = "1101" then
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sdar <= p_in.spr_val;
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elsif doalert = '1' then
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sdar <= p_in.addr;
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end if;
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if p_in.mtspr = '1' and p_in.spr_num(3 downto 0) = "0000" then
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sier <= p_in.spr_val;
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elsif doalert = '1' then
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sier <= (others => '0');
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sier(SIER_SAMPPR) <= p_in.pr_msr;
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sier(SIER_SIARV) <= '1';
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sier(SIER_SDARV) <= p_in.addr_v;
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end if;
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end if;
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prev_tb <= p_in.tbbits;
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end if;
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end process;
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pmu_2: process(all)
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variable tbdiff : std_ulogic_vector(3 downto 0);
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variable tbbit : std_ulogic;
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variable freeze : std_ulogic;
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variable event : std_ulogic;
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variable j : integer;
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variable inc : std_ulogic_vector(1 to 6);
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variable fc14wo : std_ulogic;
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begin
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event := '0';
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-- Check for timebase events
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tbdiff := p_in.tbbits and not prev_tb;
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tbbit := tbdiff(3 - to_integer(unsigned(mmcr0(MMCR0_TBSEL + 1 downto MMCR0_TBSEL))));
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if tbbit = '1' and mmcr0(MMCR0_TBEE) = '1' then
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event := '1';
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end if;
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-- Check for counter negative events
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if mmcr0(MMCR0_PMC1CE) = '1' and pmcs(1)(31) = '1' then
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event := '1';
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end if;
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if mmcr0(MMCR0_PMCjCE) = '1' and
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(pmcs(2)(31) or pmcs(3)(31) or pmcs(4)(31)) = '1' then
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event := '1';
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end if;
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if mmcr0(MMCR0_PMCjCE) = '1' and
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mmcr0(MMCR0_PMCC + 1 downto MMCR0_PMCC) /= "11" and
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(pmcs(5)(31) or pmcs(6)(31)) = '1' then
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event := '1';
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end if;
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-- Event selection
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inc := (others => '0');
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fc14wo := '0';
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case mmcr1(31 downto 24) is
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when x"f0" =>
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inc(1) := '1';
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fc14wo := '1'; -- override MMCR0[FC1_4WAIT]
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when x"f2" | x"fe" =>
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inc(1) := p_in.occur.instr_complete;
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when x"f4" =>
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inc(1) := p_in.occur.fp_complete;
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when x"f6" =>
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inc(1) := p_in.occur.itlb_miss;
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when x"f8" =>
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inc(1) := p_in.occur.no_instr_avail;
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when x"fa" =>
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inc(1) := p_in.run;
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when x"fc" =>
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inc(1) := p_in.occur.ld_complete;
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when others =>
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end case;
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case mmcr1(23 downto 16) is
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when x"f0" =>
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inc(2) := p_in.occur.st_complete;
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when x"f2" =>
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inc(2) := p_in.occur.dispatch;
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when x"f4" =>
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inc(2) := p_in.run;
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when x"f6" =>
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inc(2) := p_in.occur.dtlb_miss_resolved;
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when x"f8" =>
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inc(2) := p_in.occur.ext_interrupt;
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when x"fa" =>
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inc(2) := p_in.occur.br_taken_complete;
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when x"fc" =>
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inc(2) := p_in.occur.icache_miss;
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when x"fe" =>
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inc(2) := p_in.occur.dc_miss_resolved;
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when others =>
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end case;
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case mmcr1(15 downto 8) is
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when x"f0" =>
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inc(3) := p_in.occur.dc_store_miss;
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when x"f2" =>
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inc(3) := p_in.occur.dispatch;
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when x"f4" =>
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inc(3) := p_in.occur.instr_complete and p_in.run;
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when x"f6" =>
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inc(3) := p_in.occur.dc_ld_miss_resolved;
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when x"f8" =>
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inc(3) := tbbit;
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when x"fe" =>
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inc(3) := p_in.occur.dtlb_miss;
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when others =>
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end case;
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case mmcr1(7 downto 0) is
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when x"f0" =>
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inc(4) := p_in.occur.dc_load_miss;
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when x"f2" =>
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inc(4) := p_in.occur.dispatch;
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when x"f4" =>
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inc(4) := p_in.run;
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when x"f6" =>
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inc(4) := p_in.occur.br_mispredict;
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when x"f8" =>
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inc(4) := p_in.occur.ipref_discard;
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when x"fa" =>
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inc(4) := p_in.occur.instr_complete and p_in.run;
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when x"fc" =>
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inc(4) := p_in.occur.itlb_miss_resolved;
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when x"fe" =>
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inc(4) := p_in.occur.ld_miss_nocache;
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when others =>
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end case;
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inc(5) := (mmcr0(MMCR0_CC56RUN) or p_in.run) and p_in.occur.instr_complete;
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inc(6) := mmcr0(MMCR0_CC56RUN) or p_in.run;
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-- Evaluate freeze conditions
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freeze := mmcr0(MMCR0_FC) or
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(mmcr0(MMCR0_FCS) and not p_in.pr_msr) or
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(mmcr0(MMCR0_FCP) and not mmcr0(MMCR0_FCPC) and p_in.pr_msr) or
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(not mmcr0(MMCR0_FCP) and mmcr0(MMCR0_FCPC) and p_in.pr_msr) or
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(mmcr0(MMCR0_FCM1) and p_in.pmm_msr) or
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(mmcr0(MMCR0_FCM0) and not p_in.pmm_msr);
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if freeze = '1' or mmcr0(MMCR0_FC1_4) = '1' or
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(mmcr0(MMCR0_FC1_4W) = '1' and p_in.run = '0' and fc14wo = '0') then
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inc(1) := '0';
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end if;
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if freeze = '1' or mmcr0(MMCR0_FC1_4) = '1' or
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(mmcr0(MMCR0_FC1_4W) = '1' and p_in.run = '0') then
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inc(2 to 4) := "000";
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end if;
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if freeze = '1' or mmcr0(MMCR0_FC5_6) = '1' then
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inc(5 to 6) := "00";
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end if;
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if mmcr0(MMCR0_TRIGGER) = '1' then
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inc(2 to 6) := "00000";
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end if;
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for i in 1 to 6 loop
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j := (i - 1) * 9;
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if (mmcr2(MMCR2_FC0S - j) = '1' and p_in.pr_msr = '0') or
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(mmcr2(MMCR2_FC0P0 - j) = '1' and p_in.pr_msr = '1') or
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(mmcr2(MMCR2_FC0M1 - j) = '1' and p_in.pmm_msr = '1') or
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(mmcr2(MMCR2_FC0M1 - j) = '1' and p_in.pmm_msr = '1') then
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inc(i) := '0';
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end if;
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end loop;
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-- When MMCR0[PMCC] = "11", PMC5 and PMC6 are not controlled by the
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-- MMCRs and don't generate events, but do continue to count run
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-- instructions and run cycles.
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if mmcr0(MMCR0_PMCC + 1 downto MMCR0_PMCC) = "11" then
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inc(5) := p_in.run and p_in.occur.instr_complete;
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inc(6) := p_in.run;
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end if;
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doinc <= inc;
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doevent <= event;
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doalert <= event and mmcr0(MMCR0_PMAE);
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end process;
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end architecture behaviour;
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