microwatt/litedram/extras
Benjamin Herrenschmidt a93d9e77c9 litedram: Remove remnants of riscv-inits
We still had some wires bringing an extra serial port out of
litedram for the built-in riscv processor. This is all gone now
so take them out.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
..
fusesoc-add-files.py litedram: Remove old "VexRiscV" based initializations
litedram-wrapper-l2.vhdl litedram: Remove remnants of riscv-inits
sim_dram_verilate.mk litedram: Add simulation support
sim_litedram.vhdl litedram: Add simulation support
sim_litedram_c.cpp litedram: Add simulation support
wave.gtkw litedram: Add an L2 cache with store queue
wave.opt litedram: Add an L2 cache with store queue
wave_tb.gtkw litedram: Test bench