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microwatt/fpga
Benjamin Herrenschmidt a69a93b466 Split FPGA toplevel from soc
This will be useful when we start needing different toplevels for
different boards.

We keep the reset and clock generators in the toplevel as they will
eventually be taken over by litedram when we integrate it, and they
are more likely to change on different system types.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
6 years ago
..
LICENSE
arty_a7-35.xdc
clk_gen_bypass.vhd
clk_gen_mcmm.vhd
clk_gen_plle2.vhd
cmod_a7-35.xdc
firmware.hex
hello_world.hex
nexys-video.xdc
nexys_a7.xdc
nodivide.patch
pp_fifo.vhd
pp_soc_memory.vhd
pp_soc_uart.vhd
pp_utilities.vhd
soc.vhdl Split FPGA toplevel from soc 6 years ago
soc_reset.vhdl
soc_reset_tb.vhdl
toplevel.vhdl Split FPGA toplevel from soc 6 years ago