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microwatt
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fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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microwatt/fpga
History
Anton Blanchard a53ad60014 Rename a few reset signals 
clk -> ext_clk
reset_n -> ext_rst
reset -> rst

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 		5 years ago
..
LICENSE Initial import of microwatt 5 years ago
arty_a7-35.xdc Rename a few reset signals 5 years ago
clk_gen_bypass.vhd Add dummy clock generator 5 years ago
clk_gen_plle2.vhd Add and use plle2 primitive for nexys boards 5 years ago
firmware.hex Add a few more FPGA related files 5 years ago
hello_world.hex Rebuild hello world assuming a 50MHz clock 5 years ago
nexys-video.xdc Rename a few reset signals 5 years ago
nexys_a7.xdc Rename a few reset signals 5 years ago
nodivide.patch Add a few more FPGA related files 5 years ago
pp_fifo.vhd Initial import of microwatt 5 years ago
pp_soc_memory.vhd Fix ghdl build error with pp_soc_memory 5 years ago
pp_soc_reset.vhd Initial import of microwatt 5 years ago
pp_soc_uart.vhd Initial import of microwatt 5 years ago
pp_utilities.vhd Initial import of microwatt 5 years ago
toplevel.vhd Rename a few reset signals 5 years ago