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300 lines
8.4 KiB
VHDL
300 lines
8.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.decode_types.all;
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use work.common.all;
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use work.helpers.all;
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use work.insn_helpers.all;
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entity decode2 is
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port (
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clk : in std_ulogic;
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d_in : in Decode1ToDecode2Type;
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e_out : out Decode2ToExecute1Type;
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m_out : out Decode2ToMultiplyType;
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l_out : out Decode2ToLoadstore1Type;
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r_in : in RegisterFileToDecode2Type;
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r_out : out Decode2ToRegisterFileType;
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c_in : in CrFileToDecode2Type;
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c_out : out Decode2ToCrFileType
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);
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end entity decode2;
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architecture behaviour of decode2 is
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signal d : Decode1ToDecode2Type;
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type decode_input_reg_t is record
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reg_valid : std_ulogic;
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reg : std_ulogic_vector(4 downto 0);
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data : std_ulogic_vector(63 downto 0);
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end record;
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function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
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reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
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begin
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case t is
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when RA =>
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return ('1', insn_ra(insn_in), reg_data);
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when RA_OR_ZERO =>
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return ('1', insn_ra(insn_in), ra_or_zero(reg_data, insn_ra(insn_in)));
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when RS =>
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return ('1', insn_rs(insn_in), reg_data);
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when NONE =>
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return ('0', (others => '0'), (others => '0'));
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end case;
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end;
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function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
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reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
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begin
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case t is
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when RB =>
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return ('1', insn_rb(insn_in), reg_data);
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when RS =>
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return ('1', insn_rs(insn_in), reg_data);
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when CONST_UI =>
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return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
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when CONST_SI =>
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return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
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when CONST_SI_HI =>
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return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
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when CONST_UI_HI =>
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return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
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when CONST_LI =>
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return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
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when CONST_BD =>
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return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
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when CONST_DS =>
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return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
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when NONE =>
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return ('0', (others => '0'), (others => '0'));
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end case;
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end;
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function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
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reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
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begin
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case t is
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when RS =>
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return ('1', insn_rs(insn_in), reg_data);
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when NONE =>
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return ('0', (others => '0'), (others => '0'));
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end case;
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end;
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function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
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begin
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case t is
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when RT =>
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return insn_rt(insn_in);
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when RA =>
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return insn_ra(insn_in);
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when NONE =>
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return "00000";
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end case;
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end;
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function decode_const_a (t : constant_a_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
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begin
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case t is
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when SH =>
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return "00" & insn_sh(insn_in);
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when SH32 =>
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return "000" & insn_sh32(insn_in);
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when FXM =>
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return insn_fxm(insn_in);
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when BO =>
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return "000" & insn_bo(insn_in);
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when BF =>
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return "00000" & insn_bf(insn_in);
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when TOO =>
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return "000" & insn_to(insn_in);
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when BC =>
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return "000" & insn_bc(insn_in);
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when NONE =>
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return "00000000";
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end case;
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end;
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function decode_const_b (t : constant_b_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
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begin
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case t is
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when MB =>
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return insn_mb(insn_in);
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when ME =>
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return insn_me(insn_in);
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when MB32 =>
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return "0" & insn_mb32(insn_in);
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when BI =>
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return "0" & insn_bi(insn_in);
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when L =>
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return "00000" & insn_l(insn_in);
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when NONE =>
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return "000000";
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end case;
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end;
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function decode_const_c (t : constant_c_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
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begin
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case t is
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when ME32 =>
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return insn_me32(insn_in);
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when BH =>
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return "000" & insn_bh(insn_in);
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when NONE =>
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return "00000";
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end case;
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end;
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function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
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begin
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case t is
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when RC =>
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return insn_rc(insn_in);
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when ONE =>
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return '1';
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when NONE =>
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return '0';
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end case;
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end;
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begin
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decode2_0: process(clk)
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begin
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if rising_edge(clk) then
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d <= d_in;
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end if;
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end process;
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r_out.read1_reg <= insn_ra(d.insn) when (d.decode.input_reg_a = RA) else
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insn_ra(d.insn) when d.decode.input_reg_a = RA_OR_ZERO else
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insn_rs(d.insn) when d.decode.input_reg_a = RS else
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(others => '0');
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r_out.read2_reg <= insn_rb(d.insn) when d.decode.input_reg_b = RB else
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insn_rs(d.insn) when d.decode.input_reg_b = RS else
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(others => '0');
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r_out.read3_reg <= insn_rs(d.insn) when d.decode.input_reg_c = RS else
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(others => '0');
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decode2_1: process(all)
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variable mul_a : std_ulogic_vector(63 downto 0);
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variable mul_b : std_ulogic_vector(63 downto 0);
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variable decoded_reg_a : decode_input_reg_t;
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variable decoded_reg_b : decode_input_reg_t;
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variable decoded_reg_c : decode_input_reg_t;
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begin
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e_out <= Decode2ToExecute1Init;
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l_out <= Decode2ToLoadStore1Init;
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m_out <= Decode2ToMultiplyInit;
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mul_a := (others => '0');
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mul_b := (others => '0');
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--e_out.input_cr <= d.decode.input_cr;
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--m_out.input_cr <= d.decode.input_cr;
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--e_out.output_cr <= d.decode.output_cr;
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decoded_reg_a := decode_input_reg_a (d.decode.input_reg_a, d.insn, r_in.read1_data);
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decoded_reg_b := decode_input_reg_b (d.decode.input_reg_b, d.insn, r_in.read2_data);
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decoded_reg_c := decode_input_reg_c (d.decode.input_reg_c, d.insn, r_in.read3_data);
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case d.decode.unit is
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when ALU =>
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e_out.valid <= d.valid;
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when LDST =>
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l_out.valid <= d.valid;
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when MUL =>
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m_out.valid <= d.valid;
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when NONE =>
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e_out.valid <= d.valid;
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e_out.insn_type <= OP_ILLEGAL;
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end case;
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-- execute unit
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e_out.nia <= d.nia;
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e_out.insn_type <= d.decode.insn_type;
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e_out.read_reg1 <= decoded_reg_a.reg;
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e_out.read_data1 <= decoded_reg_a.data;
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e_out.read_reg2 <= decoded_reg_b.reg;
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e_out.read_data2 <= decoded_reg_b.data;
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e_out.write_reg <= decode_output_reg(d.decode.output_reg_a, d.insn);
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e_out.rc <= decode_rc(d.decode.rc, d.insn);
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e_out.cr <= c_in.read_cr_data;
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e_out.input_carry <= d.decode.input_carry;
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e_out.output_carry <= d.decode.output_carry;
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if d.decode.lr then
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e_out.lr <= insn_lk(d.insn);
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end if;
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e_out.const1 <= decode_const_a(d.decode.const_a, d.insn);
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e_out.const2 <= decode_const_b(d.decode.const_b, d.insn);
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e_out.const3 <= decode_const_c(d.decode.const_c, d.insn);
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-- multiply unit
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m_out.nia <= d.nia;
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m_out.insn_type <= d.decode.insn_type;
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mul_a := decoded_reg_a.data;
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mul_b := decoded_reg_b.data;
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m_out.write_reg <= decode_output_reg(d.decode.output_reg_a, d.insn);
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m_out.rc <= decode_rc(d.decode.rc, d.insn);
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if d.decode.mul_32bit = '1' then
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if d.decode.mul_signed = '1' then
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m_out.data1 <= (others => mul_a(31));
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m_out.data1(31 downto 0) <= mul_a(31 downto 0);
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m_out.data2 <= (others => mul_b(31));
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m_out.data2(31 downto 0) <= mul_b(31 downto 0);
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else
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m_out.data1 <= '0' & x"00000000" & mul_a(31 downto 0);
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m_out.data2 <= '0' & x"00000000" & mul_b(31 downto 0);
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end if;
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else
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if d.decode.mul_signed = '1' then
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m_out.data1 <= mul_a(63) & mul_a;
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m_out.data2 <= mul_b(63) & mul_b;
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else
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m_out.data1 <= '0' & mul_a;
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m_out.data2 <= '0' & mul_b;
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end if;
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end if;
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-- load/store unit
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l_out.nia <= d.nia;
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l_out.update_reg <= decoded_reg_a.reg;
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l_out.addr1 <= decoded_reg_a.data;
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l_out.addr2 <= decoded_reg_b.data;
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l_out.data <= decoded_reg_c.data;
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l_out.write_reg <= decode_output_reg(d.decode.output_reg_a, d.insn);
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if d.decode.insn_type = OP_LOAD then
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l_out.load <= '1';
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else
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l_out.load <= '0';
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end if;
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case d.decode.length is
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when is1B =>
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l_out.length <= "0001";
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when is2B =>
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l_out.length <= "0010";
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when is4B =>
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l_out.length <= "0100";
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when is8B =>
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l_out.length <= "1000";
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when NONE =>
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l_out.length <= "0000";
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end case;
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l_out.byte_reverse <= d.decode.byte_reverse;
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l_out.sign_extend <= d.decode.sign_extend;
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l_out.update <= d.decode.update;
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end process;
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end architecture behaviour;
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