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Paul Mackerras 45cd8f4fc3 core: Add support for floating-point loads and stores ... This extends the register file so it can hold FPR values, and implements the FP loads and stores that do not require conversion between single and double precision. We now have the FP, FE0 and FE1 bits in MSR. FP loads and stores cause a FP unavailable interrupt if MSR[FP] = 0. The FPU facilities are optional and their presence is controlled by the HAS_FPU generic passed down from the top-level board file. It defaults to true for all except the A7-35 boards. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>		4 years ago
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fmt_log	core: Add support for floating-point loads and stores	4 years ago
mw_debug	Add core logging	5 years ago
bin2hex.py	bin2hex: Make sure to generate little endian files	5 years ago
dependencies.py	uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl	4 years ago
gen_icache_tb.py	icache_tb: Improve test and include test file	5 years ago
run_test.sh	Dump CTR, LR and CR on sim termination, and update our tests	5 years ago
run_test_console.sh	Add test cases for new exceptions and supervisor state	5 years ago
test_micropython.py	Update micropython	5 years ago
test_micropython_long.py	Update micropython	5 years ago
vhdltags	Add VHDL TAGS	5 years ago