matthew1kalasky3
/
microwatt
forked from cores/microwatt
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
You cannot select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
master
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '9bbef035a6'
${ noResults }
microwatt/litedram/gen-src
History
Michael Neuling 9bbef035a6
Merge pull request #212 from ozbenh/liteeth 
liteeth: Hook up LiteX LiteEth ethernet controller
 		4 years ago
..
sdram_init Merge pull request #212 from ozbenh/liteeth 4 years ago
arty.yml litedram: Remove old "VexRiscV" based initializations 4 years ago
dram-init-mem.vhdl litedram: Fix DRAM init mem using too many address bits 4 years ago
generate.py litedram: Remove old "VexRiscV" based initializations 4 years ago
nexys-video.yml litedram: Remove old "VexRiscV" based initializations 4 years ago
no-init-mem.vhdl
…
sim.yml litedram: Remove old "VexRiscV" based initializations 4 years ago