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Benjamin Herrenschmidt 8e0389b973 ram: Rework main RAM interface 
This replaces the simple_ram_behavioural and mw_soc_memory modules
with a common wishbone_bram_wrapper.vhdl that interfaces the
pipelined WB with a lower-level RAM module, along with an FPGA
and a sim variants of the latter.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
..
mw_debug New C based JTAG debug tool
dependencies.py Initial import of microwatt
gen_icache_tb.py icache_tb: Improve test and include test file
hash.py Initial import of microwatt
run_test.sh ram: Rework main RAM interface
test_micropython.py ram: Rework main RAM interface
test_micropython_long.py ram: Rework main RAM interface
verific.sh Fix verific script with new VHDL files