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102 lines
2.7 KiB
VHDL
102 lines
2.7 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.decode_types.all;
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use work.ppc_fx_insns.all;
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use work.crhelpers.all;
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entity multiply is
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generic (
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PIPELINE_DEPTH : natural := 2
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);
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port (
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clk : in std_logic;
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m_in : in Decode2ToMultiplyType;
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m_out : out MultiplyToWritebackType
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);
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end entity multiply;
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architecture behaviour of multiply is
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signal m: Decode2ToMultiplyType;
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type multiply_pipeline_stage is record
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valid : std_ulogic;
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insn_type : insn_type_t;
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data : signed(129 downto 0);
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write_reg : std_ulogic_vector(4 downto 0);
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rc : std_ulogic;
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end record;
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constant MultiplyPipelineStageInit : multiply_pipeline_stage := (valid => '0', insn_type => OP_ILLEGAL, rc => '0', data => (others => '0'), others => (others => '0'));
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type multiply_pipeline_type is array(0 to PIPELINE_DEPTH-1) of multiply_pipeline_stage;
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constant MultiplyPipelineInit : multiply_pipeline_type := (others => MultiplyPipelineStageInit);
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type reg_type is record
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multiply_pipeline : multiply_pipeline_type;
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end record;
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signal r, rin : reg_type := (multiply_pipeline => MultiplyPipelineInit);
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begin
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multiply_0: process(clk)
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begin
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if rising_edge(clk) then
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m <= m_in;
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r <= rin;
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end if;
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end process;
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multiply_1: process(all)
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variable v : reg_type;
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variable d : std_ulogic_vector(129 downto 0);
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variable d2 : std_ulogic_vector(63 downto 0);
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begin
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v := r;
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m_out <= MultiplyToWritebackInit;
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v.multiply_pipeline(0).valid := m.valid;
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v.multiply_pipeline(0).insn_type := m.insn_type;
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v.multiply_pipeline(0).data := signed(m.data1) * signed(m.data2);
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v.multiply_pipeline(0).write_reg := m.write_reg;
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v.multiply_pipeline(0).rc := m.rc;
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loop_0: for i in 1 to PIPELINE_DEPTH-1 loop
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v.multiply_pipeline(i) := r.multiply_pipeline(i-1);
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end loop;
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d := std_ulogic_vector(v.multiply_pipeline(PIPELINE_DEPTH-1).data);
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case_0: case v.multiply_pipeline(PIPELINE_DEPTH-1).insn_type is
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when OP_MUL_L64 =>
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d2 := d(63 downto 0);
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when OP_MUL_H32 =>
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d2 := d(63 downto 32) & d(63 downto 32);
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when OP_MUL_H64 =>
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d2 := d(127 downto 64);
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when others =>
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--report "Illegal insn type in multiplier";
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d2 := (others => '0');
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end case;
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m_out.write_reg_data <= d2;
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m_out.write_reg_nr <= v.multiply_pipeline(PIPELINE_DEPTH-1).write_reg;
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if v.multiply_pipeline(PIPELINE_DEPTH-1).valid = '1' then
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m_out.valid <= '1';
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m_out.write_reg_enable <= '1';
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if v.multiply_pipeline(PIPELINE_DEPTH-1).rc = '1' then
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m_out.write_cr_enable <= '1';
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m_out.write_cr_mask <= num_to_fxm(0);
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m_out.write_cr_data <= ppc_cmpi('1', d2, x"0000") & x"0000000";
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end if;
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end if;
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rin <= v;
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end process;
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end architecture behaviour;
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