Paul Mackerras 1a7aebeef8 Add random number generator and implement the darn instruction ... This adds a true random number generator for the Xilinx FPGAs which uses a set of chaotic ring oscillators to generate random bits and then passes them through a Linear Hybrid Cellular Automaton (LHCA) to remove bias, as described in "High Speed True Random Number Generators in Xilinx FPGAs" by Catalin Baetoniu of Xilinx Inc., in: https://pdfs.semanticscholar.org/83ac/9e9c1bb3dad5180654984604c8d5d8137412.pdf This requires adding a .xdc file to tell vivado that the combinatorial loops that form the ring oscillators are intentional. The same code should work on other FPGAs as well if their tools can be told to accept the combinatorial loops. For simulation, the random.vhdl module gets compiled in, which uses the pseudorand() function to generate random numbers. Synthesis using yosys uses nonrandom.vhdl, which always signals an error, causing darn to return 0xffff_ffff_ffff_ffff. This adds an implementation of the darn instruction. Darn can return either raw or conditioned random numbers. On Xilinx FPGAs, reading a raw random number gives the output of the ring oscillators, and reading a conditioned random number gives the output of the LHCA. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>		5 years ago
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LICENSE	Initial import of microwatt	6 years ago
arty_a7.xdc	uart: Import and hook up opencore 16550 compatible UART	5 years ago
clk_gen_bypass.vhd	Fix clk_gen_bypass	6 years ago
clk_gen_ecp5.vhd	Add PLL for ECP5 device	5 years ago
clk_gen_mcmm.vhd	Improve PLL/MMCM clocks configuration	6 years ago
clk_gen_plle2.vhd	Improve PLL/MMCM clocks configuration	6 years ago
cmod_a7-35.xdc	Add SPI configuration to Xilinx constraint files	5 years ago
firmware.hex	Add a few more FPGA related files	6 years ago
fpga-random.vhdl	Add random number generator and implement the darn instruction	5 years ago
fpga-random.xdc	Add random number generator and implement the darn instruction	5 years ago
hello_world.hex	hello_world: Use new headers and frequency from syscon	5 years ago
main_bram.vhdl	Fix some ghdlsynth issues with fpga_bram	5 years ago
nexys-video.xdc	spi: Add SPI Flash controller	5 years ago
nexys_a7.xdc	Add SPI configuration to Xilinx constraint files	5 years ago
pp_fifo.vhd	pp_fifo: Fix full fifo losing all data on simultaneous push & pop	5 years ago
pp_soc_uart.vhd	uart: Remove combinational loops on ack and stall signal	5 years ago
pp_utilities.vhd	Initial import of microwatt	6 years ago
soc_reset.vhdl	soc_reset: Use counters, add synchronizers	5 years ago
soc_reset_tb.vhdl	Exit cleanly from testbench on success	5 years ago
top-arty.vhdl	uart: Make 16550 the default	5 years ago
top-generic.vhdl	uart: Make 16550 the default	5 years ago
top-nexys-video.vhdl	corefile/nexys_video: Parameter fixes	5 years ago