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fpu-init
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icache-unused-sig
icache-insn-u-state
dcache-unused-sig
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divider-init
loadstore-pmu-init
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caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
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orange-crab-freq
dcache-nc-fix
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cache-tlb-parameters-2
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microwatt/scripts
History
Anton Blanchard efb387b0d2 makefile: Add some verilator micropython tests 
These are the same micropython tests we use against the ghdl
simulation.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 		3 years ago
..
fmt_log decode: Add a facility field to the instruction decode tables 4 years ago
mw_debug core_debug: Add an address trigger to stop logging at a given address 4 years ago
bin2hex.py bin2hex: Make sure to generate little endian files 5 years ago
dependencies.py uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl 4 years ago
gen_icache_tb.py icache_tb: Improve test and include test file 5 years ago
run_test.sh Dump CTR, LR and CR on sim termination, and update our tests 5 years ago
run_test_console.sh Add test cases for new exceptions and supervisor state 5 years ago
test_micropython.py Update micropython 5 years ago
test_micropython_long.py Update micropython 5 years ago
test_micropython_verilator.py makefile: Add some verilator micropython tests 3 years ago
test_micropython_verilator_long.py makefile: Add some verilator micropython tests 3 years ago
vhdltags Add VHDL TAGS 5 years ago