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109 lines
3.4 KiB
Python
109 lines
3.4 KiB
Python
#!/usr/bin/python3
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from litex.build.tools import write_to_file
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from litex.build.tools import replace_in_file
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from litedram.gen import *
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import subprocess
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import os
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import shutil
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def make_new_dir(base, added):
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r = os.path.join(base, added)
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if os.path.exists(r):
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shutil.rmtree(r)
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os.mkdir(r)
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return r
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gen_src_dir = os.path.dirname(os.path.realpath(__file__))
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base_dir = os.path.normpath(os.path.join(gen_src_dir, os.pardir))
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build_top_dir = make_new_dir(base_dir, "build")
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gen_src_dir = os.path.join(base_dir, "gen-src")
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gen_dir = make_new_dir(base_dir, "generated")
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# Build the init code for microwatt-initialized DRAM
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def build_init_code(build_dir, is_sim):
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# More path fudging
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sw_dir = os.path.join(build_dir, "software");
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sw_inc_dir = os.path.join(sw_dir, "include")
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gen_inc_dir = os.path.join(sw_inc_dir, "generated")
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src_dir = os.path.join(gen_src_dir, "sdram_init")
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lxbios_src_dir = os.path.join(soc_directory, "software")
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print(" sw dir:", sw_dir)
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print("gen_inc_dir:", gen_inc_dir)
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print(" src dir:", src_dir)
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print(" lx src dir:", lxbios_src_dir)
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# Generate mem.h (hard wire size, it's not important)
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mem_h = "#define MAIN_RAM_BASE 0x40000000UL\n#define MAIN_RAM_SIZE 0x10000000UL\n"
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write_to_file(os.path.join(gen_inc_dir, "mem.h"), mem_h)
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# Environment
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env_vars = []
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def _makefile_escape(s): # From LiteX
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return s.replace("\\", "\\\\")
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def add_var(k, v):
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env_vars.append("{}={}\n".format(k, _makefile_escape(v)))
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makefile = os.path.join(src_dir, "Makefile")
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cmd = ["make", "-C", build_dir, "-f", makefile]
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cmd.append("BUILD_DIR=%s" % sw_dir)
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cmd.append("SRC_DIR=%s" % src_dir)
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cmd.append("GENINC_DIR=%s" % sw_inc_dir)
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cmd.append("LXSRC_DIR=%s" % lxbios_src_dir)
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if is_sim:
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cmd.append("EXTRA_CFLAGS=%s" % "-D__SIM__")
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# Build init code
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print(" Generating init software...")
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r = subprocess.check_call(cmd)
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print("Make result:", r)
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return os.path.join(sw_dir, "obj", "sdram_init.hex")
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def generate_one(t):
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print("Generating target:", t)
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# Is it a simulation ?
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is_sim = "sim" in t
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# Muck with directory path
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build_dir = make_new_dir(build_top_dir, t)
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t_dir = make_new_dir(gen_dir, t)
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cmd = ["litedram_gen", "--output-dir=%s" % build_dir]
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if is_sim:
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cmd.append("--sim")
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cmd.append("%s.yml" % t)
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subprocess.check_call(cmd)
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# Grab generated gatewar dir
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gw_dir = os.path.join(build_dir, "gateware")
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# Generate init code
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src_init_file = build_init_code(build_dir, is_sim)
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src_initram_file = os.path.join(gen_src_dir, "dram-init-mem.vhdl")
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# Copy generated files to target dir, amend them if necessary
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initfile_name = "litedram_core.init"
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core_file = os.path.join(gw_dir, "litedram_core.v")
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dst_init_file = os.path.join(t_dir, initfile_name)
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dst_initram_file = os.path.join(t_dir, "litedram-initmem.vhdl")
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shutil.copyfile(src_init_file, dst_init_file)
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shutil.copyfile(src_initram_file, dst_initram_file)
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if is_sim:
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initfile_path = os.path.join("litedram", "generated", "sim", initfile_name)
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replace_in_file(dst_initram_file, initfile_name, initfile_path)
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shutil.copy(core_file, t_dir)
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def main():
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targets = ['arty','nexys-video', 'genesys2', 'acorn-cle-215', 'sim']
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for t in targets:
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generate_one(t)
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if __name__ == "__main__":
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main()
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