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60d2b8ac1e
You must have openocd 0.10.0 installed. $ ./openocd/flash-arty ~/microwatt-fusesoc/build/microwatt_0/arty_a7-35-vivado/microwatt_0.bit Open On-Chip Debugger 0.10.0 Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html none separate Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'. adapter speed: 25000 kHz fpga_program Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling" Info : clock speed 25000 kHz Info : JTAG tap: xc7.tap tap/device found: 0x0362d093 (mfg: 0x049 (Xilinx), part: 0x362d, ver: 0x0) loaded file microwatt/openocd/bscan_spi_xc7a35t.bit to pld device 0 in 0s 136459us Info : JTAG tap: xc7.tap tap/device found: 0x0362d093 (mfg: 0x049 (Xilinx), part: 0x362d, ver: 0x0) Info : Found flash device 'micron n25q128' (ID 0x0018ba20) flash 'jtagspi' found at 0x00000000 auto erase enabled Info : Found flash device 'micron n25q128' (ID 0x0018ba20) Info : Found flash device 'micron n25q128' (ID 0x0018ba20) Info : Found flash device 'micron n25q128' (ID 0x0018ba20) Info : sector 0 took 241 ms Info : sector 1 took 242 ms Info : sector 2 took 241 ms Info : sector 3 took 247 ms Info : sector 4 took 253 ms Info : sector 5 took 244 ms Info : sector 6 took 246 ms Info : sector 7 took 237 ms Info : sector 8 took 258 ms Info : sector 9 took 260 ms Info : sector 10 took 262 ms Info : sector 11 took 253 ms Info : sector 12 took 256 ms Info : sector 13 took 255 ms wrote 917504 bytes from file microwatt-fusesoc/build/microwatt_0/arty_a7-35-vivado/microwatt_0.bit in 9.642746s (92.920 KiB/s) Info : Found flash device 'micron n25q128' (ID 0x0018ba20) read 907483 bytes from file microwatt-fusesoc/build/microwatt_0/arty_a7-35-vivado/microwatt_0.bit and flash bank 0 at offset 0x00000000 in 0.557387s (1589.944 KiB/s) contents match Signed-off-by: Joel Stanley <joel@jms.id.au> |
5 years ago | |
|---|---|---|
| constraints | 5 years ago | |
| fpga | 5 years ago | |
| hello_world | 5 years ago | |
| media | 5 years ago | |
| micropython | 5 years ago | |
| openocd | 5 years ago | |
| rust_lib_demo | 5 years ago | |
| scripts | 5 years ago | |
| sim-unisim | ||
| tests | 5 years ago | |
| .gitignore | 5 years ago | |
| .travis.yml | ||
| LICENSE | ||
| Makefile | 5 years ago | |
| Makefile.synth | 5 years ago | |
| README.md | 5 years ago | |
| cache_ram.vhdl | 5 years ago | |
| common.vhdl | 5 years ago | |
| control.vhdl | 5 years ago | |
| core.vhdl | 5 years ago | |
| core_debug.vhdl | 5 years ago | |
| core_tb.vhdl | 5 years ago | |
| countzero.vhdl | 5 years ago | |
| countzero_tb.vhdl | 5 years ago | |
| cr_file.vhdl | 5 years ago | |
| cr_hazard.vhdl | 5 years ago | |
| crhelpers.vhdl | 5 years ago | |
| dcache.vhdl | 5 years ago | |
| dcache_tb.vhdl | 5 years ago | |
| decode1.vhdl | 5 years ago | |
| decode2.vhdl | 5 years ago | |
| decode_types.vhdl | 5 years ago | |
| divider.vhdl | 5 years ago | |
| divider_tb.vhdl | 5 years ago | |
| dmi_dtm_dummy.vhdl | ||
| dmi_dtm_tb.vhdl | 5 years ago | |
| dmi_dtm_xilinx.vhdl | ||
| execute1.vhdl | 5 years ago | |
| fetch1.vhdl | 5 years ago | |
| fetch2.vhdl | 5 years ago | |
| glibc_random.vhdl | ||
| glibc_random_helpers.vhdl | ||
| gpr_hazard.vhdl | 5 years ago | |
| helpers.vhdl | 5 years ago | |
| icache.vhdl | 5 years ago | |
| icache_tb.vhdl | 5 years ago | |
| icache_test.bin | 5 years ago | |
| insn_helpers.vhdl | 5 years ago | |
| loadstore1.vhdl | 5 years ago | |
| logical.vhdl | 5 years ago | |
| microwatt.core | 5 years ago | |
| multiply.vhdl | 5 years ago | |
| multiply_tb.vhdl | 5 years ago | |
| plru.vhdl | 5 years ago | |
| plru_tb.vhdl | 5 years ago | |
| ppc_fx_insns.vhdl | 5 years ago | |
| register_file.vhdl | 5 years ago | |
| rotator.vhdl | 5 years ago | |
| rotator_tb.vhdl | 5 years ago | |
| sim_bram.vhdl | 5 years ago | |
| sim_bram_helpers.vhdl | 5 years ago | |
| sim_bram_helpers_c.c | 5 years ago | |
| sim_console.vhdl | ||
| sim_console_c.c | 5 years ago | |
| sim_jtag.vhdl | ||
| sim_jtag_socket.vhdl | ||
| sim_jtag_socket_c.c | 5 years ago | |
| sim_uart.vhdl | 5 years ago | |
| sim_vhpi_c.c | 5 years ago | |
| sim_vhpi_c.h | 5 years ago | |
| soc.vhdl | 5 years ago | |
| utils.vhdl | 5 years ago | |
| wishbone_arbiter.vhdl | 5 years ago | |
| wishbone_bram_tb.bin | 5 years ago | |
| wishbone_bram_tb.vhdl | 5 years ago | |
| wishbone_bram_wrapper.vhdl | 5 years ago | |
| wishbone_debug_master.vhdl | 5 years ago | |
| wishbone_types.vhdl | 5 years ago | |
| writeback.vhdl | 5 years ago | |
| xics.vhdl | 5 years ago | |
README.md
Microwatt
A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.
Simulation using ghdl
You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.
- Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../
A prebuilt micropython image is also available in the micropython/ directory.
-
Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.
If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or podman images. Read through the Makefile for details.
-
Next build microwatt:
git clone https://github.com/antonblanchard/microwatt
cd microwatt
make
- Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin
Or if you were using the pre-built image:
ln -s micropython/firmware.bin main_ram.bin
- Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null
Synthesis on Xilinx FPGAs using Vivado
-
Install Vivado (I'm using the free 2019.1 webpack edition).
-
Setup Vivado paths:
source /opt/Xilinx/Vivado/2019.1/settings64.sh
- Install FuseSoC:
pip3 install --user -U fusesoc
Fedora users can get FuseSoC package via
sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
- Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
- Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex
You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.
- To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt
Testing
- A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check
Issues
This is functional, but very simple. We still have quite a lot to do:
- There are a few instructions still to be implemented
- Need to add caches and bypassing (in progress)
- Need to add supervisor state (in progress)