microwatt/litedram/gen-src
Benjamin Herrenschmidt 599fad117b litedram: Remove old "VexRiscV" based initializations
Support for this has bitrotted and would require refactoring of L2 to
be brought back. It's also not really needed anymore now that we ship
pre-generated litedram and that LiteX supports what we do.

So take it out, which simplifies some of the scripts as well. This also
fixes up CSR alignment the sim model.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
..
sdram_init litedram: Add an L2 cache with store queue
arty.yml litedram: Remove old "VexRiscV" based initializations
dram-init-mem.vhdl litedram: Add support for booting without BRAM
generate.py litedram: Remove old "VexRiscV" based initializations
nexys-video.yml litedram: Remove old "VexRiscV" based initializations
no-init-mem.vhdl litedram: Split the init memory from the main wrapper
sim.yml litedram: Remove old "VexRiscV" based initializations