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riktw 4ebd6fc1f7 Added support for building for Arty A7 boards		5 years ago
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LICENSE	Initial import of microwatt	5 years ago
arty_a7-35.xdc	Added support for building for Arty A7 boards	5 years ago
clk_gen_bypass.vhd	Add dummy clock generator	5 years ago
clk_gen_plle2.vhd	Add and use plle2 primitive for nexys boards	5 years ago
firmware.hex	Add a few more FPGA related files	5 years ago
hello_world.hex	Rebuild hello world assuming a 50MHz clock	5 years ago
nexys-video.xdc	Initial import of microwatt	5 years ago
nexys_a7.xdc	Add constraint file for Nexys A7	5 years ago
nodivide.patch	Add a few more FPGA related files	5 years ago
pp_fifo.vhd	Initial import of microwatt	5 years ago
pp_soc_memory.vhd	Fix ghdl build error with pp_soc_memory	5 years ago
pp_soc_reset.vhd	Initial import of microwatt	5 years ago
pp_soc_uart.vhd	Initial import of microwatt	5 years ago
pp_utilities.vhd	Initial import of microwatt	5 years ago
toplevel.vhd	micropython only requires 512kB of BRAM	5 years ago