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A tiny Open POWER ISA softcore written in VHDL 2008
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65 MiB
Verilog 78.4%
VHDL 16.6%
C 3.7%
Assembly 0.6%
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Anton Blanchard 4528ef2b43 Reformat core.vhdl
fpga Share soc.vhdl between FPGA and sim
hello_world Rebuild hello world assuming a 50MHz clock
scripts Fix verific script with new VHDL files
tests Initial import of microwatt
.gitignore Add new files to git ignore
.travis.yml A few Travis CI fixes
LICENSE Initial import of microwatt
Makefile Update Makefile dependencies
README.md Add pretty gif demo of MicroPython on Microwatt to README.md
common.vhdl Rework pipeline, add stall and flush signals
core.vhdl Reformat core.vhdl
core_tb.vhdl Share soc.vhdl between FPGA and sim
cr_file.vhdl Fix CR forwarding
crhelpers.vhdl Initial import of microwatt
decode1.vhdl Remove sim console
decode2.vhdl Move debug execute output into decode2
decode_types.vhdl Remove sim console
execute1.vhdl Remove sim console
execute2.vhdl Register outputs on execute2
fetch1.vhdl Rework pipeline, add stall and flush signals
fetch2.vhdl Rework pipeline, add stall and flush signals
glibc_random.vhdl Initial import of microwatt
glibc_random_helpers.vhdl Initial import of microwatt
helpers.vhdl Remove dynamic ranges from code
insn_helpers.vhdl Rework decode2
loadstore1.vhdl Register outputs on loadstore1
loadstore2.vhdl Remove second write port
microwatt.core Share soc.vhdl between FPGA and sim
multiply.vhdl Reduce multiply to 2 cycles
multiply_tb.vhdl Initial import of microwatt
ppc_fx_insns.vhdl Remove dynamic ranges from code
register_file.vhdl Add forwarding in the register file
sim_console.vhdl Initial import of microwatt
sim_console_c.c Make sim poll non-blocking
sim_uart.vhdl Share soc.vhdl between FPGA and sim
simple_ram_behavioural.vhdl Share soc.vhdl between FPGA and sim
simple_ram_behavioural_helpers.vhdl Initial import of microwatt
simple_ram_behavioural_helpers_c.c Silence some loadstore related debug
simple_ram_behavioural_tb.bin Initial import of microwatt
simple_ram_behavioural_tb.vhdl Share soc.vhdl between FPGA and sim
soc.vhdl Switch soc to use std_ulogic
wishbone_arbiter.vhdl Initial import of microwatt
wishbone_types.vhdl Initial import of microwatt
writeback.vhdl Register outputs on writeback

README.md

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com
git clone https://github.com/mikey/micropython
cd micropython
git checkout powerpc
cd ports/powerpc
make -j$(nproc)
cd ../../../
  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:
git clone https://github.com/antonblanchard/microwatt
cd microwatt
make
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin simple_ram_behavioural.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board):
fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex
  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

  • Need to implement a simple non pipelined divide
  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)