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microwatt/fpga
Benjamin Herrenschmidt 3b603402d2 soc_reset: Use counters, add synchronizers
In some cases we need to keep the reset held for much longer,
so use counters rather than shift registers.

Additionally, some signals such as ext_rst and pll_locked
or signals going from the ext_clk domain to the pll_clk
domain need to be treated as async, and testing them without
synchronizers is asking for trouble.

Finally, make the external reset also reset the PLL.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
..
LICENSE
arty_a7.xdc fpga: Hookup Arty to litedram 5 years ago
clk_gen_bypass.vhd
clk_gen_mcmm.vhd
clk_gen_plle2.vhd
cmod_a7-35.xdc
firmware.hex
hello_world.hex hello_world: Use new headers and frequency from syscon 5 years ago
main_bram.vhdl Fix some ghdlsynth issues with fpga_bram 5 years ago
nexys-video.xdc fpga: Hookup nexys-video to litedram 5 years ago
nexys_a7.xdc
pp_fifo.vhd pp_fifo: Fix full fifo losing all data on simultaneous push & pop 5 years ago
pp_soc_uart.vhd pp_soc_uart: Fix rx synchronizers and ensure stable tx init state 5 years ago
pp_utilities.vhd
soc_reset.vhdl soc_reset: Use counters, add synchronizers 5 years ago
soc_reset_tb.vhdl soc_reset: Use counters, add synchronizers 5 years ago
top-arty.vhdl litedram: Update to new LiteX/LiteDRAM version 5 years ago
top-generic.vhdl fpga: Hookup Arty to litedram 5 years ago
top-nexys-video.vhdl litedram: Update to new LiteX/LiteDRAM version 5 years ago