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microwatt/fpga
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Michael Neuling d7458d5beb
Reduce the size of icache to help yosys ECP5 builds () 
The icache RAM is currently LUT ram not block ram. This massively
bloats the icache size. We think this is due to yosys not inferencing
the RAM correctly but that's yet to be confirmed.

Work around this for now by reducing the default size of the icache
RAM for the ECP5 builds.

On the ECP5 85K builts, this gets us from 95% down to 76% and helps
our CI to pass.

Signed-off-by: Michael Neuling <mikey@neuling.org>
..
LICENSE Initial import of microwatt
acorn-cle-215.xdc acorn: Add support for the Acorn CLE 215+
arty_a7.xdc Merge pull request from paulus/gpio
clk_gen_bypass.vhd Fix clk_gen_bypass
clk_gen_ecp5.vhd Add PLL for ECP5 device
clk_gen_mcmm.vhd Improve PLL/MMCM clocks configuration
clk_gen_plle2.vhd acorn: Add support for the Acorn CLE 215+
cmod_a7-35.xdc Add SPI configuration to Xilinx constraint files
firmware.hex Add a few more FPGA related files
fpga-random.vhdl Add random number generator and implement the darn instruction
fpga-random.xdc Add random number generator and implement the darn instruction
genesys2.xdc fpga: Add support for Genesys2
hello_world.hex hello_world: Use new headers and frequency from syscon
main_bram.vhdl Fix some ghdlsynth issues with fpga_bram
nexys-video.xdc spi: Add SPI Flash controller
nexys_a7.xdc Add SPI configuration to Xilinx constraint files
pp_fifo.vhd pp_fifo: Fix full fifo losing all data on simultaneous push & pop
pp_soc_uart.vhd uart: Remove combinational loops on ack and stall signal
pp_utilities.vhd Initial import of microwatt
soc_reset.vhdl soc_reset: Use counters, add synchronizers
soc_reset_tb.vhdl Exit cleanly from testbench on success
top-acorn-cle-215.vhdl acorn: Add support for the Acorn CLE 215+
top-arty.vhdl Merge pull request from paulus/gpio
top-generic.vhdl Reduce the size of icache to help yosys ECP5 builds ()
top-genesys2.vhdl fpga: Add support for Genesys2
top-nexys-video.vhdl fetch1: Implement a simple branch target cache