A tiny Open POWER ISA softcore written in VHDL 2008
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Michael Neuling 27b660ef76
Merge pull request #346 from mkj/dmi_ecp5
Add DMI and mw_debug for ECP5
3 years ago
.github/workflows ci: Add new Orange Crab build 3 years ago
constraints orangecrab: add Orange Crab r0.2 target 3 years ago
fpga orangecrab: Fix sdcard wishbone addressing 3 years ago
hello_world
include arty_a7: Add litesdcard interface 4 years ago
lib
litedram litedram: Add orangecrab-85-0.2 target 3 years ago
liteeth Regenerate litedram and liteeth 3 years ago
litesdcard litesdcard: add lattice, regenerate 3 years ago
media
micropython
openocd flash-arty: Add cable argument 3 years ago
rust_lib_demo
scripts mw_debug: Add Lattice ECP5 support 3 years ago
sim-unisim
tests tests/misc: Add a store/dcbz test 3 years ago
uart16550
verilator verilator: Specify top level module 3 years ago
.gitignore Add liteeth/build to gitignore 3 years ago
LICENSE
Makefile dmi_dtm_ecp5: Use ECP5 JTAGG for DMI 3 years ago
README.md
cache_ram.vhdl
common.vhdl Introduce real_addr_t and addr_to_real() 3 years ago
control.vhdl
core.vhdl core: Add a short multiplier 3 years ago
core_debug.vhdl Fix some whitespace issues 3 years ago
core_dram_tb.vhdl
core_flash_tb.vhdl
core_tb.vhdl
countbits.vhdl core: Make popcnt* take two cycles 3 years ago
countbits_tb.vhdl core: Make popcnt* take two cycles 3 years ago
cr_file.vhdl
crhelpers.vhdl
dcache.vhdl Introduce addr_to_wb() and wb_to_addr() helpers 3 years ago
dcache_tb.vhdl
decode1.vhdl decode1: Conditional trap instructions don't need to be single-issue 3 years ago
decode2.vhdl core: Make popcnt* take two cycles 3 years ago
decode_types.vhdl
divider.vhdl
divider_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging 3 years ago
dmi_dtm_dummy.vhdl
dmi_dtm_ecp5.vhdl dmi_dtm_ecp5: Use ECP5 JTAGG for DMI 3 years ago
dmi_dtm_tb.vhdl
dmi_dtm_xilinx.vhdl Fix some whitespace issues 3 years ago
dram_tb.vhdl Make wishbone addresses be in units of doublewords or words 3 years ago
execute1.vhdl core: Make popcnt* take two cycles 3 years ago
fetch1.vhdl core: Predict not-taken conditional branches using BTC 3 years ago
foreign_random.vhdl Make core testbenches recognized by VUnit 3 years ago
fpu.vhdl
glibc_random.vhdl
glibc_random_helpers.vhdl
gpio.vhdl Make wishbone addresses be in units of doublewords or words 3 years ago
helpers.vhdl
icache.vhdl icache: req_laddr becomes req_raddr 3 years ago
icache_tb.vhdl
icache_test.bin
insn_helpers.vhdl
loadstore1.vhdl loadstore1: Make r1.req.addr not depend on l_in.valid 3 years ago
logical.vhdl core: Make popcnt* take two cycles 3 years ago
microwatt.core core: Make popcnt* take two cycles 3 years ago
mmu.vhdl MMU: Implement a vestigial partition table 3 years ago
multiply.vhdl core: Add a short multiplier 3 years ago
multiply_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging 3 years ago
nonrandom.vhdl
plru.vhdl
plru_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging 3 years ago
pmu.vhdl PMU: Add several more events 3 years ago
ppc_fx_insns.vhdl Fix some whitespace issues 3 years ago
random.vhdl Make core testbenches recognized by VUnit 3 years ago
register_file.vhdl
rotator.vhdl
rotator_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging 3 years ago
run.py VUnit: style 3 years ago
sim_16550_uart.vhdl
sim_bram.vhdl Rename 'do' signal to avoid verilator System Verilog warning 3 years ago
sim_bram_helpers.vhdl
sim_bram_helpers_c.c
sim_console.vhdl
sim_console_c.c
sim_jtag.vhdl
sim_jtag_socket.vhdl
sim_jtag_socket_c.c
sim_no_flash.vhdl
sim_pp_uart.vhdl
sim_vhpi_c.c
sim_vhpi_c.h
soc.vhdl Merge pull request #329 from paulusmack/wb-fix 3 years ago
spi_flash_ctrl.vhdl Make wishbone addresses be in units of doublewords or words 3 years ago
spi_rxtx.vhdl
sync_fifo.vhdl
syscon.vhdl Make wishbone addresses be in units of doublewords or words 3 years ago
utils.vhdl
wishbone_arbiter.vhdl
wishbone_bram_tb.bin
wishbone_bram_tb.vhdl Make wishbone addresses be in units of doublewords or words 3 years ago
wishbone_bram_wrapper.vhdl Make wishbone addresses be in units of doublewords or words 3 years ago
wishbone_debug_master.vhdl Make wishbone addresses be in units of doublewords or words 3 years ago
wishbone_types.vhdl Introduce addr_to_wb() and wb_to_addr() helpers 3 years ago
writeback.vhdl PMU: Add several more events 3 years ago
xics.vhdl Make wishbone addresses be in units of doublewords or words 3 years ago
xilinx-mult.vhdl core: Add a short multiplier 3 years ago

README.md

Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

    If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.

  • Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
  • If this is your first time using fusesoc, initialize fusesoc. This is needed to be able to pull down fussoc library components referenced by microwatt. Run
fusesoc init
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100): You may wish to ensure you have installed Digilent Board files or appropriate files for your board first.
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)