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microwatt/litedram/extras
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Benjamin Herrenschmidt bedc9c0085 litedram: l2: Add a few comments about litedram behaviour 
litedram ignores a couple of signals of his "pseudo-axi" port,
this adds a bit of documentation around it.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 		4 years ago
..
fusesoc-add-files.py litedram: Remove old "VexRiscV" based initializations 5 years ago
litedram-wrapper-l2.vhdl litedram: l2: Add a few comments about litedram behaviour 4 years ago
sim_dram_verilate.mk
…
sim_litedram.vhdl
…
sim_litedram_c.cpp
…
wave.gtkw litedram: Add an L2 cache with store queue 5 years ago
wave.opt litedram: Add an L2 cache with store queue 5 years ago
wave_tb.gtkw litedram: l2: Latency improvements 4 years ago