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microwatt/fpga
Michael Neuling d7458d5beb
Reduce the size of icache to help yosys ECP5 builds (#303)
The icache RAM is currently LUT ram not block ram. This massively
bloats the icache size. We think this is due to yosys not inferencing
the RAM correctly but that's yet to be confirmed.

Work around this for now by reducing the default size of the icache
RAM for the ECP5 builds.

On the ECP5 85K builts, this gets us from 95% down to 76% and helps
our CI to pass.

Signed-off-by: Michael Neuling <mikey@neuling.org>
3 years ago
..
LICENSE
acorn-cle-215.xdc
arty_a7.xdc Merge pull request #277 from paulus/gpio 4 years ago
clk_gen_bypass.vhd
clk_gen_ecp5.vhd
clk_gen_mcmm.vhd
clk_gen_plle2.vhd
cmod_a7-35.xdc
firmware.hex
fpga-random.vhdl
fpga-random.xdc
genesys2.xdc fpga: Add support for Genesys2 4 years ago
hello_world.hex
main_bram.vhdl
nexys-video.xdc
nexys_a7.xdc
pp_fifo.vhd
pp_soc_uart.vhd
pp_utilities.vhd
soc_reset.vhdl
soc_reset_tb.vhdl
top-acorn-cle-215.vhdl
top-arty.vhdl Merge pull request #277 from paulus/gpio 4 years ago
top-generic.vhdl Reduce the size of icache to help yosys ECP5 builds (#303) 3 years ago
top-genesys2.vhdl fpga: Add support for Genesys2 4 years ago
top-nexys-video.vhdl fetch1: Implement a simple branch target cache 4 years ago