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microwatt/fpga
Anton Blanchard 142a722ce4 Remove names from end record statements
These are optional, and vhdlpp from iverilog barfs on them.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
6 years ago
..
LICENSE
arty_a7-35.xdc Merge pull request #20 from antonblanchard/reset-rework2 6 years ago
clk_gen_bypass.vhd Rework SOC reset 6 years ago
clk_gen_mcmm.vhd Remove names from end record statements 6 years ago
clk_gen_plle2.vhd Remove names from end record statements 6 years ago
cmod_a7-35.xdc Cmod A7-35 support 6 years ago
firmware.hex
hello_world.hex
mw_soc_memory.vhdl Pass wishbone record to bram memory module 6 years ago
nexys-video.xdc
nexys_a7.xdc Merge pull request #20 from antonblanchard/reset-rework2 6 years ago
nodivide.patch
pp_fifo.vhd
pp_soc_uart.vhd
pp_utilities.vhd
soc_reset.vhdl Rework SOC reset 6 years ago
soc_reset_tb.vhdl Rework SOC reset 6 years ago
toplevel.vhdl Share soc.vhdl between FPGA and sim 6 years ago