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13e84b0bbb
The rx synchronizers were ... non existent. Someone forgot to add a if rising_edge(clk) to the process. For tx, ensure that we have a default value so that TX stays high from TPGA configuration to the reset being sampled on the first clock cycle. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
4 years ago | |
|---|---|---|
| .. | ||
| LICENSE | ||
| arty_a7.xdc | ||
| clk_gen_bypass.vhd | ||
| clk_gen_mcmm.vhd | ||
| clk_gen_plle2.vhd | ||
| cmod_a7-35.xdc | ||
| firmware.hex | ||
| hello_world.hex | 4 years ago | |
| main_bram.vhdl | ||
| nexys-video.xdc | ||
| nexys_a7.xdc | ||
| pp_fifo.vhd | 4 years ago | |
| pp_soc_uart.vhd | 4 years ago | |
| pp_utilities.vhd | ||
| soc_reset.vhdl | ||
| soc_reset_tb.vhdl | ||
| top-arty.vhdl | 4 years ago | |
| top-generic.vhdl | ||
| top-nexys-video.vhdl | 4 years ago | |