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515 lines
12 KiB
C
515 lines
12 KiB
C
#include <stddef.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "console.h"
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#define MSR_LE 0x1
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#define MSR_DR 0x10
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#define MSR_IR 0x20
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#define MSR_SF 0x8000000000000000ul
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extern unsigned long callit(unsigned long arg1, unsigned long arg2,
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unsigned long fn, unsigned long msr);
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extern void do_lq(void *src, unsigned long *regs);
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extern void do_lq_np(void *src, unsigned long *regs);
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extern void do_lq_bad(void *src, unsigned long *regs);
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extern void do_stq(void *dst, unsigned long *regs);
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extern void do_lq_be(void *src, unsigned long *regs);
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extern void do_lq_np_be(void *src, unsigned long *regs);
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extern void do_stq_be(void *dst, unsigned long *regs);
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static inline void do_tlbie(unsigned long rb, unsigned long rs)
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{
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__asm__ volatile("tlbie %0,%1" : : "r" (rb), "r" (rs) : "memory");
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}
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#define DSISR 18
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#define DAR 19
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#define SRR0 26
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#define SRR1 27
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#define PID 48
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#define SPRG0 272
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#define SPRG1 273
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#define SPRG3 275
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#define PTCR 464
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static inline unsigned long mfspr(int sprnum)
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{
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long val;
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__asm__ volatile("mfspr %0,%1" : "=r" (val) : "i" (sprnum));
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return val;
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}
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static inline void mtspr(int sprnum, unsigned long val)
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{
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__asm__ volatile("mtspr %0,%1" : : "i" (sprnum), "r" (val));
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}
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static inline void store_pte(unsigned long *p, unsigned long pte)
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{
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__asm__ volatile("stdbrx %1,0,%0" : : "r" (p), "r" (pte) : "memory");
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}
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void print_string(const char *str)
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{
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for (; *str; ++str)
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putchar(*str);
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}
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void print_hex(unsigned long val, int ndigit)
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{
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int i, x;
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for (i = (ndigit - 1) * 4; i >= 0; i -= 4) {
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x = (val >> i) & 0xf;
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if (x >= 10)
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putchar(x + 'a' - 10);
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else
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putchar(x + '0');
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}
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}
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// i < 100
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void print_test_number(int i)
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{
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print_string("test ");
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putchar(48 + i/10);
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putchar(48 + i%10);
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putchar(':');
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}
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#define CACHE_LINE_SIZE 64
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void zero_memory(void *ptr, unsigned long nbytes)
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{
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unsigned long nb, i, nl;
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void *p;
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for (; nbytes != 0; nbytes -= nb, ptr += nb) {
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nb = -((unsigned long)ptr) & (CACHE_LINE_SIZE - 1);
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if (nb == 0 && nbytes >= CACHE_LINE_SIZE) {
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nl = nbytes / CACHE_LINE_SIZE;
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p = ptr;
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for (i = 0; i < nl; ++i) {
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__asm__ volatile("dcbz 0,%0" : : "r" (p) : "memory");
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p += CACHE_LINE_SIZE;
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}
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nb = nl * CACHE_LINE_SIZE;
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} else {
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if (nb > nbytes)
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nb = nbytes;
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for (i = 0; i < nb; ++i)
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((unsigned char *)ptr)[i] = 0;
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}
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}
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}
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#define PERM_EX 0x001
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#define PERM_WR 0x002
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#define PERM_RD 0x004
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#define PERM_PRIV 0x008
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#define ATTR_NC 0x020
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#define CHG 0x080
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#define REF 0x100
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#define DFLT_PERM (PERM_EX | PERM_WR | PERM_RD | REF | CHG)
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/*
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* Set up an MMU translation tree using memory starting at the 64k point.
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* We use 3 levels, mapping 512GB, with 4kB PGD/PMD/PTE pages.
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*/
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unsigned long *part_tbl = (unsigned long *) 0x10000;
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unsigned long *proc_tbl = (unsigned long *) 0x11000;
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unsigned long *pgdir = (unsigned long *) 0x12000;
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unsigned long free_ptr = 0x13000;
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void init_mmu(void)
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{
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/* set up partition table */
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store_pte(&part_tbl[1], (unsigned long)proc_tbl);
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/* set up process table */
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zero_memory(proc_tbl, 512 * sizeof(unsigned long));
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mtspr(PTCR, (unsigned long)part_tbl);
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mtspr(PID, 1);
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zero_memory(pgdir, 512 * sizeof(unsigned long));
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/* RTS = 8 (512GB address space), RPDS = 9 (512-entry top level) */
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store_pte(&proc_tbl[2 * 1], (unsigned long) pgdir | 0x2000000000000009);
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do_tlbie(0xc00, 0); /* invalidate all TLB entries */
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}
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static unsigned long *read_pd(unsigned long *pdp, unsigned long i)
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{
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unsigned long ret;
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__asm__ volatile("ldbrx %0,%1,%2" : "=r" (ret) : "b" (pdp),
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"r" (i * sizeof(unsigned long)));
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return (unsigned long *) (ret & 0x00ffffffffffff00);
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}
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void map(unsigned long ea, unsigned long pa, unsigned long perm_attr)
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{
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unsigned long epn = ea >> 12;
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unsigned long h, i, j;
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unsigned long *ptep;
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unsigned long *pmdp;
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h = (epn >> 18) & 0x1ff;
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i = (epn >> 9) & 0x1ff;
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j = epn & 0x1ff;
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if (pgdir[h] == 0) {
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zero_memory((void *)free_ptr, 512 * sizeof(unsigned long));
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store_pte(&pgdir[h], 0x8000000000000000 | free_ptr | 9);
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free_ptr += 512 * sizeof(unsigned long);
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}
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pmdp = read_pd(pgdir, h);
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if (pmdp[i] == 0) {
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zero_memory((void *)free_ptr, 512 * sizeof(unsigned long));
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store_pte(&pmdp[i], 0x8000000000000000 | free_ptr | 9);
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free_ptr += 512 * sizeof(unsigned long);
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}
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ptep = read_pd(pmdp, i);
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if (ptep[j]) {
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ptep[j] = 0;
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do_tlbie(ea & ~0xfff, 0);
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}
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store_pte(&ptep[j], 0xc000000000000000 | (pa & 0x00fffffffffff000) |
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perm_attr);
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}
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void unmap(void *ea)
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{
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unsigned long epn = (unsigned long) ea >> 12;
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unsigned long h, i, j;
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unsigned long *ptep, *pmdp;
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h = (epn >> 18) & 0x1ff;
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i = (epn >> 9) & 0x1ff;
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j = epn & 0x1ff;
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if (pgdir[h] == 0)
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return;
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pmdp = read_pd(pgdir, h);
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if (pmdp[i] == 0)
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return;
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ptep = read_pd(pmdp, i);
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ptep[j] = 0;
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do_tlbie(((unsigned long)ea & ~0xfff), 0);
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}
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extern unsigned long test_code(unsigned long sel, unsigned long addr);
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static unsigned long bits = 0x0102030405060708ul;
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int mode_test_1(void)
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{
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unsigned long ret, msr;
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msr = MSR_SF | MSR_IR | MSR_DR | MSR_LE;
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ret = callit(1, (unsigned long)&bits, (unsigned long)&test_code, msr);
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if (ret != bits)
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return ret? ret: 1;
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return 0;
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}
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unsigned long be_test_code;
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int mode_test_2(void)
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{
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unsigned long i;
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unsigned int *src, *dst;
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unsigned long ret, msr;
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/* copy and byte-swap the page containing test_code */
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be_test_code = free_ptr;
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free_ptr += 0x1000;
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src = (unsigned int *) &test_code;
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dst = (unsigned int *) be_test_code;
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for (i = 0; i < 0x1000 / sizeof(unsigned int); ++i)
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dst[i] = __builtin_bswap32(src[i]);
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__asm__ volatile("isync; icbi 0,%0" : : "r" (be_test_code));
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map(be_test_code, be_test_code, DFLT_PERM);
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msr = MSR_SF | MSR_IR | MSR_DR;
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ret = callit(1, (unsigned long)&bits, be_test_code, msr);
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if (ret != __builtin_bswap64(bits))
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return ret? ret: 1;
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return 0;
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}
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int mode_test_3(void)
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{
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unsigned long ret, msr;
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unsigned long addr = (unsigned long) &bits;
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unsigned long code = (unsigned long) &test_code;
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msr = MSR_IR | MSR_DR | MSR_LE;
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ret = callit(1, addr, code, msr);
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if (ret != bits)
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return ret? ret: 1;
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ret = callit(1, addr + 0x5555555500000000ul,
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code + 0x9999999900000000ul, msr);
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if (ret != bits)
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return ret? ret: 2;
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return 0;
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}
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int mode_test_4(void)
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{
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unsigned long ret, msr;
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unsigned long addr = (unsigned long) &bits;
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msr = MSR_IR | MSR_DR;
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ret = callit(1, addr, be_test_code, msr);
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if (ret != __builtin_bswap64(bits))
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return ret? ret: 1;
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ret = callit(1, addr + 0x5555555500000000ul,
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be_test_code + 0x9999999900000000ul, msr);
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if (ret != __builtin_bswap64(bits))
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return ret? ret: 2;
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return 0;
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}
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int mode_test_5(void)
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{
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unsigned long ret, msr;
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/*
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* Try branching from the page at fffff000
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* to the page at 0 in 32-bit mode.
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*/
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map(0xfffff000, (unsigned long) &test_code, DFLT_PERM);
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map(0, (unsigned long) &test_code, DFLT_PERM);
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msr = MSR_IR | MSR_DR | MSR_LE;
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ret = callit(2, 0, 0xfffff000, msr);
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return ret;
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}
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int mode_test_6(void)
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{
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unsigned long ret, msr;
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/*
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* Try a bl from address fffffffc in 32-bit mode.
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* We expect LR to be set to 100000000, though the
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* arch says the value is undefined.
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*/
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msr = MSR_IR | MSR_DR | MSR_LE;
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ret = callit(3, 0, 0xfffff000, msr);
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if (ret != 0x100000000ul)
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return 1;
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return 0;
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}
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int mode_test_7(void)
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{
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unsigned long quad[4] __attribute__((__aligned__(16)));
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unsigned long regs[2];
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unsigned long ret, msr;
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/*
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* Test lq/stq in LE mode
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*/
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msr = MSR_SF | MSR_LE;
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quad[0] = 0x123456789abcdef0ul;
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quad[1] = 0xfafa5959bcbc3434ul;
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ret = callit((unsigned long)quad, (unsigned long)regs,
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(unsigned long)&do_lq, msr);
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if (ret)
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return ret | 1;
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if (regs[0] != quad[1] || regs[1] != quad[0])
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return 2;
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/* unaligned may give alignment interrupt */
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quad[2] = 0x0011223344556677ul;
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ret = callit((unsigned long)&quad[1], (unsigned long)regs,
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(unsigned long)&do_lq, msr);
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if (ret == 0) {
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if (regs[0] != quad[2] || regs[1] != quad[1])
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return 3;
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} else if (ret == 0x600) {
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if (mfspr(SPRG0) != (unsigned long) &do_lq ||
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mfspr(DAR) != (unsigned long) &quad[1])
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return ret | 4;
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} else
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return ret | 5;
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/* try stq */
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regs[0] = 0x5238523852385238ul;
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regs[1] = 0x5239523952395239ul;
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ret = callit((unsigned long)quad, (unsigned long)regs,
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(unsigned long)&do_stq, msr);
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if (ret)
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return ret | 5;
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if (quad[0] != regs[1] || quad[1] != regs[0])
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return 6;
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regs[0] = 0x0172686966746564ul;
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regs[1] = 0xfe8d0badd00dabcdul;
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ret = callit((unsigned long)quad + 1, (unsigned long)regs,
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(unsigned long)&do_stq, msr);
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if (ret)
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return ret | 7;
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if (((quad[0] >> 8) | (quad[1] << 56)) != regs[1] ||
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((quad[1] >> 8) | (quad[2] << 56)) != regs[0])
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return 8;
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/* try lq non-preferred form */
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quad[0] = 0x56789abcdef01234ul;
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quad[1] = 0x5959bcbc3434fafaul;
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ret = callit((unsigned long)quad, (unsigned long)regs,
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(unsigned long)&do_lq_np, msr);
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if (ret)
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return ret | 9;
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if (regs[0] != quad[1] || regs[1] != quad[0])
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return 10;
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/* unaligned should give alignment interrupt in uW implementation */
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quad[2] = 0x6677001122334455ul;
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ret = callit((unsigned long)&quad[1], (unsigned long)regs,
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(unsigned long)&do_lq_np, msr);
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if (ret == 0x600) {
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if (mfspr(SPRG0) != (unsigned long) &do_lq_np + 4 ||
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mfspr(DAR) != (unsigned long) &quad[1])
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return ret | 11;
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} else
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return 12;
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/* make sure lq with rt = ra causes an illegal instruction interrupt */
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ret = callit((unsigned long)quad, (unsigned long)regs,
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(unsigned long)&do_lq_bad, msr);
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if (ret != 0x700)
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return 13;
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if (mfspr(SPRG0) != (unsigned long)&do_lq_bad + 4 ||
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!(mfspr(SPRG3) & 0x80000))
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return 14;
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return 0;
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}
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int mode_test_8(void)
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{
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unsigned long quad[4] __attribute__((__aligned__(16)));
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unsigned long regs[2];
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unsigned long ret, msr;
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/*
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* Test lq/stq in BE mode
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*/
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msr = MSR_SF;
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quad[0] = 0x123456789abcdef0ul;
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quad[1] = 0xfafa5959bcbc3434ul;
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ret = callit((unsigned long)quad, (unsigned long)regs,
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(unsigned long)&do_lq_be, msr);
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if (ret)
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return ret | 1;
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if (regs[0] != quad[0] || regs[1] != quad[1]) {
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print_hex(regs[0], 16);
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print_string(" ");
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print_hex(regs[1], 16);
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print_string(" ");
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return 2;
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}
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/* don't expect alignment interrupt */
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quad[2] = 0x0011223344556677ul;
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ret = callit((unsigned long)&quad[1], (unsigned long)regs,
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(unsigned long)&do_lq_be, msr);
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if (ret == 0) {
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if (regs[0] != quad[1] || regs[1] != quad[2])
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return 3;
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} else
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return ret | 5;
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/* try stq */
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regs[0] = 0x5238523852385238ul;
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regs[1] = 0x5239523952395239ul;
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ret = callit((unsigned long)quad, (unsigned long)regs,
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(unsigned long)&do_stq_be, msr);
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if (ret)
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return ret | 5;
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if (quad[0] != regs[0] || quad[1] != regs[1])
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return 6;
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regs[0] = 0x0172686966746564ul;
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regs[1] = 0xfe8d0badd00dabcdul;
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ret = callit((unsigned long)quad + 1, (unsigned long)regs,
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(unsigned long)&do_stq_be, msr);
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if (ret)
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return ret | 7;
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if (((quad[0] >> 8) | (quad[1] << 56)) != regs[0] ||
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((quad[1] >> 8) | (quad[2] << 56)) != regs[1]) {
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print_hex(quad[0], 16);
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print_string(" ");
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print_hex(quad[1], 16);
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print_string(" ");
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print_hex(quad[2], 16);
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print_string(" ");
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return 8;
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}
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/* try lq non-preferred form */
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quad[0] = 0x56789abcdef01234ul;
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quad[1] = 0x5959bcbc3434fafaul;
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ret = callit((unsigned long)quad, (unsigned long)regs,
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(unsigned long)&do_lq_np_be, msr);
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if (ret)
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return ret | 9;
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if (regs[0] != quad[0] || regs[1] != quad[1])
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return 10;
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/* unaligned should not give alignment interrupt in uW implementation */
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quad[2] = 0x6677001122334455ul;
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ret = callit((unsigned long)&quad[1], (unsigned long)regs,
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(unsigned long)&do_lq_np_be, msr);
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if (ret)
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return ret | 11;
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if (regs[0] != quad[1] || regs[1] != quad[2])
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return 12;
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return 0;
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}
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int fail = 0;
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void do_test(int num, int (*test)(void))
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{
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int ret;
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print_test_number(num);
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ret = test();
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if (ret == 0) {
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print_string("PASS\r\n");
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} else {
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fail = 1;
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print_string("FAIL ");
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print_hex(ret, 16);
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if (ret != 0 && (ret & ~0xfe0ul) == 0) {
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print_string(" SRR0=");
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print_hex(mfspr(SPRG0), 16);
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print_string(" SRR1=");
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print_hex(mfspr(SPRG1), 16);
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}
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print_string("\r\n");
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}
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}
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int main(void)
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{
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unsigned long addr;
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extern unsigned char __stack_top[];
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console_init();
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init_mmu();
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/*
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* Map test code and stack 1-1
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*/
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for (addr = 0; addr < (unsigned long)&__stack_top; addr += 0x1000)
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map(addr, addr, DFLT_PERM);
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do_test(1, mode_test_1);
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do_test(2, mode_test_2);
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do_test(3, mode_test_3);
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do_test(4, mode_test_4);
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do_test(5, mode_test_5);
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do_test(6, mode_test_6);
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do_test(7, mode_test_7);
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do_test(8, mode_test_8);
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return fail;
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}
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