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72 lines
2.6 KiB
Python
72 lines
2.6 KiB
Python
#!/usr/bin/python
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import argparse
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import re
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module_regex = r'[a-zA-Z0-9_:\.\\]+'
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# match:
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# module dcache(clk, rst, d_in, m_in, wishbone_in, d_out, m_out, stall_out, wishbone_out);
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# A bit of a hack - ignore anything contining a '`', and assume that means we've already
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# processed this module in a previous run. This helps when having to run this script
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# multiple times for different power names.
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multiline_module_re = re.compile(r'module\s+(' + module_regex + r')\(([^`]*?)\);', re.DOTALL)
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module_re = re.compile(r'module\s+(' + module_regex + r')\((.*?)\);')
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# match:
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# dcache_64_2_2_2_2_12_0 dcache_0 (
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hookup_re = re.compile(r'\s+(' + module_regex + r') ' + module_regex + r'\s+\(')
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header1 = """\
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`ifdef USE_POWER_PINS
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{power}, {ground}, `endif\
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"""
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header2 = """\
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`ifdef USE_POWER_PINS
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inout {power};
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inout {ground};
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`endif\
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"""
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header3 = """\
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`ifdef USE_POWER_PINS
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.{power}({parent_power}),
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.{ground}({parent_ground}),
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`endif\
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"""
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parser = argparse.ArgumentParser(description='Insert power and ground into verilog modules')
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parser.add_argument('--power', default='VPWR', help='POWER net name (default VPWR)')
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parser.add_argument('--ground', default='VGND', help='POWER net name (default VGND)')
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parser.add_argument('--parent-power', default='VPWR', help='POWER net name of parent module (default VPWR)')
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parser.add_argument('--parent-ground', default='VGND', help='POWER net name of parent module (default VGND)')
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parser.add_argument('--verilog', required=True, help='Verilog file to modify')
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parser.add_argument('--module', required=True, action='append', help='Module to replace (can be specified multiple times')
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args = parser.parse_args()
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with open(args.verilog, 'r') as f:
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d = f.read()
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# Remove newlines from module definitions, yosys started doing this as of
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# commit ff8e999a7112 ("Split module ports, 20 per line")
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fixed = multiline_module_re.sub(lambda m: m.group(0).replace("\n", ""), d)
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for line in fixed.splitlines():
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m = module_re.match(line)
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m2 = hookup_re.match(line)
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if m and m.group(1) in args.module:
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module_name = m.group(1)
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module_args = m.group(2)
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print('module %s(' % (module_name))
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print("")
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print(header1.format(power=args.power, ground=args.ground))
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print(' %s);' % module_args)
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print(header2.format(power=args.power, ground=args.ground))
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elif m2 and m2.group(1) in args.module:
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print(line)
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print(header3.format(parent_power=args.parent_power, parent_ground=args.parent_ground, power=args.power, ground=args.ground))
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else:
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print(line)
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