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Benjamin Herrenschmidt 025cf5efe8 syscon: Add syscon registers ... These provides some info about the SoC (though it's still somewhat incomplete and needs more work, see comments). There's also a control register for selecting DRAM vs. BRAM at 0 (and for soft-resetting the SoC but that isn't wired up yet). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		5 years ago
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LICENSE	Initial import of microwatt	5 years ago
arty_a7.xdc	fpga: Hookup Arty to litedram	5 years ago
clk_gen_bypass.vhd	Fix clk_gen_bypass	5 years ago
clk_gen_mcmm.vhd	Improve PLL/MMCM clocks configuration	5 years ago
clk_gen_plle2.vhd	Improve PLL/MMCM clocks configuration	5 years ago
cmod_a7-35.xdc	Add SPI configuration to Xilinx constraint files	5 years ago
firmware.hex	Add a few more FPGA related files	5 years ago
hello_world.hex	Update hello_world for 100Mhz clock	5 years ago
main_bram.vhdl	Fix some ghdlsynth issues with fpga_bram	5 years ago
nexys-video.xdc	fpga: Hookup nexys-video to litedram	5 years ago
nexys_a7.xdc	Add SPI configuration to Xilinx constraint files	5 years ago
pp_fifo.vhd	fifo: Reformat	5 years ago
pp_soc_uart.vhd	Add a few FFs on the RX input to avoid metastability issues	5 years ago
pp_utilities.vhd	Initial import of microwatt	5 years ago
soc_reset.vhdl	Rework SOC reset	5 years ago
soc_reset_tb.vhdl	Rework SOC reset	5 years ago
top-arty.vhdl	syscon: Add syscon registers	5 years ago
top-generic.vhdl	fpga: Hookup Arty to litedram	5 years ago
top-nexys-video.vhdl	syscon: Add syscon registers	5 years ago