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276 lines
8.4 KiB
VHDL
276 lines
8.4 KiB
VHDL
-- Xilinx internal JTAG to DMI interface
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--
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-- DMI bus
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--
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-- req : ____/------------\_____
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-- addr: xxxx< >xxxxx
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-- dout: xxxx< >xxxxx
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-- wr : xxxx< >xxxxx
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-- din : xxxxxxxxxxxx< >xxx
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-- ack : ____________/------\___
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--
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-- * addr/dout set along with req, can be latched on same cycle by slave
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-- * ack & din remain up until req is dropped by master, the slave must
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-- provide a stable output on din on reads during that time.
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-- * req remains low at until at least one sysclk after ack seen down.
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--
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-- JTAG (tck) DMI (sys_clk)
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--
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-- * jtag_req = 1
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-- (jtag_req_0) *
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-- (jtag_req_1) -> * dmi_req = 1 >
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-- *.../...
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-- * dmi_ack = 1 <
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-- * (dmi_ack_0)
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-- * <- (dmi_ack_1)
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-- * jtag_req = 0 (and latch dmi_din)
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-- (jtag_req_0) *
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-- (jtag_req_1) -> * dmi_req = 0 >
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-- * dmi_ack = 0 <
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-- * (dmi_ack_0)
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-- * <- (dmi_ack_1)
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--
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-- jtag_req can go back to 1 when jtag_rsp_1 is 0
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--
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-- Questions/TODO:
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-- - I use 2 flip fops for sync, is that enough ?
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-- - I treat the jtag_reset as an async reset, is that necessary ?
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-- - Dbl check reset situation since we have two different resets
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-- each only resetting part of the logic...
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-- - Look at optionally removing the synchronizer on the ack path,
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-- assuming JTAG is always slow enough that ack will have been
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-- stable long enough by the time CAPTURE comes in.
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-- - We could avoid the latched request by not shifting while a
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-- request is in progress (and force TDO to 1 to return a busy
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-- status).
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--
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-- WARNING: This isn't the real DMI JTAG protocol (at least not yet).
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-- a command while busy will be ignored. A response of "11"
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-- means the previous command is still going, try again.
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-- As such We don't implement the DMI "error" status, and
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-- we don't implement DTMCS yet... This may still all change
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-- but for now it's easier that way as the real DMI protocol
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-- requires for a command to work properly that enough TCK
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-- are sent while IDLE and I'm having trouble getting that
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-- working with UrJtag and the Xilinx BSCAN2 for now.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.math_real.all;
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library work;
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use work.wishbone_types.all;
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library unisim;
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use unisim.vcomponents.all;
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entity dmi_dtm is
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generic(ABITS : INTEGER:=8;
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DBITS : INTEGER:=32);
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port(sys_clk : in std_ulogic;
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sys_reset : in std_ulogic;
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dmi_addr : out std_ulogic_vector(ABITS - 1 downto 0);
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dmi_din : in std_ulogic_vector(DBITS - 1 downto 0);
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dmi_dout : out std_ulogic_vector(DBITS - 1 downto 0);
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dmi_req : out std_ulogic;
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dmi_wr : out std_ulogic;
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dmi_ack : in std_ulogic
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-- dmi_err : in std_ulogic TODO: Add error response
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);
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end entity dmi_dtm;
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architecture behaviour of dmi_dtm is
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-- Signals coming out of the BSCANE2 block
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signal jtag_reset : std_ulogic;
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signal capture : std_ulogic;
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signal update : std_ulogic;
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signal drck : std_ulogic;
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signal jtag_clk : std_ulogic;
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signal sel : std_ulogic;
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signal shift : std_ulogic;
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signal tdi : std_ulogic;
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signal tdo : std_ulogic;
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signal tck : std_ulogic;
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-- ** JTAG clock domain **
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-- Shift register
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signal shiftr : std_ulogic_vector(ABITS + DBITS + 1 downto 0);
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-- Latched request
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signal request : std_ulogic_vector(ABITS + DBITS + 1 downto 0);
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-- A request is present
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signal jtag_req : std_ulogic;
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-- Synchronizer for jtag_rsp (sys clk -> jtag_clk)
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signal dmi_ack_0 : std_ulogic;
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signal dmi_ack_1 : std_ulogic;
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-- ** sys clock domain **
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-- Synchronizer for jtag_req (jtag clk -> sys clk)
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signal jtag_req_0 : std_ulogic;
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signal jtag_req_1 : std_ulogic;
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-- ** combination signals
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signal jtag_bsy : std_ulogic;
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signal op_valid : std_ulogic;
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signal rsp_op : std_ulogic_vector(1 downto 0);
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-- ** Constants **
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constant DMI_REQ_NOP : std_ulogic_vector(1 downto 0) := "00";
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constant DMI_REQ_RD : std_ulogic_vector(1 downto 0) := "01";
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constant DMI_REQ_WR : std_ulogic_vector(1 downto 0) := "10";
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constant DMI_RSP_OK : std_ulogic_vector(1 downto 0) := "00";
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constant DMI_RSP_BSY : std_ulogic_vector(1 downto 0) := "11";
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begin
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-- Implement the Xilinx bscan2 for series 7 devices (TODO: use PoC to
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-- wrap this if compatibility is required with older devices).
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bscan : BSCANE2
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generic map (
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JTAG_CHAIN => 2
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)
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port map (
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CAPTURE => capture,
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DRCK => drck,
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RESET => jtag_reset,
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RUNTEST => open,
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SEL => sel,
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SHIFT => shift,
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TCK => tck,
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TDI => tdi,
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TMS => open,
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UPDATE => update,
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TDO => tdo
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);
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-- Some examples out there suggest buffering the clock so it's
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-- treated as a proper clock net. This is probably needed when using
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-- drck (the gated clock) but I'm using the real tck here to avoid
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-- missing the update phase so maybe not...
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--
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clkbuf : BUFG
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port map (
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-- I => drck,
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I => tck,
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O => jtag_clk
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);
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-- dmi_req synchronization
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dmi_req_sync : process(sys_clk)
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begin
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-- sys_reset is synchronous
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if rising_edge(sys_clk) then
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if (sys_reset = '1') then
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jtag_req_0 <= '0';
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jtag_req_1 <= '0';
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else
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jtag_req_0 <= jtag_req;
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jtag_req_1 <= jtag_req_0;
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end if;
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end if;
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end process;
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dmi_req <= jtag_req_1;
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-- dmi_ack synchronization
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dmi_ack_sync: process(jtag_clk, jtag_reset)
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begin
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-- jtag_reset is async (see comments)
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if jtag_reset = '1' then
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dmi_ack_0 <= '0';
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dmi_ack_1 <= '0';
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elsif rising_edge(jtag_clk) then
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dmi_ack_0 <= dmi_ack;
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dmi_ack_1 <= dmi_ack_0;
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end if;
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end process;
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-- jtag_bsy indicates whether we can start a new request, we can when
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-- we aren't already processing one (jtag_req) and the synchronized ack
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-- of the previous one is 0.
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--
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jtag_bsy <= jtag_req or dmi_ack_1;
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-- decode request type in shift register
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with shiftr(1 downto 0) select op_valid <=
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'1' when DMI_REQ_RD,
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'1' when DMI_REQ_WR,
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'0' when others;
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-- encode response op
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rsp_op <= DMI_RSP_BSY when jtag_bsy = '1' else DMI_RSP_OK;
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-- Some DMI out signals are directly driven from the request register
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dmi_addr <= request(ABITS + DBITS + 1 downto DBITS + 2);
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dmi_dout <= request(DBITS + 1 downto 2);
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dmi_wr <= '1' when request(1 downto 0) = DMI_REQ_WR else '0';
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-- TDO is wired to shift register bit 0
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tdo <= shiftr(0);
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-- Main state machine. Handles shift registers, request latch and
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-- jtag_req latch. Could be split into 3 processes but it's probably
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-- not worthwhile.
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--
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shifter: process(jtag_clk, jtag_reset)
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begin
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if jtag_reset = '1' then
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shiftr <= (others => '0');
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jtag_req <= '0';
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elsif rising_edge(jtag_clk) then
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-- Handle jtag "commands" when sel is 1
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if sel = '1' then
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-- Shift state, rotate the register
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if shift = '1' then
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shiftr <= tdi & shiftr(ABITS + DBITS + 1 downto 1);
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end if;
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-- Update state (trigger)
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--
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-- Latch the request if we aren't already processing one and
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-- it has a valid command opcode.
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--
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if update = '1' and op_valid = '1' then
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if jtag_bsy = '0' then
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request <= shiftr;
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jtag_req <= '1';
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end if;
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-- Set the shift register "op" to "busy". This will prevent
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-- us from re-starting the command on the next update if
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-- the command completes before that.
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shiftr(1 downto 0) <= DMI_RSP_BSY;
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end if;
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-- Request completion.
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--
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-- Capture the response data for reads and clear request flag.
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--
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-- Note: We clear req (and thus dmi_req) here which relies on tck
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-- ticking and sel set. This means we are stuck with dmi_req up if
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-- the jtag interface stops. Slaves must be resilient to this.
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--
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if jtag_req = '1' and dmi_ack_1 = '1' then
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jtag_req <= '0';
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if request(1 downto 0) = DMI_REQ_RD then
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request(DBITS + 1 downto 2) <= dmi_din;
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end if;
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end if;
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-- Capture state, grab latch content with updated status
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if capture = '1' then
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shiftr <= request(ABITS + DBITS + 1 downto 2) & rsp_op;
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end if;
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end if;
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end if;
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end process;
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end architecture behaviour;
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