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microwatt/fpga
Jordan Niethe a45c503aea Connect to the caravel logic analyzer
This connects 32 read and 32 write bits to the caravel logic analyzer.

Thanks to Jordan for the original patch
4 years ago
..
LICENSE
acorn-cle-215.xdc acorn: Add support for the Acorn CLE 215+ 4 years ago
arty_a7.xdc uart: Import and hook up opencore 16550 compatible UART 4 years ago
clk_gen_bypass.vhd Fix clk_gen_bypass 5 years ago
clk_gen_ecp5.vhd Add PLL for ECP5 device 4 years ago
clk_gen_mcmm.vhd Improve PLL/MMCM clocks configuration 5 years ago
clk_gen_plle2.vhd acorn: Add support for the Acorn CLE 215+ 4 years ago
cmod_a7-35.xdc Add SPI configuration to Xilinx constraint files 5 years ago
firmware.hex
fpga-random.vhdl Add random number generator and implement the darn instruction 4 years ago
fpga-random.xdc Add random number generator and implement the darn instruction 4 years ago
genesys2.xdc fpga: Add support for Genesys2 4 years ago
hello_world.hex hello_world: Use new headers and frequency from syscon 5 years ago
main_bram.vhdl Fix some ghdlsynth issues with fpga_bram 5 years ago
main_bram_caravel.vhdl Add RAM_512x64 4 years ago
nexys-video.xdc spi: Add SPI Flash controller 5 years ago
nexys_a7.xdc Add SPI configuration to Xilinx constraint files 5 years ago
pp_fifo.vhd pp_fifo: Fix full fifo losing all data on simultaneous push & pop 5 years ago
pp_soc_uart.vhd uart: Remove combinational loops on ack and stall signal 5 years ago
pp_utilities.vhd
soc_reset.vhdl soc_reset: Use counters, add synchronizers 5 years ago
soc_reset_tb.vhdl Exit cleanly from testbench on success 5 years ago
top-acorn-cle-215.vhdl acorn: Add support for the Acorn CLE 215+ 4 years ago
top-arty.vhdl core: Add support for floating-point loads and stores 4 years ago
top-caravel.vhdl Connect to the caravel logic analyzer 4 years ago
top-generic.vhdl Add LOG_LENGTH to top-generic.vhdl 4 years ago
top-genesys2.vhdl fpga: Add support for Genesys2 4 years ago
top-nexys-video.vhdl core: Add support for floating-point loads and stores 4 years ago