//--------------------------------------------------------------------------------
// Auto-generated by Migen (27dbf03) & LiteX (78c1751c) on 2021-08-15 06:19:19
//--------------------------------------------------------------------------------
module litedram_core(
input wire sim_trace,
input wire clk,
output wire init_done,
output wire init_error,
input wire [29:0] wb_ctrl_adr,
input wire [31:0] wb_ctrl_dat_w,
output wire [31:0] wb_ctrl_dat_r,
input wire [3:0] wb_ctrl_sel,
input wire wb_ctrl_cyc,
input wire wb_ctrl_stb,
output wire wb_ctrl_ack,
input wire wb_ctrl_we,
input wire [2:0] wb_ctrl_cti,
input wire [1:0] wb_ctrl_bte,
output wire wb_ctrl_err,
output wire user_clk,
output wire user_rst,
input wire user_port_native_0_cmd_valid,
output wire user_port_native_0_cmd_ready,
input wire user_port_native_0_cmd_we,
input wire [23:0] user_port_native_0_cmd_addr,
input wire user_port_native_0_wdata_valid,
output wire user_port_native_0_wdata_ready,
input wire [15:0] user_port_native_0_wdata_we,
input wire [127:0] user_port_native_0_wdata_data,
output wire user_port_native_0_rdata_valid,
input wire user_port_native_0_rdata_ready,
output wire [127:0] user_port_native_0_rdata_data
);
wire sys_clk;
wire sys_rst;
wire por_clk;
reg soc_int_rst = 1'd1;
wire [13:0] soc_ddrphy_dfi_p0_address;
wire [2:0] soc_ddrphy_dfi_p0_bank;
wire soc_ddrphy_dfi_p0_cas_n;
wire soc_ddrphy_dfi_p0_cs_n;
wire soc_ddrphy_dfi_p0_ras_n;
wire soc_ddrphy_dfi_p0_we_n;
wire soc_ddrphy_dfi_p0_cke;
wire soc_ddrphy_dfi_p0_odt;
wire soc_ddrphy_dfi_p0_reset_n;
wire soc_ddrphy_dfi_p0_act_n;
wire [31:0] soc_ddrphy_dfi_p0_wrdata;
wire soc_ddrphy_dfi_p0_wrdata_en;
wire [3:0] soc_ddrphy_dfi_p0_wrdata_mask;
wire soc_ddrphy_dfi_p0_rddata_en;
wire [31:0] soc_ddrphy_dfi_p0_rddata;
wire soc_ddrphy_dfi_p0_rddata_valid;
wire [13:0] soc_ddrphy_dfi_p1_address;
wire [2:0] soc_ddrphy_dfi_p1_bank;
wire soc_ddrphy_dfi_p1_cas_n;
wire soc_ddrphy_dfi_p1_cs_n;
wire soc_ddrphy_dfi_p1_ras_n;
wire soc_ddrphy_dfi_p1_we_n;
wire soc_ddrphy_dfi_p1_cke;
wire soc_ddrphy_dfi_p1_odt;
wire soc_ddrphy_dfi_p1_reset_n;
wire soc_ddrphy_dfi_p1_act_n;
wire [31:0] soc_ddrphy_dfi_p1_wrdata;
wire soc_ddrphy_dfi_p1_wrdata_en;
wire [3:0] soc_ddrphy_dfi_p1_wrdata_mask;
wire soc_ddrphy_dfi_p1_rddata_en;
wire [31:0] soc_ddrphy_dfi_p1_rddata;
wire soc_ddrphy_dfi_p1_rddata_valid;
wire [13:0] soc_ddrphy_dfi_p2_address;
wire [2:0] soc_ddrphy_dfi_p2_bank;
wire soc_ddrphy_dfi_p2_cas_n;
wire soc_ddrphy_dfi_p2_cs_n;
wire soc_ddrphy_dfi_p2_ras_n;
wire soc_ddrphy_dfi_p2_we_n;
wire soc_ddrphy_dfi_p2_cke;
wire soc_ddrphy_dfi_p2_odt;
wire soc_ddrphy_dfi_p2_reset_n;
wire soc_ddrphy_dfi_p2_act_n;
wire [31:0] soc_ddrphy_dfi_p2_wrdata;
wire soc_ddrphy_dfi_p2_wrdata_en;
wire [3:0] soc_ddrphy_dfi_p2_wrdata_mask;
wire soc_ddrphy_dfi_p2_rddata_en;
wire [31:0] soc_ddrphy_dfi_p2_rddata;
wire soc_ddrphy_dfi_p2_rddata_valid;
wire [13:0] soc_ddrphy_dfi_p3_address;
wire [2:0] soc_ddrphy_dfi_p3_bank;
wire soc_ddrphy_dfi_p3_cas_n;
wire soc_ddrphy_dfi_p3_cs_n;
wire soc_ddrphy_dfi_p3_ras_n;
wire soc_ddrphy_dfi_p3_we_n;
wire soc_ddrphy_dfi_p3_cke;
wire soc_ddrphy_dfi_p3_odt;
wire soc_ddrphy_dfi_p3_reset_n;
wire soc_ddrphy_dfi_p3_act_n;
wire [31:0] soc_ddrphy_dfi_p3_wrdata;
wire soc_ddrphy_dfi_p3_wrdata_en;
wire [3:0] soc_ddrphy_dfi_p3_wrdata_mask;
wire soc_ddrphy_dfi_p3_rddata_en;
wire [31:0] soc_ddrphy_dfi_p3_rddata;
wire soc_ddrphy_dfi_p3_rddata_valid;
reg soc_ddrphy_dfiphasemodel0_activate = 1'd0;
reg soc_ddrphy_dfiphasemodel0_precharge = 1'd0;
reg soc_ddrphy_dfiphasemodel0_write = 1'd0;
reg soc_ddrphy_dfiphasemodel0_read = 1'd0;
reg soc_ddrphy_dfiphasemodel1_activate = 1'd0;
reg soc_ddrphy_dfiphasemodel1_precharge = 1'd0;
reg soc_ddrphy_dfiphasemodel1_write = 1'd0;
reg soc_ddrphy_dfiphasemodel1_read = 1'd0;
reg soc_ddrphy_dfiphasemodel2_activate = 1'd0;
reg soc_ddrphy_dfiphasemodel2_precharge = 1'd0;
reg soc_ddrphy_dfiphasemodel2_write = 1'd0;
reg soc_ddrphy_dfiphasemodel2_read = 1'd0;
reg soc_ddrphy_dfiphasemodel3_activate = 1'd0;
reg soc_ddrphy_dfiphasemodel3_precharge = 1'd0;
reg soc_ddrphy_dfiphasemodel3_write = 1'd0;
reg soc_ddrphy_dfiphasemodel3_read = 1'd0;
reg soc_ddrphy_bankmodel0_activate = 1'd0;
reg [13:0] soc_ddrphy_bankmodel0_activate_row = 14'd0;
reg soc_ddrphy_bankmodel0_precharge = 1'd0;
wire soc_ddrphy_bankmodel0_write;
wire [9:0] soc_ddrphy_bankmodel0_write_col;
wire [127:0] soc_ddrphy_bankmodel0_write_data;
wire [15:0] soc_ddrphy_bankmodel0_write_mask;
reg soc_ddrphy_bankmodel0_read = 1'd0;
reg [9:0] soc_ddrphy_bankmodel0_read_col = 10'd0;
reg [127:0] soc_ddrphy_bankmodel0_read_data = 128'd0;
reg soc_ddrphy_bankmodel0_active = 1'd0;
reg [13:0] soc_ddrphy_bankmodel0_row = 14'd0;
reg [20:0] soc_ddrphy_bankmodel0_write_port_adr = 21'd0;
wire [127:0] soc_ddrphy_bankmodel0_write_port_dat_r;
reg [15:0] soc_ddrphy_bankmodel0_write_port_we = 16'd0;
reg [127:0] soc_ddrphy_bankmodel0_write_port_dat_w = 128'd0;
reg [20:0] soc_ddrphy_bankmodel0_read_port_adr = 21'd0;
wire [127:0] soc_ddrphy_bankmodel0_read_port_dat_r;
wire [20:0] soc_ddrphy_bankmodel0_wraddr;
wire [20:0] soc_ddrphy_bankmodel0_rdaddr;
reg soc_ddrphy_bankmodel1_activate = 1'd0;
reg [13:0] soc_ddrphy_bankmodel1_activate_row = 14'd0;
reg soc_ddrphy_bankmodel1_precharge = 1'd0;
wire soc_ddrphy_bankmodel1_write;
wire [9:0] soc_ddrphy_bankmodel1_write_col;
wire [127:0] soc_ddrphy_bankmodel1_write_data;
wire [15:0] soc_ddrphy_bankmodel1_write_mask;
reg soc_ddrphy_bankmodel1_read = 1'd0;
reg [9:0] soc_ddrphy_bankmodel1_read_col = 10'd0;
reg [127:0] soc_ddrphy_bankmodel1_read_data = 128'd0;
reg soc_ddrphy_bankmodel1_active = 1'd0;
reg [13:0] soc_ddrphy_bankmodel1_row = 14'd0;
reg [20:0] soc_ddrphy_bankmodel1_write_port_adr = 21'd0;
wire [127:0] soc_ddrphy_bankmodel1_write_port_dat_r;
reg [15:0] soc_ddrphy_bankmodel1_write_port_we = 16'd0;
reg [127:0] soc_ddrphy_bankmodel1_write_port_dat_w = 128'd0;
reg [20:0] soc_ddrphy_bankmodel1_read_port_adr = 21'd0;
wire [127:0] soc_ddrphy_bankmodel1_read_port_dat_r;
wire [20:0] soc_ddrphy_bankmodel1_wraddr;
wire [20:0] soc_ddrphy_bankmodel1_rdaddr;
reg soc_ddrphy_bankmodel2_activate = 1'd0;
reg [13:0] soc_ddrphy_bankmodel2_activate_row = 14'd0;
reg soc_ddrphy_bankmodel2_precharge = 1'd0;
wire soc_ddrphy_bankmodel2_write;
wire [9:0] soc_ddrphy_bankmodel2_write_col;
wire [127:0] soc_ddrphy_bankmodel2_write_data;
wire [15:0] soc_ddrphy_bankmodel2_write_mask;
reg soc_ddrphy_bankmodel2_read = 1'd0;
reg [9:0] soc_ddrphy_bankmodel2_read_col = 10'd0;
reg [127:0] soc_ddrphy_bankmodel2_read_data = 128'd0;
reg soc_ddrphy_bankmodel2_active = 1'd0;
reg [13:0] soc_ddrphy_bankmodel2_row = 14'd0;
reg [20:0] soc_ddrphy_bankmodel2_write_port_adr = 21'd0;
wire [127:0] soc_ddrphy_bankmodel2_write_port_dat_r;
reg [15:0] soc_ddrphy_bankmodel2_write_port_we = 16'd0;
reg [127:0] soc_ddrphy_bankmodel2_write_port_dat_w = 128'd0;
reg [20:0] soc_ddrphy_bankmodel2_read_port_adr = 21'd0;
wire [127:0] soc_ddrphy_bankmodel2_read_port_dat_r;
wire [20:0] soc_ddrphy_bankmodel2_wraddr;
wire [20:0] soc_ddrphy_bankmodel2_rdaddr;
reg soc_ddrphy_bankmodel3_activate = 1'd0;
reg [13:0] soc_ddrphy_bankmodel3_activate_row = 14'd0;
reg soc_ddrphy_bankmodel3_precharge = 1'd0;
wire soc_ddrphy_bankmodel3_write;
wire [9:0] soc_ddrphy_bankmodel3_write_col;
wire [127:0] soc_ddrphy_bankmodel3_write_data;
wire [15:0] soc_ddrphy_bankmodel3_write_mask;
reg soc_ddrphy_bankmodel3_read = 1'd0;
reg [9:0] soc_ddrphy_bankmodel3_read_col = 10'd0;
reg [127:0] soc_ddrphy_bankmodel3_read_data = 128'd0;
reg soc_ddrphy_bankmodel3_active = 1'd0;
reg [13:0] soc_ddrphy_bankmodel3_row = 14'd0;
reg [20:0] soc_ddrphy_bankmodel3_write_port_adr = 21'd0;
wire [127:0] soc_ddrphy_bankmodel3_write_port_dat_r;
reg [15:0] soc_ddrphy_bankmodel3_write_port_we = 16'd0;
reg [127:0] soc_ddrphy_bankmodel3_write_port_dat_w = 128'd0;
reg [20:0] soc_ddrphy_bankmodel3_read_port_adr = 21'd0;
wire [127:0] soc_ddrphy_bankmodel3_read_port_dat_r;
wire [20:0] soc_ddrphy_bankmodel3_wraddr;
wire [20:0] soc_ddrphy_bankmodel3_rdaddr;
reg soc_ddrphy_bankmodel4_activate = 1'd0;
reg [13:0] soc_ddrphy_bankmodel4_activate_row = 14'd0;
reg soc_ddrphy_bankmodel4_precharge = 1'd0;
wire soc_ddrphy_bankmodel4_write;
wire [9:0] soc_ddrphy_bankmodel4_write_col;
wire [127:0] soc_ddrphy_bankmodel4_write_data;
wire [15:0] soc_ddrphy_bankmodel4_write_mask;
reg soc_ddrphy_bankmodel4_read = 1'd0;
reg [9:0] soc_ddrphy_bankmodel4_read_col = 10'd0;
reg [127:0] soc_ddrphy_bankmodel4_read_data = 128'd0;
reg soc_ddrphy_bankmodel4_active = 1'd0;
reg [13:0] soc_ddrphy_bankmodel4_row = 14'd0;
reg [20:0] soc_ddrphy_bankmodel4_write_port_adr = 21'd0;
wire [127:0] soc_ddrphy_bankmodel4_write_port_dat_r;
reg [15:0] soc_ddrphy_bankmodel4_write_port_we = 16'd0;
reg [127:0] soc_ddrphy_bankmodel4_write_port_dat_w = 128'd0;
reg [20:0] soc_ddrphy_bankmodel4_read_port_adr = 21'd0;
wire [127:0] soc_ddrphy_bankmodel4_read_port_dat_r;
wire [20:0] soc_ddrphy_bankmodel4_wraddr;
wire [20:0] soc_ddrphy_bankmodel4_rdaddr;
reg soc_ddrphy_bankmodel5_activate = 1'd0;
reg [13:0] soc_ddrphy_bankmodel5_activate_row = 14'd0;
reg soc_ddrphy_bankmodel5_precharge = 1'd0;
wire soc_ddrphy_bankmodel5_write;
wire [9:0] soc_ddrphy_bankmodel5_write_col;
wire [127:0] soc_ddrphy_bankmodel5_write_data;
wire [15:0] soc_ddrphy_bankmodel5_write_mask;
reg soc_ddrphy_bankmodel5_read = 1'd0;
reg [9:0] soc_ddrphy_bankmodel5_read_col = 10'd0;
reg [127:0] soc_ddrphy_bankmodel5_read_data = 128'd0;
reg soc_ddrphy_bankmodel5_active = 1'd0;
reg [13:0] soc_ddrphy_bankmodel5_row = 14'd0;
reg [20:0] soc_ddrphy_bankmodel5_write_port_adr = 21'd0;
wire [127:0] soc_ddrphy_bankmodel5_write_port_dat_r;
reg [15:0] soc_ddrphy_bankmodel5_write_port_we = 16'd0;
reg [127:0] soc_ddrphy_bankmodel5_write_port_dat_w = 128'd0;
reg [20:0] soc_ddrphy_bankmodel5_read_port_adr = 21'd0;
wire [127:0] soc_ddrphy_bankmodel5_read_port_dat_r;
wire [20:0] soc_ddrphy_bankmodel5_wraddr;
wire [20:0] soc_ddrphy_bankmodel5_rdaddr;
reg soc_ddrphy_bankmodel6_activate = 1'd0;
reg [13:0] soc_ddrphy_bankmodel6_activate_row = 14'd0;
reg soc_ddrphy_bankmodel6_precharge = 1'd0;
wire soc_ddrphy_bankmodel6_write;
wire [9:0] soc_ddrphy_bankmodel6_write_col;
wire [127:0] soc_ddrphy_bankmodel6_write_data;
wire [15:0] soc_ddrphy_bankmodel6_write_mask;
reg soc_ddrphy_bankmodel6_read = 1'd0;
reg [9:0] soc_ddrphy_bankmodel6_read_col = 10'd0;
reg [127:0] soc_ddrphy_bankmodel6_read_data = 128'd0;
reg soc_ddrphy_bankmodel6_active = 1'd0;
reg [13:0] soc_ddrphy_bankmodel6_row = 14'd0;
reg [20:0] soc_ddrphy_bankmodel6_write_port_adr = 21'd0;
wire [127:0] soc_ddrphy_bankmodel6_write_port_dat_r;
reg [15:0] soc_ddrphy_bankmodel6_write_port_we = 16'd0;
reg [127:0] soc_ddrphy_bankmodel6_write_port_dat_w = 128'd0;
reg [20:0] soc_ddrphy_bankmodel6_read_port_adr = 21'd0;
wire [127:0] soc_ddrphy_bankmodel6_read_port_dat_r;
wire [20:0] soc_ddrphy_bankmodel6_wraddr;
wire [20:0] soc_ddrphy_bankmodel6_rdaddr;
reg soc_ddrphy_bankmodel7_activate = 1'd0;
reg [13:0] soc_ddrphy_bankmodel7_activate_row = 14'd0;
reg soc_ddrphy_bankmodel7_precharge = 1'd0;
wire soc_ddrphy_bankmodel7_write;
wire [9:0] soc_ddrphy_bankmodel7_write_col;
wire [127:0] soc_ddrphy_bankmodel7_write_data;
wire [15:0] soc_ddrphy_bankmodel7_write_mask;
reg soc_ddrphy_bankmodel7_read = 1'd0;
reg [9:0] soc_ddrphy_bankmodel7_read_col = 10'd0;
reg [127:0] soc_ddrphy_bankmodel7_read_data = 128'd0;
reg soc_ddrphy_bankmodel7_active = 1'd0;
reg [13:0] soc_ddrphy_bankmodel7_row = 14'd0;
reg [20:0] soc_ddrphy_bankmodel7_write_port_adr = 21'd0;
wire [127:0] soc_ddrphy_bankmodel7_write_port_dat_r;
reg [15:0] soc_ddrphy_bankmodel7_write_port_we = 16'd0;
reg [127:0] soc_ddrphy_bankmodel7_write_port_dat_w = 128'd0;
reg [20:0] soc_ddrphy_bankmodel7_read_port_adr = 21'd0;
wire [127:0] soc_ddrphy_bankmodel7_read_port_dat_r;
wire [20:0] soc_ddrphy_bankmodel7_wraddr;
wire [20:0] soc_ddrphy_bankmodel7_rdaddr;
reg [3:0] soc_ddrphy_activates0 = 4'd0;
reg [3:0] soc_ddrphy_precharges0 = 4'd0;
reg soc_ddrphy_bank_write0 = 1'd0;
reg [9:0] soc_ddrphy_bank_write_col0 = 10'd0;
reg [3:0] soc_ddrphy_writes0 = 4'd0;
reg soc_ddrphy_new_bank_write0 = 1'd0;
reg [9:0] soc_ddrphy_new_bank_write_col0 = 10'd0;
reg [3:0] soc_ddrphy_reads0 = 4'd0;
reg [3:0] soc_ddrphy_activates1 = 4'd0;
reg [3:0] soc_ddrphy_precharges1 = 4'd0;
reg soc_ddrphy_bank_write1 = 1'd0;
reg [9:0] soc_ddrphy_bank_write_col1 = 10'd0;
reg [3:0] soc_ddrphy_writes1 = 4'd0;
reg soc_ddrphy_new_bank_write1 = 1'd0;
reg [9:0] soc_ddrphy_new_bank_write_col1 = 10'd0;
reg [3:0] soc_ddrphy_reads1 = 4'd0;
reg [3:0] soc_ddrphy_activates2 = 4'd0;
reg [3:0] soc_ddrphy_precharges2 = 4'd0;
reg soc_ddrphy_bank_write2 = 1'd0;
reg [9:0] soc_ddrphy_bank_write_col2 = 10'd0;
reg [3:0] soc_ddrphy_writes2 = 4'd0;
reg soc_ddrphy_new_bank_write2 = 1'd0;
reg [9:0] soc_ddrphy_new_bank_write_col2 = 10'd0;
reg [3:0] soc_ddrphy_reads2 = 4'd0;
reg [3:0] soc_ddrphy_activates3 = 4'd0;
reg [3:0] soc_ddrphy_precharges3 = 4'd0;
reg soc_ddrphy_bank_write3 = 1'd0;
reg [9:0] soc_ddrphy_bank_write_col3 = 10'd0;
reg [3:0] soc_ddrphy_writes3 = 4'd0;
reg soc_ddrphy_new_bank_write3 = 1'd0;
reg [9:0] soc_ddrphy_new_bank_write_col3 = 10'd0;
reg [3:0] soc_ddrphy_reads3 = 4'd0;
reg [3:0] soc_ddrphy_activates4 = 4'd0;
reg [3:0] soc_ddrphy_precharges4 = 4'd0;
reg soc_ddrphy_bank_write4 = 1'd0;
reg [9:0] soc_ddrphy_bank_write_col4 = 10'd0;
reg [3:0] soc_ddrphy_writes4 = 4'd0;
reg soc_ddrphy_new_bank_write4 = 1'd0;
reg [9:0] soc_ddrphy_new_bank_write_col4 = 10'd0;
reg [3:0] soc_ddrphy_reads4 = 4'd0;
reg [3:0] soc_ddrphy_activates5 = 4'd0;
reg [3:0] soc_ddrphy_precharges5 = 4'd0;
reg soc_ddrphy_bank_write5 = 1'd0;
reg [9:0] soc_ddrphy_bank_write_col5 = 10'd0;
reg [3:0] soc_ddrphy_writes5 = 4'd0;
reg soc_ddrphy_new_bank_write5 = 1'd0;
reg [9:0] soc_ddrphy_new_bank_write_col5 = 10'd0;
reg [3:0] soc_ddrphy_reads5 = 4'd0;
reg [3:0] soc_ddrphy_activates6 = 4'd0;
reg [3:0] soc_ddrphy_precharges6 = 4'd0;
reg soc_ddrphy_bank_write6 = 1'd0;
reg [9:0] soc_ddrphy_bank_write_col6 = 10'd0;
reg [3:0] soc_ddrphy_writes6 = 4'd0;
reg soc_ddrphy_new_bank_write6 = 1'd0;
reg [9:0] soc_ddrphy_new_bank_write_col6 = 10'd0;
reg [3:0] soc_ddrphy_reads6 = 4'd0;
reg [3:0] soc_ddrphy_activates7 = 4'd0;
reg [3:0] soc_ddrphy_precharges7 = 4'd0;
reg soc_ddrphy_bank_write7 = 1'd0;
reg [9:0] soc_ddrphy_bank_write_col7 = 10'd0;
reg [3:0] soc_ddrphy_writes7 = 4'd0;
reg soc_ddrphy_new_bank_write7 = 1'd0;
reg [9:0] soc_ddrphy_new_bank_write_col7 = 10'd0;
reg [3:0] soc_ddrphy_reads7 = 4'd0;
wire soc_ddrphy_banks_read;
wire [127:0] soc_ddrphy_banks_read_data;
reg soc_ddrphy_new_banks_read0 = 1'd0;
reg [127:0] soc_ddrphy_new_banks_read_data0 = 128'd0;
reg soc_ddrphy_new_banks_read1 = 1'd0;
reg [127:0] soc_ddrphy_new_banks_read_data1 = 128'd0;
reg soc_ddrphy_new_banks_read2 = 1'd0;
reg [127:0] soc_ddrphy_new_banks_read_data2 = 128'd0;
reg soc_ddrphy_new_banks_read3 = 1'd0;
reg [127:0] soc_ddrphy_new_banks_read_data3 = 128'd0;
reg soc_ddrphy_new_banks_read4 = 1'd0;
reg [127:0] soc_ddrphy_new_banks_read_data4 = 128'd0;
reg soc_ddrphy_new_banks_read5 = 1'd0;
reg [127:0] soc_ddrphy_new_banks_read_data5 = 128'd0;
reg soc_ddrphy_new_banks_read6 = 1'd0;
reg [127:0] soc_ddrphy_new_banks_read_data6 = 128'd0;
reg soc_ddrphy_new_banks_read7 = 1'd0;
reg [127:0] soc_ddrphy_new_banks_read_data7 = 128'd0;
wire [13:0] soc_litedramcore_inti_p0_address;
wire [2:0] soc_litedramcore_inti_p0_bank;
reg soc_litedramcore_inti_p0_cas_n = 1'd1;
reg soc_litedramcore_inti_p0_cs_n = 1'd1;
reg soc_litedramcore_inti_p0_ras_n = 1'd1;
reg soc_litedramcore_inti_p0_we_n = 1'd1;
wire soc_litedramcore_inti_p0_cke;
wire soc_litedramcore_inti_p0_odt;
wire soc_litedramcore_inti_p0_reset_n;
reg soc_litedramcore_inti_p0_act_n = 1'd1;
wire [31:0] soc_litedramcore_inti_p0_wrdata;
wire soc_litedramcore_inti_p0_wrdata_en;
wire [3:0] soc_litedramcore_inti_p0_wrdata_mask;
wire soc_litedramcore_inti_p0_rddata_en;
reg [31:0] soc_litedramcore_inti_p0_rddata = 32'd0;
reg soc_litedramcore_inti_p0_rddata_valid = 1'd0;
wire [13:0] soc_litedramcore_inti_p1_address;
wire [2:0] soc_litedramcore_inti_p1_bank;
reg soc_litedramcore_inti_p1_cas_n = 1'd1;
reg soc_litedramcore_inti_p1_cs_n = 1'd1;
reg soc_litedramcore_inti_p1_ras_n = 1'd1;
reg soc_litedramcore_inti_p1_we_n = 1'd1;
wire soc_litedramcore_inti_p1_cke;
wire soc_litedramcore_inti_p1_odt;
wire soc_litedramcore_inti_p1_reset_n;
reg soc_litedramcore_inti_p1_act_n = 1'd1;
wire [31:0] soc_litedramcore_inti_p1_wrdata;
wire soc_litedramcore_inti_p1_wrdata_en;
wire [3:0] soc_litedramcore_inti_p1_wrdata_mask;
wire soc_litedramcore_inti_p1_rddata_en;
reg [31:0] soc_litedramcore_inti_p1_rddata = 32'd0;
reg soc_litedramcore_inti_p1_rddata_valid = 1'd0;
wire [13:0] soc_litedramcore_inti_p2_address;
wire [2:0] soc_litedramcore_inti_p2_bank;
reg soc_litedramcore_inti_p2_cas_n = 1'd1;
reg soc_litedramcore_inti_p2_cs_n = 1'd1;
reg soc_litedramcore_inti_p2_ras_n = 1'd1;
reg soc_litedramcore_inti_p2_we_n = 1'd1;
wire soc_litedramcore_inti_p2_cke;
wire soc_litedramcore_inti_p2_odt;
wire soc_litedramcore_inti_p2_reset_n;
reg soc_litedramcore_inti_p2_act_n = 1'd1;
wire [31:0] soc_litedramcore_inti_p2_wrdata;
wire soc_litedramcore_inti_p2_wrdata_en;
wire [3:0] soc_litedramcore_inti_p2_wrdata_mask;
wire soc_litedramcore_inti_p2_rddata_en;
reg [31:0] soc_litedramcore_inti_p2_rddata = 32'd0;
reg soc_litedramcore_inti_p2_rddata_valid = 1'd0;
wire [13:0] soc_litedramcore_inti_p3_address;
wire [2:0] soc_litedramcore_inti_p3_bank;
reg soc_litedramcore_inti_p3_cas_n = 1'd1;
reg soc_litedramcore_inti_p3_cs_n = 1'd1;
reg soc_litedramcore_inti_p3_ras_n = 1'd1;
reg soc_litedramcore_inti_p3_we_n = 1'd1;
wire soc_litedramcore_inti_p3_cke;
wire soc_litedramcore_inti_p3_odt;
wire soc_litedramcore_inti_p3_reset_n;
reg soc_litedramcore_inti_p3_act_n = 1'd1;
wire [31:0] soc_litedramcore_inti_p3_wrdata;
wire soc_litedramcore_inti_p3_wrdata_en;
wire [3:0] soc_litedramcore_inti_p3_wrdata_mask;
wire soc_litedramcore_inti_p3_rddata_en;
reg [31:0] soc_litedramcore_inti_p3_rddata = 32'd0;
reg soc_litedramcore_inti_p3_rddata_valid = 1'd0;
wire [13:0] soc_litedramcore_slave_p0_address;
wire [2:0] soc_litedramcore_slave_p0_bank;
wire soc_litedramcore_slave_p0_cas_n;
wire soc_litedramcore_slave_p0_cs_n;
wire soc_litedramcore_slave_p0_ras_n;
wire soc_litedramcore_slave_p0_we_n;
wire soc_litedramcore_slave_p0_cke;
wire soc_litedramcore_slave_p0_odt;
wire soc_litedramcore_slave_p0_reset_n;
wire soc_litedramcore_slave_p0_act_n;
wire [31:0] soc_litedramcore_slave_p0_wrdata;
wire soc_litedramcore_slave_p0_wrdata_en;
wire [3:0] soc_litedramcore_slave_p0_wrdata_mask;
wire soc_litedramcore_slave_p0_rddata_en;
reg [31:0] soc_litedramcore_slave_p0_rddata = 32'd0;
reg soc_litedramcore_slave_p0_rddata_valid = 1'd0;
wire [13:0] soc_litedramcore_slave_p1_address;
wire [2:0] soc_litedramcore_slave_p1_bank;
wire soc_litedramcore_slave_p1_cas_n;
wire soc_litedramcore_slave_p1_cs_n;
wire soc_litedramcore_slave_p1_ras_n;
wire soc_litedramcore_slave_p1_we_n;
wire soc_litedramcore_slave_p1_cke;
wire soc_litedramcore_slave_p1_odt;
wire soc_litedramcore_slave_p1_reset_n;
wire soc_litedramcore_slave_p1_act_n;
wire [31:0] soc_litedramcore_slave_p1_wrdata;
wire soc_litedramcore_slave_p1_wrdata_en;
wire [3:0] soc_litedramcore_slave_p1_wrdata_mask;
wire soc_litedramcore_slave_p1_rddata_en;
reg [31:0] soc_litedramcore_slave_p1_rddata = 32'd0;
reg soc_litedramcore_slave_p1_rddata_valid = 1'd0;
wire [13:0] soc_litedramcore_slave_p2_address;
wire [2:0] soc_litedramcore_slave_p2_bank;
wire soc_litedramcore_slave_p2_cas_n;
wire soc_litedramcore_slave_p2_cs_n;
wire soc_litedramcore_slave_p2_ras_n;
wire soc_litedramcore_slave_p2_we_n;
wire soc_litedramcore_slave_p2_cke;
wire soc_litedramcore_slave_p2_odt;
wire soc_litedramcore_slave_p2_reset_n;
wire soc_litedramcore_slave_p2_act_n;
wire [31:0] soc_litedramcore_slave_p2_wrdata;
wire soc_litedramcore_slave_p2_wrdata_en;
wire [3:0] soc_litedramcore_slave_p2_wrdata_mask;
wire soc_litedramcore_slave_p2_rddata_en;
reg [31:0] soc_litedramcore_slave_p2_rddata = 32'd0;
reg soc_litedramcore_slave_p2_rddata_valid = 1'd0;
wire [13:0] soc_litedramcore_slave_p3_address;
wire [2:0] soc_litedramcore_slave_p3_bank;
wire soc_litedramcore_slave_p3_cas_n;
wire soc_litedramcore_slave_p3_cs_n;
wire soc_litedramcore_slave_p3_ras_n;
wire soc_litedramcore_slave_p3_we_n;
wire soc_litedramcore_slave_p3_cke;
wire soc_litedramcore_slave_p3_odt;
wire soc_litedramcore_slave_p3_reset_n;
wire soc_litedramcore_slave_p3_act_n;
wire [31:0] soc_litedramcore_slave_p3_wrdata;
wire soc_litedramcore_slave_p3_wrdata_en;
wire [3:0] soc_litedramcore_slave_p3_wrdata_mask;
wire soc_litedramcore_slave_p3_rddata_en;
reg [31:0] soc_litedramcore_slave_p3_rddata = 32'd0;
reg soc_litedramcore_slave_p3_rddata_valid = 1'd0;
reg [13:0] soc_litedramcore_master_p0_address = 14'd0;
reg [2:0] soc_litedramcore_master_p0_bank = 3'd0;
reg soc_litedramcore_master_p0_cas_n = 1'd1;
reg soc_litedramcore_master_p0_cs_n = 1'd1;
reg soc_litedramcore_master_p0_ras_n = 1'd1;
reg soc_litedramcore_master_p0_we_n = 1'd1;
reg soc_litedramcore_master_p0_cke = 1'd0;
reg soc_litedramcore_master_p0_odt = 1'd0;
reg soc_litedramcore_master_p0_reset_n = 1'd0;
reg soc_litedramcore_master_p0_act_n = 1'd1;
reg [31:0] soc_litedramcore_master_p0_wrdata = 32'd0;
reg soc_litedramcore_master_p0_wrdata_en = 1'd0;
reg [3:0] soc_litedramcore_master_p0_wrdata_mask = 4'd0;
reg soc_litedramcore_master_p0_rddata_en = 1'd0;
wire [31:0] soc_litedramcore_master_p0_rddata;
wire soc_litedramcore_master_p0_rddata_valid;
reg [13:0] soc_litedramcore_master_p1_address = 14'd0;
reg [2:0] soc_litedramcore_master_p1_bank = 3'd0;
reg soc_litedramcore_master_p1_cas_n = 1'd1;
reg soc_litedramcore_master_p1_cs_n = 1'd1;
reg soc_litedramcore_master_p1_ras_n = 1'd1;
reg soc_litedramcore_master_p1_we_n = 1'd1;
reg soc_litedramcore_master_p1_cke = 1'd0;
reg soc_litedramcore_master_p1_odt = 1'd0;
reg soc_litedramcore_master_p1_reset_n = 1'd0;
reg soc_litedramcore_master_p1_act_n = 1'd1;
reg [31:0] soc_litedramcore_master_p1_wrdata = 32'd0;
reg soc_litedramcore_master_p1_wrdata_en = 1'd0;
reg [3:0] soc_litedramcore_master_p1_wrdata_mask = 4'd0;
reg soc_litedramcore_master_p1_rddata_en = 1'd0;
wire [31:0] soc_litedramcore_master_p1_rddata;
wire soc_litedramcore_master_p1_rddata_valid;
reg [13:0] soc_litedramcore_master_p2_address = 14'd0;
reg [2:0] soc_litedramcore_master_p2_bank = 3'd0;
reg soc_litedramcore_master_p2_cas_n = 1'd1;
reg soc_litedramcore_master_p2_cs_n = 1'd1;
reg soc_litedramcore_master_p2_ras_n = 1'd1;
reg soc_litedramcore_master_p2_we_n = 1'd1;
reg soc_litedramcore_master_p2_cke = 1'd0;
reg soc_litedramcore_master_p2_odt = 1'd0;
reg soc_litedramcore_master_p2_reset_n = 1'd0;
reg soc_litedramcore_master_p2_act_n = 1'd1;
reg [31:0] soc_litedramcore_master_p2_wrdata = 32'd0;
reg soc_litedramcore_master_p2_wrdata_en = 1'd0;
reg [3:0] soc_litedramcore_master_p2_wrdata_mask = 4'd0;
reg soc_litedramcore_master_p2_rddata_en = 1'd0;
wire [31:0] soc_litedramcore_master_p2_rddata;
wire soc_litedramcore_master_p2_rddata_valid;
reg [13:0] soc_litedramcore_master_p3_address = 14'd0;
reg [2:0] soc_litedramcore_master_p3_bank = 3'd0;
reg soc_litedramcore_master_p3_cas_n = 1'd1;
reg soc_litedramcore_master_p3_cs_n = 1'd1;
reg soc_litedramcore_master_p3_ras_n = 1'd1;
reg soc_litedramcore_master_p3_we_n = 1'd1;
reg soc_litedramcore_master_p3_cke = 1'd0;
reg soc_litedramcore_master_p3_odt = 1'd0;
reg soc_litedramcore_master_p3_reset_n = 1'd0;
reg soc_litedramcore_master_p3_act_n = 1'd1;
reg [31:0] soc_litedramcore_master_p3_wrdata = 32'd0;
reg soc_litedramcore_master_p3_wrdata_en = 1'd0;
reg [3:0] soc_litedramcore_master_p3_wrdata_mask = 4'd0;
reg soc_litedramcore_master_p3_rddata_en = 1'd0;
wire [31:0] soc_litedramcore_master_p3_rddata;
wire soc_litedramcore_master_p3_rddata_valid;
wire soc_litedramcore_sel;
wire soc_litedramcore_cke;
wire soc_litedramcore_odt;
wire soc_litedramcore_reset_n;
reg [3:0] soc_litedramcore_storage = 4'd1;
reg soc_litedramcore_re = 1'd0;
reg [5:0] soc_litedramcore_phaseinjector0_command_storage = 6'd0;
reg soc_litedramcore_phaseinjector0_command_re = 1'd0;
reg soc_litedramcore_phaseinjector0_command_issue_re = 1'd0;
wire soc_litedramcore_phaseinjector0_command_issue_r;
reg soc_litedramcore_phaseinjector0_command_issue_we = 1'd0;
reg soc_litedramcore_phaseinjector0_command_issue_w = 1'd0;
reg [13:0] soc_litedramcore_phaseinjector0_address_storage = 14'd0;
reg soc_litedramcore_phaseinjector0_address_re = 1'd0;
reg [2:0] soc_litedramcore_phaseinjector0_baddress_storage = 3'd0;
reg soc_litedramcore_phaseinjector0_baddress_re = 1'd0;
reg [31:0] soc_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
reg soc_litedramcore_phaseinjector0_wrdata_re = 1'd0;
reg [31:0] soc_litedramcore_phaseinjector0_rddata_status = 32'd0;
wire soc_litedramcore_phaseinjector0_rddata_we;
reg soc_litedramcore_phaseinjector0_rddata_re = 1'd0;
reg [5:0] soc_litedramcore_phaseinjector1_command_storage = 6'd0;
reg soc_litedramcore_phaseinjector1_command_re = 1'd0;
reg soc_litedramcore_phaseinjector1_command_issue_re = 1'd0;
wire soc_litedramcore_phaseinjector1_command_issue_r;
reg soc_litedramcore_phaseinjector1_command_issue_we = 1'd0;
reg soc_litedramcore_phaseinjector1_command_issue_w = 1'd0;
reg [13:0] soc_litedramcore_phaseinjector1_address_storage = 14'd0;
reg soc_litedramcore_phaseinjector1_address_re = 1'd0;
reg [2:0] soc_litedramcore_phaseinjector1_baddress_storage = 3'd0;
reg soc_litedramcore_phaseinjector1_baddress_re = 1'd0;
reg [31:0] soc_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
reg soc_litedramcore_phaseinjector1_wrdata_re = 1'd0;
reg [31:0] soc_litedramcore_phaseinjector1_rddata_status = 32'd0;
wire soc_litedramcore_phaseinjector1_rddata_we;
reg soc_litedramcore_phaseinjector1_rddata_re = 1'd0;
reg [5:0] soc_litedramcore_phaseinjector2_command_storage = 6'd0;
reg soc_litedramcore_phaseinjector2_command_re = 1'd0;
reg soc_litedramcore_phaseinjector2_command_issue_re = 1'd0;
wire soc_litedramcore_phaseinjector2_command_issue_r;
reg soc_litedramcore_phaseinjector2_command_issue_we = 1'd0;
reg soc_litedramcore_phaseinjector2_command_issue_w = 1'd0;
reg [13:0] soc_litedramcore_phaseinjector2_address_storage = 14'd0;
reg soc_litedramcore_phaseinjector2_address_re = 1'd0;
reg [2:0] soc_litedramcore_phaseinjector2_baddress_storage = 3'd0;
reg soc_litedramcore_phaseinjector2_baddress_re = 1'd0;
reg [31:0] soc_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
reg soc_litedramcore_phaseinjector2_wrdata_re = 1'd0;
reg [31:0] soc_litedramcore_phaseinjector2_rddata_status = 32'd0;
wire soc_litedramcore_phaseinjector2_rddata_we;
reg soc_litedramcore_phaseinjector2_rddata_re = 1'd0;
reg [5:0] soc_litedramcore_phaseinjector3_command_storage = 6'd0;
reg soc_litedramcore_phaseinjector3_command_re = 1'd0;
reg soc_litedramcore_phaseinjector3_command_issue_re = 1'd0;
wire soc_litedramcore_phaseinjector3_command_issue_r;
reg soc_litedramcore_phaseinjector3_command_issue_we = 1'd0;
reg soc_litedramcore_phaseinjector3_command_issue_w = 1'd0;
reg [13:0] soc_litedramcore_phaseinjector3_address_storage = 14'd0;
reg soc_litedramcore_phaseinjector3_address_re = 1'd0;
reg [2:0] soc_litedramcore_phaseinjector3_baddress_storage = 3'd0;
reg soc_litedramcore_phaseinjector3_baddress_re = 1'd0;
reg [31:0] soc_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
reg soc_litedramcore_phaseinjector3_wrdata_re = 1'd0;
reg [31:0] soc_litedramcore_phaseinjector3_rddata_status = 32'd0;
wire soc_litedramcore_phaseinjector3_rddata_we;
reg soc_litedramcore_phaseinjector3_rddata_re = 1'd0;
wire soc_litedramcore_interface_bank0_valid;
wire soc_litedramcore_interface_bank0_ready;
wire soc_litedramcore_interface_bank0_we;
wire [20:0] soc_litedramcore_interface_bank0_addr;
wire soc_litedramcore_interface_bank0_lock;
wire soc_litedramcore_interface_bank0_wdata_ready;
wire soc_litedramcore_interface_bank0_rdata_valid;
wire soc_litedramcore_interface_bank1_valid;
wire soc_litedramcore_interface_bank1_ready;
wire soc_litedramcore_interface_bank1_we;
wire [20:0] soc_litedramcore_interface_bank1_addr;
wire soc_litedramcore_interface_bank1_lock;
wire soc_litedramcore_interface_bank1_wdata_ready;
wire soc_litedramcore_interface_bank1_rdata_valid;
wire soc_litedramcore_interface_bank2_valid;
wire soc_litedramcore_interface_bank2_ready;
wire soc_litedramcore_interface_bank2_we;
wire [20:0] soc_litedramcore_interface_bank2_addr;
wire soc_litedramcore_interface_bank2_lock;
wire soc_litedramcore_interface_bank2_wdata_ready;
wire soc_litedramcore_interface_bank2_rdata_valid;
wire soc_litedramcore_interface_bank3_valid;
wire soc_litedramcore_interface_bank3_ready;
wire soc_litedramcore_interface_bank3_we;
wire [20:0] soc_litedramcore_interface_bank3_addr;
wire soc_litedramcore_interface_bank3_lock;
wire soc_litedramcore_interface_bank3_wdata_ready;
wire soc_litedramcore_interface_bank3_rdata_valid;
wire soc_litedramcore_interface_bank4_valid;
wire soc_litedramcore_interface_bank4_ready;
wire soc_litedramcore_interface_bank4_we;
wire [20:0] soc_litedramcore_interface_bank4_addr;
wire soc_litedramcore_interface_bank4_lock;
wire soc_litedramcore_interface_bank4_wdata_ready;
wire soc_litedramcore_interface_bank4_rdata_valid;
wire soc_litedramcore_interface_bank5_valid;
wire soc_litedramcore_interface_bank5_ready;
wire soc_litedramcore_interface_bank5_we;
wire [20:0] soc_litedramcore_interface_bank5_addr;
wire soc_litedramcore_interface_bank5_lock;
wire soc_litedramcore_interface_bank5_wdata_ready;
wire soc_litedramcore_interface_bank5_rdata_valid;
wire soc_litedramcore_interface_bank6_valid;
wire soc_litedramcore_interface_bank6_ready;
wire soc_litedramcore_interface_bank6_we;
wire [20:0] soc_litedramcore_interface_bank6_addr;
wire soc_litedramcore_interface_bank6_lock;
wire soc_litedramcore_interface_bank6_wdata_ready;
wire soc_litedramcore_interface_bank6_rdata_valid;
wire soc_litedramcore_interface_bank7_valid;
wire soc_litedramcore_interface_bank7_ready;
wire soc_litedramcore_interface_bank7_we;
wire [20:0] soc_litedramcore_interface_bank7_addr;
wire soc_litedramcore_interface_bank7_lock;
wire soc_litedramcore_interface_bank7_wdata_ready;
wire soc_litedramcore_interface_bank7_rdata_valid;
reg [127:0] soc_litedramcore_interface_wdata = 128'd0;
reg [15:0] soc_litedramcore_interface_wdata_we = 16'd0;
wire [127:0] soc_litedramcore_interface_rdata;
reg [13:0] soc_litedramcore_dfi_p0_address = 14'd0;
reg [2:0] soc_litedramcore_dfi_p0_bank = 3'd0;
reg soc_litedramcore_dfi_p0_cas_n = 1'd1;
reg soc_litedramcore_dfi_p0_cs_n = 1'd1;
reg soc_litedramcore_dfi_p0_ras_n = 1'd1;
reg soc_litedramcore_dfi_p0_we_n = 1'd1;
wire soc_litedramcore_dfi_p0_cke;
wire soc_litedramcore_dfi_p0_odt;
wire soc_litedramcore_dfi_p0_reset_n;
reg soc_litedramcore_dfi_p0_act_n = 1'd1;
wire [31:0] soc_litedramcore_dfi_p0_wrdata;
reg soc_litedramcore_dfi_p0_wrdata_en = 1'd0;
wire [3:0] soc_litedramcore_dfi_p0_wrdata_mask;
reg soc_litedramcore_dfi_p0_rddata_en = 1'd0;
wire [31:0] soc_litedramcore_dfi_p0_rddata;
wire soc_litedramcore_dfi_p0_rddata_valid;
reg [13:0] soc_litedramcore_dfi_p1_address = 14'd0;
reg [2:0] soc_litedramcore_dfi_p1_bank = 3'd0;
reg soc_litedramcore_dfi_p1_cas_n = 1'd1;
reg soc_litedramcore_dfi_p1_cs_n = 1'd1;
reg soc_litedramcore_dfi_p1_ras_n = 1'd1;
reg soc_litedramcore_dfi_p1_we_n = 1'd1;
wire soc_litedramcore_dfi_p1_cke;
wire soc_litedramcore_dfi_p1_odt;
wire soc_litedramcore_dfi_p1_reset_n;
reg soc_litedramcore_dfi_p1_act_n = 1'd1;
wire [31:0] soc_litedramcore_dfi_p1_wrdata;
reg soc_litedramcore_dfi_p1_wrdata_en = 1'd0;
wire [3:0] soc_litedramcore_dfi_p1_wrdata_mask;
reg soc_litedramcore_dfi_p1_rddata_en = 1'd0;
wire [31:0] soc_litedramcore_dfi_p1_rddata;
wire soc_litedramcore_dfi_p1_rddata_valid;
reg [13:0] soc_litedramcore_dfi_p2_address = 14'd0;
reg [2:0] soc_litedramcore_dfi_p2_bank = 3'd0;
reg soc_litedramcore_dfi_p2_cas_n = 1'd1;
reg soc_litedramcore_dfi_p2_cs_n = 1'd1;
reg soc_litedramcore_dfi_p2_ras_n = 1'd1;
reg soc_litedramcore_dfi_p2_we_n = 1'd1;
wire soc_litedramcore_dfi_p2_cke;
wire soc_litedramcore_dfi_p2_odt;
wire soc_litedramcore_dfi_p2_reset_n;
reg soc_litedramcore_dfi_p2_act_n = 1'd1;
wire [31:0] soc_litedramcore_dfi_p2_wrdata;
reg soc_litedramcore_dfi_p2_wrdata_en = 1'd0;
wire [3:0] soc_litedramcore_dfi_p2_wrdata_mask;
reg soc_litedramcore_dfi_p2_rddata_en = 1'd0;
wire [31:0] soc_litedramcore_dfi_p2_rddata;
wire soc_litedramcore_dfi_p2_rddata_valid;
reg [13:0] soc_litedramcore_dfi_p3_address = 14'd0;
reg [2:0] soc_litedramcore_dfi_p3_bank = 3'd0;
reg soc_litedramcore_dfi_p3_cas_n = 1'd1;
reg soc_litedramcore_dfi_p3_cs_n = 1'd1;
reg soc_litedramcore_dfi_p3_ras_n = 1'd1;
reg soc_litedramcore_dfi_p3_we_n = 1'd1;
wire soc_litedramcore_dfi_p3_cke;
wire soc_litedramcore_dfi_p3_odt;
wire soc_litedramcore_dfi_p3_reset_n;
reg soc_litedramcore_dfi_p3_act_n = 1'd1;
wire [31:0] soc_litedramcore_dfi_p3_wrdata;
reg soc_litedramcore_dfi_p3_wrdata_en = 1'd0;
wire [3:0] soc_litedramcore_dfi_p3_wrdata_mask;
reg soc_litedramcore_dfi_p3_rddata_en = 1'd0;
wire [31:0] soc_litedramcore_dfi_p3_rddata;
wire soc_litedramcore_dfi_p3_rddata_valid;
reg soc_litedramcore_cmd_valid = 1'd0;
reg soc_litedramcore_cmd_ready = 1'd0;
reg soc_litedramcore_cmd_last = 1'd0;
reg [13:0] soc_litedramcore_cmd_payload_a = 14'd0;
reg [2:0] soc_litedramcore_cmd_payload_ba = 3'd0;
reg soc_litedramcore_cmd_payload_cas = 1'd0;
reg soc_litedramcore_cmd_payload_ras = 1'd0;
reg soc_litedramcore_cmd_payload_we = 1'd0;
reg soc_litedramcore_cmd_payload_is_read = 1'd0;
reg soc_litedramcore_cmd_payload_is_write = 1'd0;
wire soc_litedramcore_wants_refresh;
wire soc_litedramcore_wants_zqcs;
wire soc_litedramcore_timer_wait;
wire soc_litedramcore_timer_done0;
wire [9:0] soc_litedramcore_timer_count0;
wire soc_litedramcore_timer_done1;
reg [9:0] soc_litedramcore_timer_count1 = 10'd781;
wire soc_litedramcore_postponer_req_i;
reg soc_litedramcore_postponer_req_o = 1'd0;
reg soc_litedramcore_postponer_count = 1'd0;
reg soc_litedramcore_sequencer_start0 = 1'd0;
wire soc_litedramcore_sequencer_done0;
wire soc_litedramcore_sequencer_start1;
reg soc_litedramcore_sequencer_done1 = 1'd0;
reg [5:0] soc_litedramcore_sequencer_counter = 6'd0;
reg soc_litedramcore_sequencer_count = 1'd0;
wire soc_litedramcore_zqcs_timer_wait;
wire soc_litedramcore_zqcs_timer_done0;
wire [26:0] soc_litedramcore_zqcs_timer_count0;
wire soc_litedramcore_zqcs_timer_done1;
reg [26:0] soc_litedramcore_zqcs_timer_count1 = 27'd99999999;
reg soc_litedramcore_zqcs_executer_start = 1'd0;
reg soc_litedramcore_zqcs_executer_done = 1'd0;
reg [4:0] soc_litedramcore_zqcs_executer_counter = 5'd0;
wire soc_litedramcore_bankmachine0_req_valid;
wire soc_litedramcore_bankmachine0_req_ready;
wire soc_litedramcore_bankmachine0_req_we;
wire [20:0] soc_litedramcore_bankmachine0_req_addr;
wire soc_litedramcore_bankmachine0_req_lock;
reg soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
reg soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
wire soc_litedramcore_bankmachine0_refresh_req;
reg soc_litedramcore_bankmachine0_refresh_gnt = 1'd0;
reg soc_litedramcore_bankmachine0_cmd_valid = 1'd0;
reg soc_litedramcore_bankmachine0_cmd_ready = 1'd0;
reg [13:0] soc_litedramcore_bankmachine0_cmd_payload_a = 14'd0;
wire [2:0] soc_litedramcore_bankmachine0_cmd_payload_ba;
reg soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
reg soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
reg soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
reg soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
reg soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
reg soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
reg soc_litedramcore_bankmachine0_auto_precharge = 1'd0;
wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
reg [4:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
wire [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
wire soc_litedramcore_bankmachine0_cmd_buffer_sink_valid;
wire soc_litedramcore_bankmachine0_cmd_buffer_sink_ready;
wire soc_litedramcore_bankmachine0_cmd_buffer_sink_first;
wire soc_litedramcore_bankmachine0_cmd_buffer_sink_last;
wire soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
reg soc_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
wire soc_litedramcore_bankmachine0_cmd_buffer_source_ready;
reg soc_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
reg soc_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
reg soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0;
reg [13:0] soc_litedramcore_bankmachine0_row = 14'd0;
reg soc_litedramcore_bankmachine0_row_opened = 1'd0;
wire soc_litedramcore_bankmachine0_row_hit;
reg soc_litedramcore_bankmachine0_row_open = 1'd0;
reg soc_litedramcore_bankmachine0_row_close = 1'd0;
reg soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
wire soc_litedramcore_bankmachine0_twtpcon_valid;
reg soc_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
reg [2:0] soc_litedramcore_bankmachine0_twtpcon_count = 3'd0;
wire soc_litedramcore_bankmachine0_trccon_valid;
reg soc_litedramcore_bankmachine0_trccon_ready = 1'd0;
reg [2:0] soc_litedramcore_bankmachine0_trccon_count = 3'd0;
wire soc_litedramcore_bankmachine0_trascon_valid;
reg soc_litedramcore_bankmachine0_trascon_ready = 1'd0;
reg [2:0] soc_litedramcore_bankmachine0_trascon_count = 3'd0;
wire soc_litedramcore_bankmachine1_req_valid;
wire soc_litedramcore_bankmachine1_req_ready;
wire soc_litedramcore_bankmachine1_req_we;
wire [20:0] soc_litedramcore_bankmachine1_req_addr;
wire soc_litedramcore_bankmachine1_req_lock;
reg soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
reg soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
wire soc_litedramcore_bankmachine1_refresh_req;
reg soc_litedramcore_bankmachine1_refresh_gnt = 1'd0;
reg soc_litedramcore_bankmachine1_cmd_valid = 1'd0;
reg soc_litedramcore_bankmachine1_cmd_ready = 1'd0;
reg [13:0] soc_litedramcore_bankmachine1_cmd_payload_a = 14'd0;
wire [2:0] soc_litedramcore_bankmachine1_cmd_payload_ba;
reg soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
reg soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
reg soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
reg soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
reg soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
reg soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
reg soc_litedramcore_bankmachine1_auto_precharge = 1'd0;
wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
reg [4:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
wire [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
wire soc_litedramcore_bankmachine1_cmd_buffer_sink_valid;
wire soc_litedramcore_bankmachine1_cmd_buffer_sink_ready;
wire soc_litedramcore_bankmachine1_cmd_buffer_sink_first;
wire soc_litedramcore_bankmachine1_cmd_buffer_sink_last;
wire soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
reg soc_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
wire soc_litedramcore_bankmachine1_cmd_buffer_source_ready;
reg soc_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
reg soc_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
reg soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0;
reg [13:0] soc_litedramcore_bankmachine1_row = 14'd0;
reg soc_litedramcore_bankmachine1_row_opened = 1'd0;
wire soc_litedramcore_bankmachine1_row_hit;
reg soc_litedramcore_bankmachine1_row_open = 1'd0;
reg soc_litedramcore_bankmachine1_row_close = 1'd0;
reg soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
wire soc_litedramcore_bankmachine1_twtpcon_valid;
reg soc_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
reg [2:0] soc_litedramcore_bankmachine1_twtpcon_count = 3'd0;
wire soc_litedramcore_bankmachine1_trccon_valid;
reg soc_litedramcore_bankmachine1_trccon_ready = 1'd0;
reg [2:0] soc_litedramcore_bankmachine1_trccon_count = 3'd0;
wire soc_litedramcore_bankmachine1_trascon_valid;
reg soc_litedramcore_bankmachine1_trascon_ready = 1'd0;
reg [2:0] soc_litedramcore_bankmachine1_trascon_count = 3'd0;
wire soc_litedramcore_bankmachine2_req_valid;
wire soc_litedramcore_bankmachine2_req_ready;
wire soc_litedramcore_bankmachine2_req_we;
wire [20:0] soc_litedramcore_bankmachine2_req_addr;
wire soc_litedramcore_bankmachine2_req_lock;
reg soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
reg soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
wire soc_litedramcore_bankmachine2_refresh_req;
reg soc_litedramcore_bankmachine2_refresh_gnt = 1'd0;
reg soc_litedramcore_bankmachine2_cmd_valid = 1'd0;
reg soc_litedramcore_bankmachine2_cmd_ready = 1'd0;
reg [13:0] soc_litedramcore_bankmachine2_cmd_payload_a = 14'd0;
wire [2:0] soc_litedramcore_bankmachine2_cmd_payload_ba;
reg soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
reg soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
reg soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
reg soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
reg soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
reg soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
reg soc_litedramcore_bankmachine2_auto_precharge = 1'd0;
wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
reg [4:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
wire [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
wire soc_litedramcore_bankmachine2_cmd_buffer_sink_valid;
wire soc_litedramcore_bankmachine2_cmd_buffer_sink_ready;
wire soc_litedramcore_bankmachine2_cmd_buffer_sink_first;
wire soc_litedramcore_bankmachine2_cmd_buffer_sink_last;
wire soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
reg soc_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
wire soc_litedramcore_bankmachine2_cmd_buffer_source_ready;
reg soc_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
reg soc_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
reg soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0;
reg [13:0] soc_litedramcore_bankmachine2_row = 14'd0;
reg soc_litedramcore_bankmachine2_row_opened = 1'd0;
wire soc_litedramcore_bankmachine2_row_hit;
reg soc_litedramcore_bankmachine2_row_open = 1'd0;
reg soc_litedramcore_bankmachine2_row_close = 1'd0;
reg soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
wire soc_litedramcore_bankmachine2_twtpcon_valid;
reg soc_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
reg [2:0] soc_litedramcore_bankmachine2_twtpcon_count = 3'd0;
wire soc_litedramcore_bankmachine2_trccon_valid;
reg soc_litedramcore_bankmachine2_trccon_ready = 1'd0;
reg [2:0] soc_litedramcore_bankmachine2_trccon_count = 3'd0;
wire soc_litedramcore_bankmachine2_trascon_valid;
reg soc_litedramcore_bankmachine2_trascon_ready = 1'd0;
reg [2:0] soc_litedramcore_bankmachine2_trascon_count = 3'd0;
wire soc_litedramcore_bankmachine3_req_valid;
wire soc_litedramcore_bankmachine3_req_ready;
wire soc_litedramcore_bankmachine3_req_we;
wire [20:0] soc_litedramcore_bankmachine3_req_addr;
wire soc_litedramcore_bankmachine3_req_lock;
reg soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
reg soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
wire soc_litedramcore_bankmachine3_refresh_req;
reg soc_litedramcore_bankmachine3_refresh_gnt = 1'd0;
reg soc_litedramcore_bankmachine3_cmd_valid = 1'd0;
reg soc_litedramcore_bankmachine3_cmd_ready = 1'd0;
reg [13:0] soc_litedramcore_bankmachine3_cmd_payload_a = 14'd0;
wire [2:0] soc_litedramcore_bankmachine3_cmd_payload_ba;
reg soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
reg soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
reg soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
reg soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
reg soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
reg soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
reg soc_litedramcore_bankmachine3_auto_precharge = 1'd0;
wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
reg [4:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
wire [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
wire soc_litedramcore_bankmachine3_cmd_buffer_sink_valid;
wire soc_litedramcore_bankmachine3_cmd_buffer_sink_ready;
wire soc_litedramcore_bankmachine3_cmd_buffer_sink_first;
wire soc_litedramcore_bankmachine3_cmd_buffer_sink_last;
wire soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
reg soc_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
wire soc_litedramcore_bankmachine3_cmd_buffer_source_ready;
reg soc_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
reg soc_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
reg soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0;
reg [13:0] soc_litedramcore_bankmachine3_row = 14'd0;
reg soc_litedramcore_bankmachine3_row_opened = 1'd0;
wire soc_litedramcore_bankmachine3_row_hit;
reg soc_litedramcore_bankmachine3_row_open = 1'd0;
reg soc_litedramcore_bankmachine3_row_close = 1'd0;
reg soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
wire soc_litedramcore_bankmachine3_twtpcon_valid;
reg soc_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
reg [2:0] soc_litedramcore_bankmachine3_twtpcon_count = 3'd0;
wire soc_litedramcore_bankmachine3_trccon_valid;
reg soc_litedramcore_bankmachine3_trccon_ready = 1'd0;
reg [2:0] soc_litedramcore_bankmachine3_trccon_count = 3'd0;
wire soc_litedramcore_bankmachine3_trascon_valid;
reg soc_litedramcore_bankmachine3_trascon_ready = 1'd0;
reg [2:0] soc_litedramcore_bankmachine3_trascon_count = 3'd0;
wire soc_litedramcore_bankmachine4_req_valid;
wire soc_litedramcore_bankmachine4_req_ready;
wire soc_litedramcore_bankmachine4_req_we;
wire [20:0] soc_litedramcore_bankmachine4_req_addr;
wire soc_litedramcore_bankmachine4_req_lock;
reg soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
reg soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
wire soc_litedramcore_bankmachine4_refresh_req;
reg soc_litedramcore_bankmachine4_refresh_gnt = 1'd0;
reg soc_litedramcore_bankmachine4_cmd_valid = 1'd0;
reg soc_litedramcore_bankmachine4_cmd_ready = 1'd0;
reg [13:0] soc_litedramcore_bankmachine4_cmd_payload_a = 14'd0;
wire [2:0] soc_litedramcore_bankmachine4_cmd_payload_ba;
reg soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
reg soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
reg soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
reg soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
reg soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
reg soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
reg soc_litedramcore_bankmachine4_auto_precharge = 1'd0;
wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
reg [4:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
wire [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
wire soc_litedramcore_bankmachine4_cmd_buffer_sink_valid;
wire soc_litedramcore_bankmachine4_cmd_buffer_sink_ready;
wire soc_litedramcore_bankmachine4_cmd_buffer_sink_first;
wire soc_litedramcore_bankmachine4_cmd_buffer_sink_last;
wire soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
reg soc_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
wire soc_litedramcore_bankmachine4_cmd_buffer_source_ready;
reg soc_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
reg soc_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
reg soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0;
reg [13:0] soc_litedramcore_bankmachine4_row = 14'd0;
reg soc_litedramcore_bankmachine4_row_opened = 1'd0;
wire soc_litedramcore_bankmachine4_row_hit;
reg soc_litedramcore_bankmachine4_row_open = 1'd0;
reg soc_litedramcore_bankmachine4_row_close = 1'd0;
reg soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
wire soc_litedramcore_bankmachine4_twtpcon_valid;
reg soc_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
reg [2:0] soc_litedramcore_bankmachine4_twtpcon_count = 3'd0;
wire soc_litedramcore_bankmachine4_trccon_valid;
reg soc_litedramcore_bankmachine4_trccon_ready = 1'd0;
reg [2:0] soc_litedramcore_bankmachine4_trccon_count = 3'd0;
wire soc_litedramcore_bankmachine4_trascon_valid;
reg soc_litedramcore_bankmachine4_trascon_ready = 1'd0;
reg [2:0] soc_litedramcore_bankmachine4_trascon_count = 3'd0;
wire soc_litedramcore_bankmachine5_req_valid;
wire soc_litedramcore_bankmachine5_req_ready;
wire soc_litedramcore_bankmachine5_req_we;
wire [20:0] soc_litedramcore_bankmachine5_req_addr;
wire soc_litedramcore_bankmachine5_req_lock;
reg soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
reg soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
wire soc_litedramcore_bankmachine5_refresh_req;
reg soc_litedramcore_bankmachine5_refresh_gnt = 1'd0;
reg soc_litedramcore_bankmachine5_cmd_valid = 1'd0;
reg soc_litedramcore_bankmachine5_cmd_ready = 1'd0;
reg [13:0] soc_litedramcore_bankmachine5_cmd_payload_a = 14'd0;
wire [2:0] soc_litedramcore_bankmachine5_cmd_payload_ba;
reg soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
reg soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
reg soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
reg soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
reg soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
reg soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
reg soc_litedramcore_bankmachine5_auto_precharge = 1'd0;
wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
reg [4:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
wire [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
wire soc_litedramcore_bankmachine5_cmd_buffer_sink_valid;
wire soc_litedramcore_bankmachine5_cmd_buffer_sink_ready;
wire soc_litedramcore_bankmachine5_cmd_buffer_sink_first;
wire soc_litedramcore_bankmachine5_cmd_buffer_sink_last;
wire soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
reg soc_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
wire soc_litedramcore_bankmachine5_cmd_buffer_source_ready;
reg soc_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
reg soc_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
reg soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0;
reg [13:0] soc_litedramcore_bankmachine5_row = 14'd0;
reg soc_litedramcore_bankmachine5_row_opened = 1'd0;
wire soc_litedramcore_bankmachine5_row_hit;
reg soc_litedramcore_bankmachine5_row_open = 1'd0;
reg soc_litedramcore_bankmachine5_row_close = 1'd0;
reg soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
wire soc_litedramcore_bankmachine5_twtpcon_valid;
reg soc_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
reg [2:0] soc_litedramcore_bankmachine5_twtpcon_count = 3'd0;
wire soc_litedramcore_bankmachine5_trccon_valid;
reg soc_litedramcore_bankmachine5_trccon_ready = 1'd0;
reg [2:0] soc_litedramcore_bankmachine5_trccon_count = 3'd0;
wire soc_litedramcore_bankmachine5_trascon_valid;
reg soc_litedramcore_bankmachine5_trascon_ready = 1'd0;
reg [2:0] soc_litedramcore_bankmachine5_trascon_count = 3'd0;
wire soc_litedramcore_bankmachine6_req_valid;
wire soc_litedramcore_bankmachine6_req_ready;
wire soc_litedramcore_bankmachine6_req_we;
wire [20:0] soc_litedramcore_bankmachine6_req_addr;
wire soc_litedramcore_bankmachine6_req_lock;
reg soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
reg soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
wire soc_litedramcore_bankmachine6_refresh_req;
reg soc_litedramcore_bankmachine6_refresh_gnt = 1'd0;
reg soc_litedramcore_bankmachine6_cmd_valid = 1'd0;
reg soc_litedramcore_bankmachine6_cmd_ready = 1'd0;
reg [13:0] soc_litedramcore_bankmachine6_cmd_payload_a = 14'd0;
wire [2:0] soc_litedramcore_bankmachine6_cmd_payload_ba;
reg soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
reg soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
reg soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
reg soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
reg soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
reg soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
reg soc_litedramcore_bankmachine6_auto_precharge = 1'd0;
wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
reg [4:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
wire [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
wire soc_litedramcore_bankmachine6_cmd_buffer_sink_valid;
wire soc_litedramcore_bankmachine6_cmd_buffer_sink_ready;
wire soc_litedramcore_bankmachine6_cmd_buffer_sink_first;
wire soc_litedramcore_bankmachine6_cmd_buffer_sink_last;
wire soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
reg soc_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
wire soc_litedramcore_bankmachine6_cmd_buffer_source_ready;
reg soc_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
reg soc_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
reg soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0;
reg [13:0] soc_litedramcore_bankmachine6_row = 14'd0;
reg soc_litedramcore_bankmachine6_row_opened = 1'd0;
wire soc_litedramcore_bankmachine6_row_hit;
reg soc_litedramcore_bankmachine6_row_open = 1'd0;
reg soc_litedramcore_bankmachine6_row_close = 1'd0;
reg soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
wire soc_litedramcore_bankmachine6_twtpcon_valid;
reg soc_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
reg [2:0] soc_litedramcore_bankmachine6_twtpcon_count = 3'd0;
wire soc_litedramcore_bankmachine6_trccon_valid;
reg soc_litedramcore_bankmachine6_trccon_ready = 1'd0;
reg [2:0] soc_litedramcore_bankmachine6_trccon_count = 3'd0;
wire soc_litedramcore_bankmachine6_trascon_valid;
reg soc_litedramcore_bankmachine6_trascon_ready = 1'd0;
reg [2:0] soc_litedramcore_bankmachine6_trascon_count = 3'd0;
wire soc_litedramcore_bankmachine7_req_valid;
wire soc_litedramcore_bankmachine7_req_ready;
wire soc_litedramcore_bankmachine7_req_we;
wire [20:0] soc_litedramcore_bankmachine7_req_addr;
wire soc_litedramcore_bankmachine7_req_lock;
reg soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
reg soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
wire soc_litedramcore_bankmachine7_refresh_req;
reg soc_litedramcore_bankmachine7_refresh_gnt = 1'd0;
reg soc_litedramcore_bankmachine7_cmd_valid = 1'd0;
reg soc_litedramcore_bankmachine7_cmd_ready = 1'd0;
reg [13:0] soc_litedramcore_bankmachine7_cmd_payload_a = 14'd0;
wire [2:0] soc_litedramcore_bankmachine7_cmd_payload_ba;
reg soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
reg soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
reg soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
reg soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
reg soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
reg soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
reg soc_litedramcore_bankmachine7_auto_precharge = 1'd0;
wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
reg [4:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
wire [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
wire soc_litedramcore_bankmachine7_cmd_buffer_sink_valid;
wire soc_litedramcore_bankmachine7_cmd_buffer_sink_ready;
wire soc_litedramcore_bankmachine7_cmd_buffer_sink_first;
wire soc_litedramcore_bankmachine7_cmd_buffer_sink_last;
wire soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
reg soc_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
wire soc_litedramcore_bankmachine7_cmd_buffer_source_ready;
reg soc_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
reg soc_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
reg soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0;
reg [13:0] soc_litedramcore_bankmachine7_row = 14'd0;
reg soc_litedramcore_bankmachine7_row_opened = 1'd0;
wire soc_litedramcore_bankmachine7_row_hit;
reg soc_litedramcore_bankmachine7_row_open = 1'd0;
reg soc_litedramcore_bankmachine7_row_close = 1'd0;
reg soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
wire soc_litedramcore_bankmachine7_twtpcon_valid;
reg soc_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
reg [2:0] soc_litedramcore_bankmachine7_twtpcon_count = 3'd0;
wire soc_litedramcore_bankmachine7_trccon_valid;
reg soc_litedramcore_bankmachine7_trccon_ready = 1'd0;
reg [2:0] soc_litedramcore_bankmachine7_trccon_count = 3'd0;
wire soc_litedramcore_bankmachine7_trascon_valid;
reg soc_litedramcore_bankmachine7_trascon_ready = 1'd0;
reg [2:0] soc_litedramcore_bankmachine7_trascon_count = 3'd0;
wire soc_litedramcore_ras_allowed;
wire soc_litedramcore_cas_allowed;
reg soc_litedramcore_choose_cmd_want_reads = 1'd0;
reg soc_litedramcore_choose_cmd_want_writes = 1'd0;
reg soc_litedramcore_choose_cmd_want_cmds = 1'd0;
reg soc_litedramcore_choose_cmd_want_activates = 1'd0;
wire soc_litedramcore_choose_cmd_cmd_valid;
reg soc_litedramcore_choose_cmd_cmd_ready = 1'd0;
wire [13:0] soc_litedramcore_choose_cmd_cmd_payload_a;
wire [2:0] soc_litedramcore_choose_cmd_cmd_payload_ba;
reg soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
reg soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
reg soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
wire soc_litedramcore_choose_cmd_cmd_payload_is_cmd;
wire soc_litedramcore_choose_cmd_cmd_payload_is_read;
wire soc_litedramcore_choose_cmd_cmd_payload_is_write;
reg [7:0] soc_litedramcore_choose_cmd_valids = 8'd0;
wire [7:0] soc_litedramcore_choose_cmd_request;
reg [2:0] soc_litedramcore_choose_cmd_grant = 3'd0;
wire soc_litedramcore_choose_cmd_ce;
reg soc_litedramcore_choose_req_want_reads = 1'd0;
reg soc_litedramcore_choose_req_want_writes = 1'd0;
reg soc_litedramcore_choose_req_want_cmds = 1'd0;
reg soc_litedramcore_choose_req_want_activates = 1'd0;
wire soc_litedramcore_choose_req_cmd_valid;
reg soc_litedramcore_choose_req_cmd_ready = 1'd0;
wire [13:0] soc_litedramcore_choose_req_cmd_payload_a;
wire [2:0] soc_litedramcore_choose_req_cmd_payload_ba;
reg soc_litedramcore_choose_req_cmd_payload_cas = 1'd0;
reg soc_litedramcore_choose_req_cmd_payload_ras = 1'd0;
reg soc_litedramcore_choose_req_cmd_payload_we = 1'd0;
wire soc_litedramcore_choose_req_cmd_payload_is_cmd;
wire soc_litedramcore_choose_req_cmd_payload_is_read;
wire soc_litedramcore_choose_req_cmd_payload_is_write;
reg [7:0] soc_litedramcore_choose_req_valids = 8'd0;
wire [7:0] soc_litedramcore_choose_req_request;
reg [2:0] soc_litedramcore_choose_req_grant = 3'd0;
wire soc_litedramcore_choose_req_ce;
reg [13:0] soc_litedramcore_nop_a = 14'd0;
reg [2:0] soc_litedramcore_nop_ba = 3'd0;
reg [1:0] soc_litedramcore_steerer_sel0 = 2'd0;
reg [1:0] soc_litedramcore_steerer_sel1 = 2'd0;
reg [1:0] soc_litedramcore_steerer_sel2 = 2'd0;
reg [1:0] soc_litedramcore_steerer_sel3 = 2'd0;
reg soc_litedramcore_steerer0 = 1'd1;
reg soc_litedramcore_steerer1 = 1'd1;
reg soc_litedramcore_steerer2 = 1'd1;
reg soc_litedramcore_steerer3 = 1'd1;
reg soc_litedramcore_steerer4 = 1'd1;
reg soc_litedramcore_steerer5 = 1'd1;
reg soc_litedramcore_steerer6 = 1'd1;
reg soc_litedramcore_steerer7 = 1'd1;
wire soc_litedramcore_trrdcon_valid;
reg soc_litedramcore_trrdcon_ready = 1'd0;
reg soc_litedramcore_trrdcon_count = 1'd0;
wire soc_litedramcore_tfawcon_valid;
reg soc_litedramcore_tfawcon_ready = 1'd1;
wire [2:0] soc_litedramcore_tfawcon_count;
reg [4:0] soc_litedramcore_tfawcon_window = 5'd0;
wire soc_litedramcore_tccdcon_valid;
reg soc_litedramcore_tccdcon_ready = 1'd0;
reg soc_litedramcore_tccdcon_count = 1'd0;
wire soc_litedramcore_twtrcon_valid;
reg soc_litedramcore_twtrcon_ready = 1'd0;
reg [2:0] soc_litedramcore_twtrcon_count = 3'd0;
wire soc_litedramcore_read_available;
wire soc_litedramcore_write_available;
reg soc_litedramcore_en0 = 1'd0;
wire soc_litedramcore_max_time0;
reg [4:0] soc_litedramcore_time0 = 5'd0;
reg soc_litedramcore_en1 = 1'd0;
wire soc_litedramcore_max_time1;
reg [3:0] soc_litedramcore_time1 = 4'd0;
wire soc_litedramcore_go_to_refresh;
reg soc_init_done_storage = 1'd0;
reg soc_init_done_re = 1'd0;
reg soc_init_error_storage = 1'd0;
reg soc_init_error_re = 1'd0;
wire [29:0] soc_wb_bus_adr;
wire [31:0] soc_wb_bus_dat_w;
wire [31:0] soc_wb_bus_dat_r;
wire [3:0] soc_wb_bus_sel;
wire soc_wb_bus_cyc;
wire soc_wb_bus_stb;
wire soc_wb_bus_ack;
wire soc_wb_bus_we;
wire [2:0] soc_wb_bus_cti;
wire [1:0] soc_wb_bus_bte;
wire soc_wb_bus_err;
wire soc_user_port_cmd_valid;
wire soc_user_port_cmd_ready;
wire soc_user_port_cmd_payload_we;
wire [23:0] soc_user_port_cmd_payload_addr;
wire soc_user_port_wdata_valid;
wire soc_user_port_wdata_ready;
wire [127:0] soc_user_port_wdata_payload_data;
wire [15:0] soc_user_port_wdata_payload_we;
wire soc_user_port_rdata_valid;
wire soc_user_port_rdata_ready;
wire [127:0] soc_user_port_rdata_payload_data;
reg [1:0] refresher_state = 2'd0;
reg [1:0] refresher_next_state = 2'd0;
reg [3:0] bankmachine0_state = 4'd0;
reg [3:0] bankmachine0_next_state = 4'd0;
reg [3:0] bankmachine1_state = 4'd0;
reg [3:0] bankmachine1_next_state = 4'd0;
reg [3:0] bankmachine2_state = 4'd0;
reg [3:0] bankmachine2_next_state = 4'd0;
reg [3:0] bankmachine3_state = 4'd0;
reg [3:0] bankmachine3_next_state = 4'd0;
reg [3:0] bankmachine4_state = 4'd0;
reg [3:0] bankmachine4_next_state = 4'd0;
reg [3:0] bankmachine5_state = 4'd0;
reg [3:0] bankmachine5_next_state = 4'd0;
reg [3:0] bankmachine6_state = 4'd0;
reg [3:0] bankmachine6_next_state = 4'd0;
reg [3:0] bankmachine7_state = 4'd0;
reg [3:0] bankmachine7_next_state = 4'd0;
reg [3:0] multiplexer_state = 4'd0;
reg [3:0] multiplexer_next_state = 4'd0;
wire roundrobin0_request;
wire roundrobin0_grant;
wire roundrobin0_ce;
wire roundrobin1_request;
wire roundrobin1_grant;
wire roundrobin1_ce;
wire roundrobin2_request;
wire roundrobin2_grant;
wire roundrobin2_ce;
wire roundrobin3_request;
wire roundrobin3_grant;
wire roundrobin3_ce;
wire roundrobin4_request;
wire roundrobin4_grant;
wire roundrobin4_ce;
wire roundrobin5_request;
wire roundrobin5_grant;
wire roundrobin5_ce;
wire roundrobin6_request;
wire roundrobin6_grant;
wire roundrobin6_ce;
wire roundrobin7_request;
wire roundrobin7_grant;
wire roundrobin7_ce;
reg locked0 = 1'd0;
reg locked1 = 1'd0;
reg locked2 = 1'd0;
reg locked3 = 1'd0;
reg locked4 = 1'd0;
reg locked5 = 1'd0;
reg locked6 = 1'd0;
reg locked7 = 1'd0;
reg new_master_wdata_ready0 = 1'd0;
reg new_master_wdata_ready1 = 1'd0;
reg new_master_rdata_valid0 = 1'd0;
reg new_master_rdata_valid1 = 1'd0;
reg new_master_rdata_valid2 = 1'd0;
reg new_master_rdata_valid3 = 1'd0;
reg new_master_rdata_valid4 = 1'd0;
reg new_master_rdata_valid5 = 1'd0;
reg new_master_rdata_valid6 = 1'd0;
reg new_master_rdata_valid7 = 1'd0;
reg new_master_rdata_valid8 = 1'd0;
reg [13:0] litedramcore_adr = 14'd0;
reg litedramcore_we = 1'd0;
reg [7:0] litedramcore_dat_w = 8'd0;
wire [7:0] litedramcore_dat_r;
wire [29:0] litedramcore_wishbone_adr;
wire [31:0] litedramcore_wishbone_dat_w;
reg [31:0] litedramcore_wishbone_dat_r = 32'd0;
wire [3:0] litedramcore_wishbone_sel;
wire litedramcore_wishbone_cyc;
wire litedramcore_wishbone_stb;
reg litedramcore_wishbone_ack = 1'd0;
wire litedramcore_wishbone_we;
wire [2:0] litedramcore_wishbone_cti;
wire [1:0] litedramcore_wishbone_bte;
reg litedramcore_wishbone_err = 1'd0;
wire [13:0] interface0_bank_bus_adr;
wire interface0_bank_bus_we;
wire [7:0] interface0_bank_bus_dat_w;
reg [7:0] interface0_bank_bus_dat_r = 8'd0;
reg csrbank0_init_done0_re = 1'd0;
wire csrbank0_init_done0_r;
reg csrbank0_init_done0_we = 1'd0;
wire csrbank0_init_done0_w;
reg csrbank0_init_error0_re = 1'd0;
wire csrbank0_init_error0_r;
reg csrbank0_init_error0_we = 1'd0;
wire csrbank0_init_error0_w;
wire csrbank0_sel;
wire [13:0] interface1_bank_bus_adr;
wire interface1_bank_bus_we;
wire [7:0] interface1_bank_bus_dat_w;
reg [7:0] interface1_bank_bus_dat_r = 8'd0;
reg csrbank1_dfii_control0_re = 1'd0;
wire [3:0] csrbank1_dfii_control0_r;
reg csrbank1_dfii_control0_we = 1'd0;
wire [3:0] csrbank1_dfii_control0_w;
reg csrbank1_dfii_pi0_command0_re = 1'd0;
wire [5:0] csrbank1_dfii_pi0_command0_r;
reg csrbank1_dfii_pi0_command0_we = 1'd0;
wire [5:0] csrbank1_dfii_pi0_command0_w;
reg csrbank1_dfii_pi0_address1_re = 1'd0;
wire [5:0] csrbank1_dfii_pi0_address1_r;
reg csrbank1_dfii_pi0_address1_we = 1'd0;
wire [5:0] csrbank1_dfii_pi0_address1_w;
reg csrbank1_dfii_pi0_address0_re = 1'd0;
wire [7:0] csrbank1_dfii_pi0_address0_r;
reg csrbank1_dfii_pi0_address0_we = 1'd0;
wire [7:0] csrbank1_dfii_pi0_address0_w;
reg csrbank1_dfii_pi0_baddress0_re = 1'd0;
wire [2:0] csrbank1_dfii_pi0_baddress0_r;
reg csrbank1_dfii_pi0_baddress0_we = 1'd0;
wire [2:0] csrbank1_dfii_pi0_baddress0_w;
reg csrbank1_dfii_pi0_wrdata3_re = 1'd0;
wire [7:0] csrbank1_dfii_pi0_wrdata3_r;
reg csrbank1_dfii_pi0_wrdata3_we = 1'd0;
wire [7:0] csrbank1_dfii_pi0_wrdata3_w;
reg csrbank1_dfii_pi0_wrdata2_re = 1'd0;
wire [7:0] csrbank1_dfii_pi0_wrdata2_r;
reg csrbank1_dfii_pi0_wrdata2_we = 1'd0;
wire [7:0] csrbank1_dfii_pi0_wrdata2_w;
reg csrbank1_dfii_pi0_wrdata1_re = 1'd0;
wire [7:0] csrbank1_dfii_pi0_wrdata1_r;
reg csrbank1_dfii_pi0_wrdata1_we = 1'd0;
wire [7:0] csrbank1_dfii_pi0_wrdata1_w;
reg csrbank1_dfii_pi0_wrdata0_re = 1'd0;
wire [7:0] csrbank1_dfii_pi0_wrdata0_r;
reg csrbank1_dfii_pi0_wrdata0_we = 1'd0;
wire [7:0] csrbank1_dfii_pi0_wrdata0_w;
reg csrbank1_dfii_pi0_rddata3_re = 1'd0;
wire [7:0] csrbank1_dfii_pi0_rddata3_r;
reg csrbank1_dfii_pi0_rddata3_we = 1'd0;
wire [7:0] csrbank1_dfii_pi0_rddata3_w;
reg csrbank1_dfii_pi0_rddata2_re = 1'd0;
wire [7:0] csrbank1_dfii_pi0_rddata2_r;
reg csrbank1_dfii_pi0_rddata2_we = 1'd0;
wire [7:0] csrbank1_dfii_pi0_rddata2_w;
reg csrbank1_dfii_pi0_rddata1_re = 1'd0;
wire [7:0] csrbank1_dfii_pi0_rddata1_r;
reg csrbank1_dfii_pi0_rddata1_we = 1'd0;
wire [7:0] csrbank1_dfii_pi0_rddata1_w;
reg csrbank1_dfii_pi0_rddata0_re = 1'd0;
wire [7:0] csrbank1_dfii_pi0_rddata0_r;
reg csrbank1_dfii_pi0_rddata0_we = 1'd0;
wire [7:0] csrbank1_dfii_pi0_rddata0_w;
reg csrbank1_dfii_pi1_command0_re = 1'd0;
wire [5:0] csrbank1_dfii_pi1_command0_r;
reg csrbank1_dfii_pi1_command0_we = 1'd0;
wire [5:0] csrbank1_dfii_pi1_command0_w;
reg csrbank1_dfii_pi1_address1_re = 1'd0;
wire [5:0] csrbank1_dfii_pi1_address1_r;
reg csrbank1_dfii_pi1_address1_we = 1'd0;
wire [5:0] csrbank1_dfii_pi1_address1_w;
reg csrbank1_dfii_pi1_address0_re = 1'd0;
wire [7:0] csrbank1_dfii_pi1_address0_r;
reg csrbank1_dfii_pi1_address0_we = 1'd0;
wire [7:0] csrbank1_dfii_pi1_address0_w;
reg csrbank1_dfii_pi1_baddress0_re = 1'd0;
wire [2:0] csrbank1_dfii_pi1_baddress0_r;
reg csrbank1_dfii_pi1_baddress0_we = 1'd0;
wire [2:0] csrbank1_dfii_pi1_baddress0_w;
reg csrbank1_dfii_pi1_wrdata3_re = 1'd0;
wire [7:0] csrbank1_dfii_pi1_wrdata3_r;
reg csrbank1_dfii_pi1_wrdata3_we = 1'd0;
wire [7:0] csrbank1_dfii_pi1_wrdata3_w;
reg csrbank1_dfii_pi1_wrdata2_re = 1'd0;
wire [7:0] csrbank1_dfii_pi1_wrdata2_r;
reg csrbank1_dfii_pi1_wrdata2_we = 1'd0;
wire [7:0] csrbank1_dfii_pi1_wrdata2_w;
reg csrbank1_dfii_pi1_wrdata1_re = 1'd0;
wire [7:0] csrbank1_dfii_pi1_wrdata1_r;
reg csrbank1_dfii_pi1_wrdata1_we = 1'd0;
wire [7:0] csrbank1_dfii_pi1_wrdata1_w;
reg csrbank1_dfii_pi1_wrdata0_re = 1'd0;
wire [7:0] csrbank1_dfii_pi1_wrdata0_r;
reg csrbank1_dfii_pi1_wrdata0_we = 1'd0;
wire [7:0] csrbank1_dfii_pi1_wrdata0_w;
reg csrbank1_dfii_pi1_rddata3_re = 1'd0;
wire [7:0] csrbank1_dfii_pi1_rddata3_r;
reg csrbank1_dfii_pi1_rddata3_we = 1'd0;
wire [7:0] csrbank1_dfii_pi1_rddata3_w;
reg csrbank1_dfii_pi1_rddata2_re = 1'd0;
wire [7:0] csrbank1_dfii_pi1_rddata2_r;
reg csrbank1_dfii_pi1_rddata2_we = 1'd0;
wire [7:0] csrbank1_dfii_pi1_rddata2_w;
reg csrbank1_dfii_pi1_rddata1_re = 1'd0;
wire [7:0] csrbank1_dfii_pi1_rddata1_r;
reg csrbank1_dfii_pi1_rddata1_we = 1'd0;
wire [7:0] csrbank1_dfii_pi1_rddata1_w;
reg csrbank1_dfii_pi1_rddata0_re = 1'd0;
wire [7:0] csrbank1_dfii_pi1_rddata0_r;
reg csrbank1_dfii_pi1_rddata0_we = 1'd0;
wire [7:0] csrbank1_dfii_pi1_rddata0_w;
reg csrbank1_dfii_pi2_command0_re = 1'd0;
wire [5:0] csrbank1_dfii_pi2_command0_r;
reg csrbank1_dfii_pi2_command0_we = 1'd0;
wire [5:0] csrbank1_dfii_pi2_command0_w;
reg csrbank1_dfii_pi2_address1_re = 1'd0;
wire [5:0] csrbank1_dfii_pi2_address1_r;
reg csrbank1_dfii_pi2_address1_we = 1'd0;
wire [5:0] csrbank1_dfii_pi2_address1_w;
reg csrbank1_dfii_pi2_address0_re = 1'd0;
wire [7:0] csrbank1_dfii_pi2_address0_r;
reg csrbank1_dfii_pi2_address0_we = 1'd0;
wire [7:0] csrbank1_dfii_pi2_address0_w;
reg csrbank1_dfii_pi2_baddress0_re = 1'd0;
wire [2:0] csrbank1_dfii_pi2_baddress0_r;
reg csrbank1_dfii_pi2_baddress0_we = 1'd0;
wire [2:0] csrbank1_dfii_pi2_baddress0_w;
reg csrbank1_dfii_pi2_wrdata3_re = 1'd0;
wire [7:0] csrbank1_dfii_pi2_wrdata3_r;
reg csrbank1_dfii_pi2_wrdata3_we = 1'd0;
wire [7:0] csrbank1_dfii_pi2_wrdata3_w;
reg csrbank1_dfii_pi2_wrdata2_re = 1'd0;
wire [7:0] csrbank1_dfii_pi2_wrdata2_r;
reg csrbank1_dfii_pi2_wrdata2_we = 1'd0;
wire [7:0] csrbank1_dfii_pi2_wrdata2_w;
reg csrbank1_dfii_pi2_wrdata1_re = 1'd0;
wire [7:0] csrbank1_dfii_pi2_wrdata1_r;
reg csrbank1_dfii_pi2_wrdata1_we = 1'd0;
wire [7:0] csrbank1_dfii_pi2_wrdata1_w;
reg csrbank1_dfii_pi2_wrdata0_re = 1'd0;
wire [7:0] csrbank1_dfii_pi2_wrdata0_r;
reg csrbank1_dfii_pi2_wrdata0_we = 1'd0;
wire [7:0] csrbank1_dfii_pi2_wrdata0_w;
reg csrbank1_dfii_pi2_rddata3_re = 1'd0;
wire [7:0] csrbank1_dfii_pi2_rddata3_r;
reg csrbank1_dfii_pi2_rddata3_we = 1'd0;
wire [7:0] csrbank1_dfii_pi2_rddata3_w;
reg csrbank1_dfii_pi2_rddata2_re = 1'd0;
wire [7:0] csrbank1_dfii_pi2_rddata2_r;
reg csrbank1_dfii_pi2_rddata2_we = 1'd0;
wire [7:0] csrbank1_dfii_pi2_rddata2_w;
reg csrbank1_dfii_pi2_rddata1_re = 1'd0;
wire [7:0] csrbank1_dfii_pi2_rddata1_r;
reg csrbank1_dfii_pi2_rddata1_we = 1'd0;
wire [7:0] csrbank1_dfii_pi2_rddata1_w;
reg csrbank1_dfii_pi2_rddata0_re = 1'd0;
wire [7:0] csrbank1_dfii_pi2_rddata0_r;
reg csrbank1_dfii_pi2_rddata0_we = 1'd0;
wire [7:0] csrbank1_dfii_pi2_rddata0_w;
reg csrbank1_dfii_pi3_command0_re = 1'd0;
wire [5:0] csrbank1_dfii_pi3_command0_r;
reg csrbank1_dfii_pi3_command0_we = 1'd0;
wire [5:0] csrbank1_dfii_pi3_command0_w;
reg csrbank1_dfii_pi3_address1_re = 1'd0;
wire [5:0] csrbank1_dfii_pi3_address1_r;
reg csrbank1_dfii_pi3_address1_we = 1'd0;
wire [5:0] csrbank1_dfii_pi3_address1_w;
reg csrbank1_dfii_pi3_address0_re = 1'd0;
wire [7:0] csrbank1_dfii_pi3_address0_r;
reg csrbank1_dfii_pi3_address0_we = 1'd0;
wire [7:0] csrbank1_dfii_pi3_address0_w;
reg csrbank1_dfii_pi3_baddress0_re = 1'd0;
wire [2:0] csrbank1_dfii_pi3_baddress0_r;
reg csrbank1_dfii_pi3_baddress0_we = 1'd0;
wire [2:0] csrbank1_dfii_pi3_baddress0_w;
reg csrbank1_dfii_pi3_wrdata3_re = 1'd0;
wire [7:0] csrbank1_dfii_pi3_wrdata3_r;
reg csrbank1_dfii_pi3_wrdata3_we = 1'd0;
wire [7:0] csrbank1_dfii_pi3_wrdata3_w;
reg csrbank1_dfii_pi3_wrdata2_re = 1'd0;
wire [7:0] csrbank1_dfii_pi3_wrdata2_r;
reg csrbank1_dfii_pi3_wrdata2_we = 1'd0;
wire [7:0] csrbank1_dfii_pi3_wrdata2_w;
reg csrbank1_dfii_pi3_wrdata1_re = 1'd0;
wire [7:0] csrbank1_dfii_pi3_wrdata1_r;
reg csrbank1_dfii_pi3_wrdata1_we = 1'd0;
wire [7:0] csrbank1_dfii_pi3_wrdata1_w;
reg csrbank1_dfii_pi3_wrdata0_re = 1'd0;
wire [7:0] csrbank1_dfii_pi3_wrdata0_r;
reg csrbank1_dfii_pi3_wrdata0_we = 1'd0;
wire [7:0] csrbank1_dfii_pi3_wrdata0_w;
reg csrbank1_dfii_pi3_rddata3_re = 1'd0;
wire [7:0] csrbank1_dfii_pi3_rddata3_r;
reg csrbank1_dfii_pi3_rddata3_we = 1'd0;
wire [7:0] csrbank1_dfii_pi3_rddata3_w;
reg csrbank1_dfii_pi3_rddata2_re = 1'd0;
wire [7:0] csrbank1_dfii_pi3_rddata2_r;
reg csrbank1_dfii_pi3_rddata2_we = 1'd0;
wire [7:0] csrbank1_dfii_pi3_rddata2_w;
reg csrbank1_dfii_pi3_rddata1_re = 1'd0;
wire [7:0] csrbank1_dfii_pi3_rddata1_r;
reg csrbank1_dfii_pi3_rddata1_we = 1'd0;
wire [7:0] csrbank1_dfii_pi3_rddata1_w;
reg csrbank1_dfii_pi3_rddata0_re = 1'd0;
wire [7:0] csrbank1_dfii_pi3_rddata0_r;
reg csrbank1_dfii_pi3_rddata0_we = 1'd0;
wire [7:0] csrbank1_dfii_pi3_rddata0_w;
wire csrbank1_sel;
wire [13:0] csr_interconnect_adr;
wire csr_interconnect_we;
wire [7:0] csr_interconnect_dat_w;
wire [7:0] csr_interconnect_dat_r;
reg [1:0] state = 2'd0;
reg [1:0] next_state = 2'd0;
reg [7:0] litedramcore_dat_w_next_value0 = 8'd0;
reg litedramcore_dat_w_next_value_ce0 = 1'd0;
reg [13:0] litedramcore_adr_next_value1 = 14'd0;
reg litedramcore_adr_next_value_ce1 = 1'd0;
reg litedramcore_we_next_value2 = 1'd0;
reg litedramcore_we_next_value_ce2 = 1'd0;
wire [24:0] slice_proxy0;
wire [24:0] slice_proxy1;
wire [24:0] slice_proxy2;
wire [24:0] slice_proxy3;
wire [24:0] slice_proxy4;
wire [24:0] slice_proxy5;
wire [24:0] slice_proxy6;
wire [24:0] slice_proxy7;
wire [24:0] slice_proxy8;
wire [24:0] slice_proxy9;
wire [24:0] slice_proxy10;
wire [24:0] slice_proxy11;
wire [24:0] slice_proxy12;
wire [24:0] slice_proxy13;
wire [24:0] slice_proxy14;
wire [24:0] slice_proxy15;
reg rhs_array_muxed0 = 1'd0;
reg [13:0] rhs_array_muxed1 = 14'd0;
reg [2:0] rhs_array_muxed2 = 3'd0;
reg rhs_array_muxed3 = 1'd0;
reg rhs_array_muxed4 = 1'd0;
reg rhs_array_muxed5 = 1'd0;
reg t_array_muxed0 = 1'd0;
reg t_array_muxed1 = 1'd0;
reg t_array_muxed2 = 1'd0;
reg rhs_array_muxed6 = 1'd0;
reg [13:0] rhs_array_muxed7 = 14'd0;
reg [2:0] rhs_array_muxed8 = 3'd0;
reg rhs_array_muxed9 = 1'd0;
reg rhs_array_muxed10 = 1'd0;
reg rhs_array_muxed11 = 1'd0;
reg t_array_muxed3 = 1'd0;
reg t_array_muxed4 = 1'd0;
reg t_array_muxed5 = 1'd0;
reg [20:0] rhs_array_muxed12 = 21'd0;
reg rhs_array_muxed13 = 1'd0;
reg rhs_array_muxed14 = 1'd0;
reg [20:0] rhs_array_muxed15 = 21'd0;
reg rhs_array_muxed16 = 1'd0;
reg rhs_array_muxed17 = 1'd0;
reg [20:0] rhs_array_muxed18 = 21'd0;
reg rhs_array_muxed19 = 1'd0;
reg rhs_array_muxed20 = 1'd0;
reg [20:0] rhs_array_muxed21 = 21'd0;
reg rhs_array_muxed22 = 1'd0;
reg rhs_array_muxed23 = 1'd0;
reg [20:0] rhs_array_muxed24 = 21'd0;
reg rhs_array_muxed25 = 1'd0;
reg rhs_array_muxed26 = 1'd0;
reg [20:0] rhs_array_muxed27 = 21'd0;
reg rhs_array_muxed28 = 1'd0;
reg rhs_array_muxed29 = 1'd0;
reg [20:0] rhs_array_muxed30 = 21'd0;
reg rhs_array_muxed31 = 1'd0;
reg rhs_array_muxed32 = 1'd0;
reg [20:0] rhs_array_muxed33 = 21'd0;
reg rhs_array_muxed34 = 1'd0;
reg rhs_array_muxed35 = 1'd0;
reg [2:0] array_muxed0 = 3'd0;
reg [13:0] array_muxed1 = 14'd0;
reg array_muxed2 = 1'd0;
reg array_muxed3 = 1'd0;
reg array_muxed4 = 1'd0;
reg array_muxed5 = 1'd0;
reg array_muxed6 = 1'd0;
reg [2:0] array_muxed7 = 3'd0;
reg [13:0] array_muxed8 = 14'd0;
reg array_muxed9 = 1'd0;
reg array_muxed10 = 1'd0;
reg array_muxed11 = 1'd0;
reg array_muxed12 = 1'd0;
reg array_muxed13 = 1'd0;
reg [2:0] array_muxed14 = 3'd0;
reg [13:0] array_muxed15 = 14'd0;
reg array_muxed16 = 1'd0;
reg array_muxed17 = 1'd0;
reg array_muxed18 = 1'd0;
reg array_muxed19 = 1'd0;
reg array_muxed20 = 1'd0;
reg [2:0] array_muxed21 = 3'd0;
reg [13:0] array_muxed22 = 14'd0;
reg array_muxed23 = 1'd0;
reg array_muxed24 = 1'd0;
reg array_muxed25 = 1'd0;
reg array_muxed26 = 1'd0;
reg array_muxed27 = 1'd0;
assign init_done = soc_init_done_storage;
assign init_error = soc_init_error_storage;
assign soc_wb_bus_adr = wb_ctrl_adr;
assign soc_wb_bus_dat_w = wb_ctrl_dat_w;
assign wb_ctrl_dat_r = soc_wb_bus_dat_r;
assign soc_wb_bus_sel = wb_ctrl_sel;
assign soc_wb_bus_cyc = wb_ctrl_cyc;
assign soc_wb_bus_stb = wb_ctrl_stb;
assign wb_ctrl_ack = soc_wb_bus_ack;
assign soc_wb_bus_we = wb_ctrl_we;
assign soc_wb_bus_cti = wb_ctrl_cti;
assign soc_wb_bus_bte = wb_ctrl_bte;
assign wb_ctrl_err = soc_wb_bus_err;
assign user_clk = sys_clk;
assign user_rst = sys_rst;
assign soc_user_port_cmd_valid = user_port_native_0_cmd_valid;
assign user_port_native_0_cmd_ready = soc_user_port_cmd_ready;
assign soc_user_port_cmd_payload_we = user_port_native_0_cmd_we;
assign soc_user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
assign soc_user_port_wdata_valid = user_port_native_0_wdata_valid;
assign user_port_native_0_wdata_ready = soc_user_port_wdata_ready;
assign soc_user_port_wdata_payload_we = user_port_native_0_wdata_we;
assign soc_user_port_wdata_payload_data = user_port_native_0_wdata_data;
assign user_port_native_0_rdata_valid = soc_user_port_rdata_valid;
assign soc_user_port_rdata_ready = user_port_native_0_rdata_ready;
assign user_port_native_0_rdata_data = soc_user_port_rdata_payload_data;
assign sys_clk = clk;
assign por_clk = clk;
assign sys_rst = soc_int_rst;
always @(*) begin
soc_ddrphy_activates0 = 4'd0;
soc_ddrphy_activates0[0] = soc_ddrphy_dfiphasemodel0_activate;
soc_ddrphy_activates0[1] = soc_ddrphy_dfiphasemodel1_activate;
soc_ddrphy_activates0[2] = soc_ddrphy_dfiphasemodel2_activate;
soc_ddrphy_activates0[3] = soc_ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
soc_ddrphy_bankmodel0_activate = 1'd0;
case (soc_ddrphy_activates0)
1'd1: begin
soc_ddrphy_bankmodel0_activate = (soc_ddrphy_dfi_p0_bank == 1'd0);
end
2'd2: begin
soc_ddrphy_bankmodel0_activate = (soc_ddrphy_dfi_p1_bank == 1'd0);
end
3'd4: begin
soc_ddrphy_bankmodel0_activate = (soc_ddrphy_dfi_p2_bank == 1'd0);
end
4'd8: begin
soc_ddrphy_bankmodel0_activate = (soc_ddrphy_dfi_p3_bank == 1'd0);
end
endcase
end
always @(*) begin
soc_ddrphy_bankmodel0_activate_row = 14'd0;
case (soc_ddrphy_activates0)
1'd1: begin
soc_ddrphy_bankmodel0_activate_row = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bankmodel0_activate_row = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bankmodel0_activate_row = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bankmodel0_activate_row = soc_ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
soc_ddrphy_precharges0 = 4'd0;
soc_ddrphy_precharges0[0] = soc_ddrphy_dfiphasemodel0_precharge;
soc_ddrphy_precharges0[1] = soc_ddrphy_dfiphasemodel1_precharge;
soc_ddrphy_precharges0[2] = soc_ddrphy_dfiphasemodel2_precharge;
soc_ddrphy_precharges0[3] = soc_ddrphy_dfiphasemodel3_precharge;
end
always @(*) begin
soc_ddrphy_bankmodel0_precharge = 1'd0;
case (soc_ddrphy_precharges0)
1'd1: begin
soc_ddrphy_bankmodel0_precharge = ((soc_ddrphy_dfi_p0_bank == 1'd0) | soc_ddrphy_dfi_p0_address[10]);
end
2'd2: begin
soc_ddrphy_bankmodel0_precharge = ((soc_ddrphy_dfi_p1_bank == 1'd0) | soc_ddrphy_dfi_p1_address[10]);
end
3'd4: begin
soc_ddrphy_bankmodel0_precharge = ((soc_ddrphy_dfi_p2_bank == 1'd0) | soc_ddrphy_dfi_p2_address[10]);
end
4'd8: begin
soc_ddrphy_bankmodel0_precharge = ((soc_ddrphy_dfi_p3_bank == 1'd0) | soc_ddrphy_dfi_p3_address[10]);
end
endcase
end
always @(*) begin
soc_ddrphy_writes0 = 4'd0;
soc_ddrphy_writes0[0] = soc_ddrphy_dfiphasemodel0_write;
soc_ddrphy_writes0[1] = soc_ddrphy_dfiphasemodel1_write;
soc_ddrphy_writes0[2] = soc_ddrphy_dfiphasemodel2_write;
soc_ddrphy_writes0[3] = soc_ddrphy_dfiphasemodel3_write;
end
always @(*) begin
soc_ddrphy_bank_write_col0 = 10'd0;
case (soc_ddrphy_writes0)
1'd1: begin
soc_ddrphy_bank_write_col0 = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bank_write_col0 = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bank_write_col0 = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bank_write_col0 = soc_ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
soc_ddrphy_bank_write0 = 1'd0;
case (soc_ddrphy_writes0)
1'd1: begin
soc_ddrphy_bank_write0 = (soc_ddrphy_dfi_p0_bank == 1'd0);
end
2'd2: begin
soc_ddrphy_bank_write0 = (soc_ddrphy_dfi_p1_bank == 1'd0);
end
3'd4: begin
soc_ddrphy_bank_write0 = (soc_ddrphy_dfi_p2_bank == 1'd0);
end
4'd8: begin
soc_ddrphy_bank_write0 = (soc_ddrphy_dfi_p3_bank == 1'd0);
end
endcase
end
assign soc_ddrphy_bankmodel0_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata};
assign soc_ddrphy_bankmodel0_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask};
assign soc_ddrphy_bankmodel0_write = soc_ddrphy_new_bank_write0;
assign soc_ddrphy_bankmodel0_write_col = soc_ddrphy_new_bank_write_col0;
always @(*) begin
soc_ddrphy_reads0 = 4'd0;
soc_ddrphy_reads0[0] = soc_ddrphy_dfiphasemodel0_read;
soc_ddrphy_reads0[1] = soc_ddrphy_dfiphasemodel1_read;
soc_ddrphy_reads0[2] = soc_ddrphy_dfiphasemodel2_read;
soc_ddrphy_reads0[3] = soc_ddrphy_dfiphasemodel3_read;
end
always @(*) begin
soc_ddrphy_bankmodel0_read = 1'd0;
case (soc_ddrphy_reads0)
1'd1: begin
soc_ddrphy_bankmodel0_read = (soc_ddrphy_dfi_p0_bank == 1'd0);
end
2'd2: begin
soc_ddrphy_bankmodel0_read = (soc_ddrphy_dfi_p1_bank == 1'd0);
end
3'd4: begin
soc_ddrphy_bankmodel0_read = (soc_ddrphy_dfi_p2_bank == 1'd0);
end
4'd8: begin
soc_ddrphy_bankmodel0_read = (soc_ddrphy_dfi_p3_bank == 1'd0);
end
endcase
end
always @(*) begin
soc_ddrphy_bankmodel0_read_col = 10'd0;
case (soc_ddrphy_reads0)
1'd1: begin
soc_ddrphy_bankmodel0_read_col = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bankmodel0_read_col = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bankmodel0_read_col = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bankmodel0_read_col = soc_ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
soc_ddrphy_activates1 = 4'd0;
soc_ddrphy_activates1[0] = soc_ddrphy_dfiphasemodel0_activate;
soc_ddrphy_activates1[1] = soc_ddrphy_dfiphasemodel1_activate;
soc_ddrphy_activates1[2] = soc_ddrphy_dfiphasemodel2_activate;
soc_ddrphy_activates1[3] = soc_ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
soc_ddrphy_bankmodel1_activate = 1'd0;
case (soc_ddrphy_activates1)
1'd1: begin
soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p0_bank == 1'd1);
end
2'd2: begin
soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p1_bank == 1'd1);
end
3'd4: begin
soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p2_bank == 1'd1);
end
4'd8: begin
soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p3_bank == 1'd1);
end
endcase
end
always @(*) begin
soc_ddrphy_bankmodel1_activate_row = 14'd0;
case (soc_ddrphy_activates1)
1'd1: begin
soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
soc_ddrphy_precharges1 = 4'd0;
soc_ddrphy_precharges1[0] = soc_ddrphy_dfiphasemodel0_precharge;
soc_ddrphy_precharges1[1] = soc_ddrphy_dfiphasemodel1_precharge;
soc_ddrphy_precharges1[2] = soc_ddrphy_dfiphasemodel2_precharge;
soc_ddrphy_precharges1[3] = soc_ddrphy_dfiphasemodel3_precharge;
end
always @(*) begin
soc_ddrphy_bankmodel1_precharge = 1'd0;
case (soc_ddrphy_precharges1)
1'd1: begin
soc_ddrphy_bankmodel1_precharge = ((soc_ddrphy_dfi_p0_bank == 1'd1) | soc_ddrphy_dfi_p0_address[10]);
end
2'd2: begin
soc_ddrphy_bankmodel1_precharge = ((soc_ddrphy_dfi_p1_bank == 1'd1) | soc_ddrphy_dfi_p1_address[10]);
end
3'd4: begin
soc_ddrphy_bankmodel1_precharge = ((soc_ddrphy_dfi_p2_bank == 1'd1) | soc_ddrphy_dfi_p2_address[10]);
end
4'd8: begin
soc_ddrphy_bankmodel1_precharge = ((soc_ddrphy_dfi_p3_bank == 1'd1) | soc_ddrphy_dfi_p3_address[10]);
end
endcase
end
always @(*) begin
soc_ddrphy_writes1 = 4'd0;
soc_ddrphy_writes1[0] = soc_ddrphy_dfiphasemodel0_write;
soc_ddrphy_writes1[1] = soc_ddrphy_dfiphasemodel1_write;
soc_ddrphy_writes1[2] = soc_ddrphy_dfiphasemodel2_write;
soc_ddrphy_writes1[3] = soc_ddrphy_dfiphasemodel3_write;
end
always @(*) begin
soc_ddrphy_bank_write1 = 1'd0;
case (soc_ddrphy_writes1)
1'd1: begin
soc_ddrphy_bank_write1 = (soc_ddrphy_dfi_p0_bank == 1'd1);
end
2'd2: begin
soc_ddrphy_bank_write1 = (soc_ddrphy_dfi_p1_bank == 1'd1);
end
3'd4: begin
soc_ddrphy_bank_write1 = (soc_ddrphy_dfi_p2_bank == 1'd1);
end
4'd8: begin
soc_ddrphy_bank_write1 = (soc_ddrphy_dfi_p3_bank == 1'd1);
end
endcase
end
always @(*) begin
soc_ddrphy_bank_write_col1 = 10'd0;
case (soc_ddrphy_writes1)
1'd1: begin
soc_ddrphy_bank_write_col1 = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bank_write_col1 = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bank_write_col1 = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bank_write_col1 = soc_ddrphy_dfi_p3_address;
end
endcase
end
assign soc_ddrphy_bankmodel1_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata};
assign soc_ddrphy_bankmodel1_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask};
assign soc_ddrphy_bankmodel1_write = soc_ddrphy_new_bank_write1;
assign soc_ddrphy_bankmodel1_write_col = soc_ddrphy_new_bank_write_col1;
always @(*) begin
soc_ddrphy_reads1 = 4'd0;
soc_ddrphy_reads1[0] = soc_ddrphy_dfiphasemodel0_read;
soc_ddrphy_reads1[1] = soc_ddrphy_dfiphasemodel1_read;
soc_ddrphy_reads1[2] = soc_ddrphy_dfiphasemodel2_read;
soc_ddrphy_reads1[3] = soc_ddrphy_dfiphasemodel3_read;
end
always @(*) begin
soc_ddrphy_bankmodel1_read = 1'd0;
case (soc_ddrphy_reads1)
1'd1: begin
soc_ddrphy_bankmodel1_read = (soc_ddrphy_dfi_p0_bank == 1'd1);
end
2'd2: begin
soc_ddrphy_bankmodel1_read = (soc_ddrphy_dfi_p1_bank == 1'd1);
end
3'd4: begin
soc_ddrphy_bankmodel1_read = (soc_ddrphy_dfi_p2_bank == 1'd1);
end
4'd8: begin
soc_ddrphy_bankmodel1_read = (soc_ddrphy_dfi_p3_bank == 1'd1);
end
endcase
end
always @(*) begin
soc_ddrphy_bankmodel1_read_col = 10'd0;
case (soc_ddrphy_reads1)
1'd1: begin
soc_ddrphy_bankmodel1_read_col = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bankmodel1_read_col = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bankmodel1_read_col = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bankmodel1_read_col = soc_ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
soc_ddrphy_activates2 = 4'd0;
soc_ddrphy_activates2[0] = soc_ddrphy_dfiphasemodel0_activate;
soc_ddrphy_activates2[1] = soc_ddrphy_dfiphasemodel1_activate;
soc_ddrphy_activates2[2] = soc_ddrphy_dfiphasemodel2_activate;
soc_ddrphy_activates2[3] = soc_ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
soc_ddrphy_bankmodel2_activate = 1'd0;
case (soc_ddrphy_activates2)
1'd1: begin
soc_ddrphy_bankmodel2_activate = (soc_ddrphy_dfi_p0_bank == 2'd2);
end
2'd2: begin
soc_ddrphy_bankmodel2_activate = (soc_ddrphy_dfi_p1_bank == 2'd2);
end
3'd4: begin
soc_ddrphy_bankmodel2_activate = (soc_ddrphy_dfi_p2_bank == 2'd2);
end
4'd8: begin
soc_ddrphy_bankmodel2_activate = (soc_ddrphy_dfi_p3_bank == 2'd2);
end
endcase
end
always @(*) begin
soc_ddrphy_bankmodel2_activate_row = 14'd0;
case (soc_ddrphy_activates2)
1'd1: begin
soc_ddrphy_bankmodel2_activate_row = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bankmodel2_activate_row = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bankmodel2_activate_row = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bankmodel2_activate_row = soc_ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
soc_ddrphy_precharges2 = 4'd0;
soc_ddrphy_precharges2[0] = soc_ddrphy_dfiphasemodel0_precharge;
soc_ddrphy_precharges2[1] = soc_ddrphy_dfiphasemodel1_precharge;
soc_ddrphy_precharges2[2] = soc_ddrphy_dfiphasemodel2_precharge;
soc_ddrphy_precharges2[3] = soc_ddrphy_dfiphasemodel3_precharge;
end
always @(*) begin
soc_ddrphy_bankmodel2_precharge = 1'd0;
case (soc_ddrphy_precharges2)
1'd1: begin
soc_ddrphy_bankmodel2_precharge = ((soc_ddrphy_dfi_p0_bank == 2'd2) | soc_ddrphy_dfi_p0_address[10]);
end
2'd2: begin
soc_ddrphy_bankmodel2_precharge = ((soc_ddrphy_dfi_p1_bank == 2'd2) | soc_ddrphy_dfi_p1_address[10]);
end
3'd4: begin
soc_ddrphy_bankmodel2_precharge = ((soc_ddrphy_dfi_p2_bank == 2'd2) | soc_ddrphy_dfi_p2_address[10]);
end
4'd8: begin
soc_ddrphy_bankmodel2_precharge = ((soc_ddrphy_dfi_p3_bank == 2'd2) | soc_ddrphy_dfi_p3_address[10]);
end
endcase
end
always @(*) begin
soc_ddrphy_writes2 = 4'd0;
soc_ddrphy_writes2[0] = soc_ddrphy_dfiphasemodel0_write;
soc_ddrphy_writes2[1] = soc_ddrphy_dfiphasemodel1_write;
soc_ddrphy_writes2[2] = soc_ddrphy_dfiphasemodel2_write;
soc_ddrphy_writes2[3] = soc_ddrphy_dfiphasemodel3_write;
end
always @(*) begin
soc_ddrphy_bank_write2 = 1'd0;
case (soc_ddrphy_writes2)
1'd1: begin
soc_ddrphy_bank_write2 = (soc_ddrphy_dfi_p0_bank == 2'd2);
end
2'd2: begin
soc_ddrphy_bank_write2 = (soc_ddrphy_dfi_p1_bank == 2'd2);
end
3'd4: begin
soc_ddrphy_bank_write2 = (soc_ddrphy_dfi_p2_bank == 2'd2);
end
4'd8: begin
soc_ddrphy_bank_write2 = (soc_ddrphy_dfi_p3_bank == 2'd2);
end
endcase
end
always @(*) begin
soc_ddrphy_bank_write_col2 = 10'd0;
case (soc_ddrphy_writes2)
1'd1: begin
soc_ddrphy_bank_write_col2 = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bank_write_col2 = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bank_write_col2 = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bank_write_col2 = soc_ddrphy_dfi_p3_address;
end
endcase
end
assign soc_ddrphy_bankmodel2_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata};
assign soc_ddrphy_bankmodel2_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask};
assign soc_ddrphy_bankmodel2_write = soc_ddrphy_new_bank_write2;
assign soc_ddrphy_bankmodel2_write_col = soc_ddrphy_new_bank_write_col2;
always @(*) begin
soc_ddrphy_reads2 = 4'd0;
soc_ddrphy_reads2[0] = soc_ddrphy_dfiphasemodel0_read;
soc_ddrphy_reads2[1] = soc_ddrphy_dfiphasemodel1_read;
soc_ddrphy_reads2[2] = soc_ddrphy_dfiphasemodel2_read;
soc_ddrphy_reads2[3] = soc_ddrphy_dfiphasemodel3_read;
end
always @(*) begin
soc_ddrphy_bankmodel2_read_col = 10'd0;
case (soc_ddrphy_reads2)
1'd1: begin
soc_ddrphy_bankmodel2_read_col = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bankmodel2_read_col = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bankmodel2_read_col = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bankmodel2_read_col = soc_ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
soc_ddrphy_bankmodel2_read = 1'd0;
case (soc_ddrphy_reads2)
1'd1: begin
soc_ddrphy_bankmodel2_read = (soc_ddrphy_dfi_p0_bank == 2'd2);
end
2'd2: begin
soc_ddrphy_bankmodel2_read = (soc_ddrphy_dfi_p1_bank == 2'd2);
end
3'd4: begin
soc_ddrphy_bankmodel2_read = (soc_ddrphy_dfi_p2_bank == 2'd2);
end
4'd8: begin
soc_ddrphy_bankmodel2_read = (soc_ddrphy_dfi_p3_bank == 2'd2);
end
endcase
end
always @(*) begin
soc_ddrphy_activates3 = 4'd0;
soc_ddrphy_activates3[0] = soc_ddrphy_dfiphasemodel0_activate;
soc_ddrphy_activates3[1] = soc_ddrphy_dfiphasemodel1_activate;
soc_ddrphy_activates3[2] = soc_ddrphy_dfiphasemodel2_activate;
soc_ddrphy_activates3[3] = soc_ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
soc_ddrphy_bankmodel3_activate = 1'd0;
case (soc_ddrphy_activates3)
1'd1: begin
soc_ddrphy_bankmodel3_activate = (soc_ddrphy_dfi_p0_bank == 2'd3);
end
2'd2: begin
soc_ddrphy_bankmodel3_activate = (soc_ddrphy_dfi_p1_bank == 2'd3);
end
3'd4: begin
soc_ddrphy_bankmodel3_activate = (soc_ddrphy_dfi_p2_bank == 2'd3);
end
4'd8: begin
soc_ddrphy_bankmodel3_activate = (soc_ddrphy_dfi_p3_bank == 2'd3);
end
endcase
end
always @(*) begin
soc_ddrphy_bankmodel3_activate_row = 14'd0;
case (soc_ddrphy_activates3)
1'd1: begin
soc_ddrphy_bankmodel3_activate_row = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bankmodel3_activate_row = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bankmodel3_activate_row = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bankmodel3_activate_row = soc_ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
soc_ddrphy_precharges3 = 4'd0;
soc_ddrphy_precharges3[0] = soc_ddrphy_dfiphasemodel0_precharge;
soc_ddrphy_precharges3[1] = soc_ddrphy_dfiphasemodel1_precharge;
soc_ddrphy_precharges3[2] = soc_ddrphy_dfiphasemodel2_precharge;
soc_ddrphy_precharges3[3] = soc_ddrphy_dfiphasemodel3_precharge;
end
always @(*) begin
soc_ddrphy_bankmodel3_precharge = 1'd0;
case (soc_ddrphy_precharges3)
1'd1: begin
soc_ddrphy_bankmodel3_precharge = ((soc_ddrphy_dfi_p0_bank == 2'd3) | soc_ddrphy_dfi_p0_address[10]);
end
2'd2: begin
soc_ddrphy_bankmodel3_precharge = ((soc_ddrphy_dfi_p1_bank == 2'd3) | soc_ddrphy_dfi_p1_address[10]);
end
3'd4: begin
soc_ddrphy_bankmodel3_precharge = ((soc_ddrphy_dfi_p2_bank == 2'd3) | soc_ddrphy_dfi_p2_address[10]);
end
4'd8: begin
soc_ddrphy_bankmodel3_precharge = ((soc_ddrphy_dfi_p3_bank == 2'd3) | soc_ddrphy_dfi_p3_address[10]);
end
endcase
end
always @(*) begin
soc_ddrphy_writes3 = 4'd0;
soc_ddrphy_writes3[0] = soc_ddrphy_dfiphasemodel0_write;
soc_ddrphy_writes3[1] = soc_ddrphy_dfiphasemodel1_write;
soc_ddrphy_writes3[2] = soc_ddrphy_dfiphasemodel2_write;
soc_ddrphy_writes3[3] = soc_ddrphy_dfiphasemodel3_write;
end
always @(*) begin
soc_ddrphy_bank_write3 = 1'd0;
case (soc_ddrphy_writes3)
1'd1: begin
soc_ddrphy_bank_write3 = (soc_ddrphy_dfi_p0_bank == 2'd3);
end
2'd2: begin
soc_ddrphy_bank_write3 = (soc_ddrphy_dfi_p1_bank == 2'd3);
end
3'd4: begin
soc_ddrphy_bank_write3 = (soc_ddrphy_dfi_p2_bank == 2'd3);
end
4'd8: begin
soc_ddrphy_bank_write3 = (soc_ddrphy_dfi_p3_bank == 2'd3);
end
endcase
end
always @(*) begin
soc_ddrphy_bank_write_col3 = 10'd0;
case (soc_ddrphy_writes3)
1'd1: begin
soc_ddrphy_bank_write_col3 = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bank_write_col3 = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bank_write_col3 = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bank_write_col3 = soc_ddrphy_dfi_p3_address;
end
endcase
end
assign soc_ddrphy_bankmodel3_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata};
assign soc_ddrphy_bankmodel3_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask};
assign soc_ddrphy_bankmodel3_write = soc_ddrphy_new_bank_write3;
assign soc_ddrphy_bankmodel3_write_col = soc_ddrphy_new_bank_write_col3;
always @(*) begin
soc_ddrphy_reads3 = 4'd0;
soc_ddrphy_reads3[0] = soc_ddrphy_dfiphasemodel0_read;
soc_ddrphy_reads3[1] = soc_ddrphy_dfiphasemodel1_read;
soc_ddrphy_reads3[2] = soc_ddrphy_dfiphasemodel2_read;
soc_ddrphy_reads3[3] = soc_ddrphy_dfiphasemodel3_read;
end
always @(*) begin
soc_ddrphy_bankmodel3_read = 1'd0;
case (soc_ddrphy_reads3)
1'd1: begin
soc_ddrphy_bankmodel3_read = (soc_ddrphy_dfi_p0_bank == 2'd3);
end
2'd2: begin
soc_ddrphy_bankmodel3_read = (soc_ddrphy_dfi_p1_bank == 2'd3);
end
3'd4: begin
soc_ddrphy_bankmodel3_read = (soc_ddrphy_dfi_p2_bank == 2'd3);
end
4'd8: begin
soc_ddrphy_bankmodel3_read = (soc_ddrphy_dfi_p3_bank == 2'd3);
end
endcase
end
always @(*) begin
soc_ddrphy_bankmodel3_read_col = 10'd0;
case (soc_ddrphy_reads3)
1'd1: begin
soc_ddrphy_bankmodel3_read_col = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bankmodel3_read_col = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bankmodel3_read_col = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bankmodel3_read_col = soc_ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
soc_ddrphy_activates4 = 4'd0;
soc_ddrphy_activates4[0] = soc_ddrphy_dfiphasemodel0_activate;
soc_ddrphy_activates4[1] = soc_ddrphy_dfiphasemodel1_activate;
soc_ddrphy_activates4[2] = soc_ddrphy_dfiphasemodel2_activate;
soc_ddrphy_activates4[3] = soc_ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
soc_ddrphy_bankmodel4_activate_row = 14'd0;
case (soc_ddrphy_activates4)
1'd1: begin
soc_ddrphy_bankmodel4_activate_row = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bankmodel4_activate_row = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bankmodel4_activate_row = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bankmodel4_activate_row = soc_ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
soc_ddrphy_bankmodel4_activate = 1'd0;
case (soc_ddrphy_activates4)
1'd1: begin
soc_ddrphy_bankmodel4_activate = (soc_ddrphy_dfi_p0_bank == 3'd4);
end
2'd2: begin
soc_ddrphy_bankmodel4_activate = (soc_ddrphy_dfi_p1_bank == 3'd4);
end
3'd4: begin
soc_ddrphy_bankmodel4_activate = (soc_ddrphy_dfi_p2_bank == 3'd4);
end
4'd8: begin
soc_ddrphy_bankmodel4_activate = (soc_ddrphy_dfi_p3_bank == 3'd4);
end
endcase
end
always @(*) begin
soc_ddrphy_precharges4 = 4'd0;
soc_ddrphy_precharges4[0] = soc_ddrphy_dfiphasemodel0_precharge;
soc_ddrphy_precharges4[1] = soc_ddrphy_dfiphasemodel1_precharge;
soc_ddrphy_precharges4[2] = soc_ddrphy_dfiphasemodel2_precharge;
soc_ddrphy_precharges4[3] = soc_ddrphy_dfiphasemodel3_precharge;
end
always @(*) begin
soc_ddrphy_bankmodel4_precharge = 1'd0;
case (soc_ddrphy_precharges4)
1'd1: begin
soc_ddrphy_bankmodel4_precharge = ((soc_ddrphy_dfi_p0_bank == 3'd4) | soc_ddrphy_dfi_p0_address[10]);
end
2'd2: begin
soc_ddrphy_bankmodel4_precharge = ((soc_ddrphy_dfi_p1_bank == 3'd4) | soc_ddrphy_dfi_p1_address[10]);
end
3'd4: begin
soc_ddrphy_bankmodel4_precharge = ((soc_ddrphy_dfi_p2_bank == 3'd4) | soc_ddrphy_dfi_p2_address[10]);
end
4'd8: begin
soc_ddrphy_bankmodel4_precharge = ((soc_ddrphy_dfi_p3_bank == 3'd4) | soc_ddrphy_dfi_p3_address[10]);
end
endcase
end
always @(*) begin
soc_ddrphy_writes4 = 4'd0;
soc_ddrphy_writes4[0] = soc_ddrphy_dfiphasemodel0_write;
soc_ddrphy_writes4[1] = soc_ddrphy_dfiphasemodel1_write;
soc_ddrphy_writes4[2] = soc_ddrphy_dfiphasemodel2_write;
soc_ddrphy_writes4[3] = soc_ddrphy_dfiphasemodel3_write;
end
always @(*) begin
soc_ddrphy_bank_write_col4 = 10'd0;
case (soc_ddrphy_writes4)
1'd1: begin
soc_ddrphy_bank_write_col4 = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bank_write_col4 = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bank_write_col4 = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bank_write_col4 = soc_ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
soc_ddrphy_bank_write4 = 1'd0;
case (soc_ddrphy_writes4)
1'd1: begin
soc_ddrphy_bank_write4 = (soc_ddrphy_dfi_p0_bank == 3'd4);
end
2'd2: begin
soc_ddrphy_bank_write4 = (soc_ddrphy_dfi_p1_bank == 3'd4);
end
3'd4: begin
soc_ddrphy_bank_write4 = (soc_ddrphy_dfi_p2_bank == 3'd4);
end
4'd8: begin
soc_ddrphy_bank_write4 = (soc_ddrphy_dfi_p3_bank == 3'd4);
end
endcase
end
assign soc_ddrphy_bankmodel4_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata};
assign soc_ddrphy_bankmodel4_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask};
assign soc_ddrphy_bankmodel4_write = soc_ddrphy_new_bank_write4;
assign soc_ddrphy_bankmodel4_write_col = soc_ddrphy_new_bank_write_col4;
always @(*) begin
soc_ddrphy_reads4 = 4'd0;
soc_ddrphy_reads4[0] = soc_ddrphy_dfiphasemodel0_read;
soc_ddrphy_reads4[1] = soc_ddrphy_dfiphasemodel1_read;
soc_ddrphy_reads4[2] = soc_ddrphy_dfiphasemodel2_read;
soc_ddrphy_reads4[3] = soc_ddrphy_dfiphasemodel3_read;
end
always @(*) begin
soc_ddrphy_bankmodel4_read = 1'd0;
case (soc_ddrphy_reads4)
1'd1: begin
soc_ddrphy_bankmodel4_read = (soc_ddrphy_dfi_p0_bank == 3'd4);
end
2'd2: begin
soc_ddrphy_bankmodel4_read = (soc_ddrphy_dfi_p1_bank == 3'd4);
end
3'd4: begin
soc_ddrphy_bankmodel4_read = (soc_ddrphy_dfi_p2_bank == 3'd4);
end
4'd8: begin
soc_ddrphy_bankmodel4_read = (soc_ddrphy_dfi_p3_bank == 3'd4);
end
endcase
end
always @(*) begin
soc_ddrphy_bankmodel4_read_col = 10'd0;
case (soc_ddrphy_reads4)
1'd1: begin
soc_ddrphy_bankmodel4_read_col = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bankmodel4_read_col = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bankmodel4_read_col = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bankmodel4_read_col = soc_ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
soc_ddrphy_activates5 = 4'd0;
soc_ddrphy_activates5[0] = soc_ddrphy_dfiphasemodel0_activate;
soc_ddrphy_activates5[1] = soc_ddrphy_dfiphasemodel1_activate;
soc_ddrphy_activates5[2] = soc_ddrphy_dfiphasemodel2_activate;
soc_ddrphy_activates5[3] = soc_ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
soc_ddrphy_bankmodel5_activate = 1'd0;
case (soc_ddrphy_activates5)
1'd1: begin
soc_ddrphy_bankmodel5_activate = (soc_ddrphy_dfi_p0_bank == 3'd5);
end
2'd2: begin
soc_ddrphy_bankmodel5_activate = (soc_ddrphy_dfi_p1_bank == 3'd5);
end
3'd4: begin
soc_ddrphy_bankmodel5_activate = (soc_ddrphy_dfi_p2_bank == 3'd5);
end
4'd8: begin
soc_ddrphy_bankmodel5_activate = (soc_ddrphy_dfi_p3_bank == 3'd5);
end
endcase
end
always @(*) begin
soc_ddrphy_bankmodel5_activate_row = 14'd0;
case (soc_ddrphy_activates5)
1'd1: begin
soc_ddrphy_bankmodel5_activate_row = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bankmodel5_activate_row = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bankmodel5_activate_row = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bankmodel5_activate_row = soc_ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
soc_ddrphy_precharges5 = 4'd0;
soc_ddrphy_precharges5[0] = soc_ddrphy_dfiphasemodel0_precharge;
soc_ddrphy_precharges5[1] = soc_ddrphy_dfiphasemodel1_precharge;
soc_ddrphy_precharges5[2] = soc_ddrphy_dfiphasemodel2_precharge;
soc_ddrphy_precharges5[3] = soc_ddrphy_dfiphasemodel3_precharge;
end
always @(*) begin
soc_ddrphy_bankmodel5_precharge = 1'd0;
case (soc_ddrphy_precharges5)
1'd1: begin
soc_ddrphy_bankmodel5_precharge = ((soc_ddrphy_dfi_p0_bank == 3'd5) | soc_ddrphy_dfi_p0_address[10]);
end
2'd2: begin
soc_ddrphy_bankmodel5_precharge = ((soc_ddrphy_dfi_p1_bank == 3'd5) | soc_ddrphy_dfi_p1_address[10]);
end
3'd4: begin
soc_ddrphy_bankmodel5_precharge = ((soc_ddrphy_dfi_p2_bank == 3'd5) | soc_ddrphy_dfi_p2_address[10]);
end
4'd8: begin
soc_ddrphy_bankmodel5_precharge = ((soc_ddrphy_dfi_p3_bank == 3'd5) | soc_ddrphy_dfi_p3_address[10]);
end
endcase
end
always @(*) begin
soc_ddrphy_writes5 = 4'd0;
soc_ddrphy_writes5[0] = soc_ddrphy_dfiphasemodel0_write;
soc_ddrphy_writes5[1] = soc_ddrphy_dfiphasemodel1_write;
soc_ddrphy_writes5[2] = soc_ddrphy_dfiphasemodel2_write;
soc_ddrphy_writes5[3] = soc_ddrphy_dfiphasemodel3_write;
end
always @(*) begin
soc_ddrphy_bank_write5 = 1'd0;
case (soc_ddrphy_writes5)
1'd1: begin
soc_ddrphy_bank_write5 = (soc_ddrphy_dfi_p0_bank == 3'd5);
end
2'd2: begin
soc_ddrphy_bank_write5 = (soc_ddrphy_dfi_p1_bank == 3'd5);
end
3'd4: begin
soc_ddrphy_bank_write5 = (soc_ddrphy_dfi_p2_bank == 3'd5);
end
4'd8: begin
soc_ddrphy_bank_write5 = (soc_ddrphy_dfi_p3_bank == 3'd5);
end
endcase
end
always @(*) begin
soc_ddrphy_bank_write_col5 = 10'd0;
case (soc_ddrphy_writes5)
1'd1: begin
soc_ddrphy_bank_write_col5 = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bank_write_col5 = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bank_write_col5 = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bank_write_col5 = soc_ddrphy_dfi_p3_address;
end
endcase
end
assign soc_ddrphy_bankmodel5_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata};
assign soc_ddrphy_bankmodel5_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask};
assign soc_ddrphy_bankmodel5_write = soc_ddrphy_new_bank_write5;
assign soc_ddrphy_bankmodel5_write_col = soc_ddrphy_new_bank_write_col5;
always @(*) begin
soc_ddrphy_reads5 = 4'd0;
soc_ddrphy_reads5[0] = soc_ddrphy_dfiphasemodel0_read;
soc_ddrphy_reads5[1] = soc_ddrphy_dfiphasemodel1_read;
soc_ddrphy_reads5[2] = soc_ddrphy_dfiphasemodel2_read;
soc_ddrphy_reads5[3] = soc_ddrphy_dfiphasemodel3_read;
end
always @(*) begin
soc_ddrphy_bankmodel5_read_col = 10'd0;
case (soc_ddrphy_reads5)
1'd1: begin
soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
soc_ddrphy_bankmodel5_read = 1'd0;
case (soc_ddrphy_reads5)
1'd1: begin
soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p0_bank == 3'd5);
end
2'd2: begin
soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p1_bank == 3'd5);
end
3'd4: begin
soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p2_bank == 3'd5);
end
4'd8: begin
soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p3_bank == 3'd5);
end
endcase
end
always @(*) begin
soc_ddrphy_activates6 = 4'd0;
soc_ddrphy_activates6[0] = soc_ddrphy_dfiphasemodel0_activate;
soc_ddrphy_activates6[1] = soc_ddrphy_dfiphasemodel1_activate;
soc_ddrphy_activates6[2] = soc_ddrphy_dfiphasemodel2_activate;
soc_ddrphy_activates6[3] = soc_ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
soc_ddrphy_bankmodel6_activate = 1'd0;
case (soc_ddrphy_activates6)
1'd1: begin
soc_ddrphy_bankmodel6_activate = (soc_ddrphy_dfi_p0_bank == 3'd6);
end
2'd2: begin
soc_ddrphy_bankmodel6_activate = (soc_ddrphy_dfi_p1_bank == 3'd6);
end
3'd4: begin
soc_ddrphy_bankmodel6_activate = (soc_ddrphy_dfi_p2_bank == 3'd6);
end
4'd8: begin
soc_ddrphy_bankmodel6_activate = (soc_ddrphy_dfi_p3_bank == 3'd6);
end
endcase
end
always @(*) begin
soc_ddrphy_bankmodel6_activate_row = 14'd0;
case (soc_ddrphy_activates6)
1'd1: begin
soc_ddrphy_bankmodel6_activate_row = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bankmodel6_activate_row = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bankmodel6_activate_row = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bankmodel6_activate_row = soc_ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
soc_ddrphy_precharges6 = 4'd0;
soc_ddrphy_precharges6[0] = soc_ddrphy_dfiphasemodel0_precharge;
soc_ddrphy_precharges6[1] = soc_ddrphy_dfiphasemodel1_precharge;
soc_ddrphy_precharges6[2] = soc_ddrphy_dfiphasemodel2_precharge;
soc_ddrphy_precharges6[3] = soc_ddrphy_dfiphasemodel3_precharge;
end
always @(*) begin
soc_ddrphy_bankmodel6_precharge = 1'd0;
case (soc_ddrphy_precharges6)
1'd1: begin
soc_ddrphy_bankmodel6_precharge = ((soc_ddrphy_dfi_p0_bank == 3'd6) | soc_ddrphy_dfi_p0_address[10]);
end
2'd2: begin
soc_ddrphy_bankmodel6_precharge = ((soc_ddrphy_dfi_p1_bank == 3'd6) | soc_ddrphy_dfi_p1_address[10]);
end
3'd4: begin
soc_ddrphy_bankmodel6_precharge = ((soc_ddrphy_dfi_p2_bank == 3'd6) | soc_ddrphy_dfi_p2_address[10]);
end
4'd8: begin
soc_ddrphy_bankmodel6_precharge = ((soc_ddrphy_dfi_p3_bank == 3'd6) | soc_ddrphy_dfi_p3_address[10]);
end
endcase
end
always @(*) begin
soc_ddrphy_writes6 = 4'd0;
soc_ddrphy_writes6[0] = soc_ddrphy_dfiphasemodel0_write;
soc_ddrphy_writes6[1] = soc_ddrphy_dfiphasemodel1_write;
soc_ddrphy_writes6[2] = soc_ddrphy_dfiphasemodel2_write;
soc_ddrphy_writes6[3] = soc_ddrphy_dfiphasemodel3_write;
end
always @(*) begin
soc_ddrphy_bank_write6 = 1'd0;
case (soc_ddrphy_writes6)
1'd1: begin
soc_ddrphy_bank_write6 = (soc_ddrphy_dfi_p0_bank == 3'd6);
end
2'd2: begin
soc_ddrphy_bank_write6 = (soc_ddrphy_dfi_p1_bank == 3'd6);
end
3'd4: begin
soc_ddrphy_bank_write6 = (soc_ddrphy_dfi_p2_bank == 3'd6);
end
4'd8: begin
soc_ddrphy_bank_write6 = (soc_ddrphy_dfi_p3_bank == 3'd6);
end
endcase
end
always @(*) begin
soc_ddrphy_bank_write_col6 = 10'd0;
case (soc_ddrphy_writes6)
1'd1: begin
soc_ddrphy_bank_write_col6 = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bank_write_col6 = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bank_write_col6 = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bank_write_col6 = soc_ddrphy_dfi_p3_address;
end
endcase
end
assign soc_ddrphy_bankmodel6_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata};
assign soc_ddrphy_bankmodel6_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask};
assign soc_ddrphy_bankmodel6_write = soc_ddrphy_new_bank_write6;
assign soc_ddrphy_bankmodel6_write_col = soc_ddrphy_new_bank_write_col6;
always @(*) begin
soc_ddrphy_reads6 = 4'd0;
soc_ddrphy_reads6[0] = soc_ddrphy_dfiphasemodel0_read;
soc_ddrphy_reads6[1] = soc_ddrphy_dfiphasemodel1_read;
soc_ddrphy_reads6[2] = soc_ddrphy_dfiphasemodel2_read;
soc_ddrphy_reads6[3] = soc_ddrphy_dfiphasemodel3_read;
end
always @(*) begin
soc_ddrphy_bankmodel6_read = 1'd0;
case (soc_ddrphy_reads6)
1'd1: begin
soc_ddrphy_bankmodel6_read = (soc_ddrphy_dfi_p0_bank == 3'd6);
end
2'd2: begin
soc_ddrphy_bankmodel6_read = (soc_ddrphy_dfi_p1_bank == 3'd6);
end
3'd4: begin
soc_ddrphy_bankmodel6_read = (soc_ddrphy_dfi_p2_bank == 3'd6);
end
4'd8: begin
soc_ddrphy_bankmodel6_read = (soc_ddrphy_dfi_p3_bank == 3'd6);
end
endcase
end
always @(*) begin
soc_ddrphy_bankmodel6_read_col = 10'd0;
case (soc_ddrphy_reads6)
1'd1: begin
soc_ddrphy_bankmodel6_read_col = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bankmodel6_read_col = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bankmodel6_read_col = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bankmodel6_read_col = soc_ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
soc_ddrphy_activates7 = 4'd0;
soc_ddrphy_activates7[0] = soc_ddrphy_dfiphasemodel0_activate;
soc_ddrphy_activates7[1] = soc_ddrphy_dfiphasemodel1_activate;
soc_ddrphy_activates7[2] = soc_ddrphy_dfiphasemodel2_activate;
soc_ddrphy_activates7[3] = soc_ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
soc_ddrphy_bankmodel7_activate_row = 14'd0;
case (soc_ddrphy_activates7)
1'd1: begin
soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
soc_ddrphy_bankmodel7_activate = 1'd0;
case (soc_ddrphy_activates7)
1'd1: begin
soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p0_bank == 3'd7);
end
2'd2: begin
soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p1_bank == 3'd7);
end
3'd4: begin
soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p2_bank == 3'd7);
end
4'd8: begin
soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p3_bank == 3'd7);
end
endcase
end
always @(*) begin
soc_ddrphy_precharges7 = 4'd0;
soc_ddrphy_precharges7[0] = soc_ddrphy_dfiphasemodel0_precharge;
soc_ddrphy_precharges7[1] = soc_ddrphy_dfiphasemodel1_precharge;
soc_ddrphy_precharges7[2] = soc_ddrphy_dfiphasemodel2_precharge;
soc_ddrphy_precharges7[3] = soc_ddrphy_dfiphasemodel3_precharge;
end
always @(*) begin
soc_ddrphy_bankmodel7_precharge = 1'd0;
case (soc_ddrphy_precharges7)
1'd1: begin
soc_ddrphy_bankmodel7_precharge = ((soc_ddrphy_dfi_p0_bank == 3'd7) | soc_ddrphy_dfi_p0_address[10]);
end
2'd2: begin
soc_ddrphy_bankmodel7_precharge = ((soc_ddrphy_dfi_p1_bank == 3'd7) | soc_ddrphy_dfi_p1_address[10]);
end
3'd4: begin
soc_ddrphy_bankmodel7_precharge = ((soc_ddrphy_dfi_p2_bank == 3'd7) | soc_ddrphy_dfi_p2_address[10]);
end
4'd8: begin
soc_ddrphy_bankmodel7_precharge = ((soc_ddrphy_dfi_p3_bank == 3'd7) | soc_ddrphy_dfi_p3_address[10]);
end
endcase
end
always @(*) begin
soc_ddrphy_writes7 = 4'd0;
soc_ddrphy_writes7[0] = soc_ddrphy_dfiphasemodel0_write;
soc_ddrphy_writes7[1] = soc_ddrphy_dfiphasemodel1_write;
soc_ddrphy_writes7[2] = soc_ddrphy_dfiphasemodel2_write;
soc_ddrphy_writes7[3] = soc_ddrphy_dfiphasemodel3_write;
end
always @(*) begin
soc_ddrphy_bank_write7 = 1'd0;
case (soc_ddrphy_writes7)
1'd1: begin
soc_ddrphy_bank_write7 = (soc_ddrphy_dfi_p0_bank == 3'd7);
end
2'd2: begin
soc_ddrphy_bank_write7 = (soc_ddrphy_dfi_p1_bank == 3'd7);
end
3'd4: begin
soc_ddrphy_bank_write7 = (soc_ddrphy_dfi_p2_bank == 3'd7);
end
4'd8: begin
soc_ddrphy_bank_write7 = (soc_ddrphy_dfi_p3_bank == 3'd7);
end
endcase
end
always @(*) begin
soc_ddrphy_bank_write_col7 = 10'd0;
case (soc_ddrphy_writes7)
1'd1: begin
soc_ddrphy_bank_write_col7 = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bank_write_col7 = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bank_write_col7 = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bank_write_col7 = soc_ddrphy_dfi_p3_address;
end
endcase
end
assign soc_ddrphy_bankmodel7_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata};
assign soc_ddrphy_bankmodel7_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask};
assign soc_ddrphy_bankmodel7_write = soc_ddrphy_new_bank_write7;
assign soc_ddrphy_bankmodel7_write_col = soc_ddrphy_new_bank_write_col7;
always @(*) begin
soc_ddrphy_reads7 = 4'd0;
soc_ddrphy_reads7[0] = soc_ddrphy_dfiphasemodel0_read;
soc_ddrphy_reads7[1] = soc_ddrphy_dfiphasemodel1_read;
soc_ddrphy_reads7[2] = soc_ddrphy_dfiphasemodel2_read;
soc_ddrphy_reads7[3] = soc_ddrphy_dfiphasemodel3_read;
end
always @(*) begin
soc_ddrphy_bankmodel7_read = 1'd0;
case (soc_ddrphy_reads7)
1'd1: begin
soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p0_bank == 3'd7);
end
2'd2: begin
soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p1_bank == 3'd7);
end
3'd4: begin
soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p2_bank == 3'd7);
end
4'd8: begin
soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p3_bank == 3'd7);
end
endcase
end
always @(*) begin
soc_ddrphy_bankmodel7_read_col = 10'd0;
case (soc_ddrphy_reads7)
1'd1: begin
soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p0_address;
end
2'd2: begin
soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p1_address;
end
3'd4: begin
soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p2_address;
end
4'd8: begin
soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p3_address;
end
endcase
end
assign soc_ddrphy_banks_read = (((((((soc_ddrphy_bankmodel0_read | soc_ddrphy_bankmodel1_read) | soc_ddrphy_bankmodel2_read) | soc_ddrphy_bankmodel3_read) | soc_ddrphy_bankmodel4_read) | soc_ddrphy_bankmodel5_read) | soc_ddrphy_bankmodel6_read) | soc_ddrphy_bankmodel7_read);
assign soc_ddrphy_banks_read_data = (((((((soc_ddrphy_bankmodel0_read_data | soc_ddrphy_bankmodel1_read_data) | soc_ddrphy_bankmodel2_read_data) | soc_ddrphy_bankmodel3_read_data) | soc_ddrphy_bankmodel4_read_data) | soc_ddrphy_bankmodel5_read_data) | soc_ddrphy_bankmodel6_read_data) | soc_ddrphy_bankmodel7_read_data);
assign {soc_ddrphy_dfi_p3_rddata_valid, soc_ddrphy_dfi_p2_rddata_valid, soc_ddrphy_dfi_p1_rddata_valid, soc_ddrphy_dfi_p0_rddata_valid} = soc_ddrphy_new_banks_read7;
assign {soc_ddrphy_dfi_p3_rddata_valid, soc_ddrphy_dfi_p2_rddata_valid, soc_ddrphy_dfi_p1_rddata_valid, soc_ddrphy_dfi_p0_rddata_valid} = soc_ddrphy_new_banks_read7;
assign {soc_ddrphy_dfi_p3_rddata_valid, soc_ddrphy_dfi_p2_rddata_valid, soc_ddrphy_dfi_p1_rddata_valid, soc_ddrphy_dfi_p0_rddata_valid} = soc_ddrphy_new_banks_read7;
assign {soc_ddrphy_dfi_p3_rddata_valid, soc_ddrphy_dfi_p2_rddata_valid, soc_ddrphy_dfi_p1_rddata_valid, soc_ddrphy_dfi_p0_rddata_valid} = soc_ddrphy_new_banks_read7;
assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rddata, soc_ddrphy_dfi_p0_rddata} = soc_ddrphy_new_banks_read_data7;
assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rddata, soc_ddrphy_dfi_p0_rddata} = soc_ddrphy_new_banks_read_data7;
assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rddata, soc_ddrphy_dfi_p0_rddata} = soc_ddrphy_new_banks_read_data7;
assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rddata, soc_ddrphy_dfi_p0_rddata} = soc_ddrphy_new_banks_read_data7;
always @(*) begin
soc_ddrphy_dfiphasemodel0_activate = 1'd0;
if ((((~soc_ddrphy_dfi_p0_cs_n) & (~soc_ddrphy_dfi_p0_ras_n)) & soc_ddrphy_dfi_p0_cas_n)) begin
soc_ddrphy_dfiphasemodel0_activate = soc_ddrphy_dfi_p0_we_n;
end
end
always @(*) begin
soc_ddrphy_dfiphasemodel0_precharge = 1'd0;
if ((((~soc_ddrphy_dfi_p0_cs_n) & (~soc_ddrphy_dfi_p0_ras_n)) & soc_ddrphy_dfi_p0_cas_n)) begin
soc_ddrphy_dfiphasemodel0_precharge = (~soc_ddrphy_dfi_p0_we_n);
end
end
always @(*) begin
soc_ddrphy_dfiphasemodel0_read = 1'd0;
if ((((~soc_ddrphy_dfi_p0_cs_n) & soc_ddrphy_dfi_p0_ras_n) & (~soc_ddrphy_dfi_p0_cas_n))) begin
soc_ddrphy_dfiphasemodel0_read = soc_ddrphy_dfi_p0_we_n;
end
end
always @(*) begin
soc_ddrphy_dfiphasemodel0_write = 1'd0;
if ((((~soc_ddrphy_dfi_p0_cs_n) & soc_ddrphy_dfi_p0_ras_n) & (~soc_ddrphy_dfi_p0_cas_n))) begin
soc_ddrphy_dfiphasemodel0_write = (~soc_ddrphy_dfi_p0_we_n);
end
end
always @(*) begin
soc_ddrphy_dfiphasemodel1_activate = 1'd0;
if ((((~soc_ddrphy_dfi_p1_cs_n) & (~soc_ddrphy_dfi_p1_ras_n)) & soc_ddrphy_dfi_p1_cas_n)) begin
soc_ddrphy_dfiphasemodel1_activate = soc_ddrphy_dfi_p1_we_n;
end
end
always @(*) begin
soc_ddrphy_dfiphasemodel1_precharge = 1'd0;
if ((((~soc_ddrphy_dfi_p1_cs_n) & (~soc_ddrphy_dfi_p1_ras_n)) & soc_ddrphy_dfi_p1_cas_n)) begin
soc_ddrphy_dfiphasemodel1_precharge = (~soc_ddrphy_dfi_p1_we_n);
end
end
always @(*) begin
soc_ddrphy_dfiphasemodel1_write = 1'd0;
if ((((~soc_ddrphy_dfi_p1_cs_n) & soc_ddrphy_dfi_p1_ras_n) & (~soc_ddrphy_dfi_p1_cas_n))) begin
soc_ddrphy_dfiphasemodel1_write = (~soc_ddrphy_dfi_p1_we_n);
end
end
always @(*) begin
soc_ddrphy_dfiphasemodel1_read = 1'd0;
if ((((~soc_ddrphy_dfi_p1_cs_n) & soc_ddrphy_dfi_p1_ras_n) & (~soc_ddrphy_dfi_p1_cas_n))) begin
soc_ddrphy_dfiphasemodel1_read = soc_ddrphy_dfi_p1_we_n;
end
end
always @(*) begin
soc_ddrphy_dfiphasemodel2_precharge = 1'd0;
if ((((~soc_ddrphy_dfi_p2_cs_n) & (~soc_ddrphy_dfi_p2_ras_n)) & soc_ddrphy_dfi_p2_cas_n)) begin
soc_ddrphy_dfiphasemodel2_precharge = (~soc_ddrphy_dfi_p2_we_n);
end
end
always @(*) begin
soc_ddrphy_dfiphasemodel2_activate = 1'd0;
if ((((~soc_ddrphy_dfi_p2_cs_n) & (~soc_ddrphy_dfi_p2_ras_n)) & soc_ddrphy_dfi_p2_cas_n)) begin
soc_ddrphy_dfiphasemodel2_activate = soc_ddrphy_dfi_p2_we_n;
end
end
always @(*) begin
soc_ddrphy_dfiphasemodel2_write = 1'd0;
if ((((~soc_ddrphy_dfi_p2_cs_n) & soc_ddrphy_dfi_p2_ras_n) & (~soc_ddrphy_dfi_p2_cas_n))) begin
soc_ddrphy_dfiphasemodel2_write = (~soc_ddrphy_dfi_p2_we_n);
end
end
always @(*) begin
soc_ddrphy_dfiphasemodel2_read = 1'd0;
if ((((~soc_ddrphy_dfi_p2_cs_n) & soc_ddrphy_dfi_p2_ras_n) & (~soc_ddrphy_dfi_p2_cas_n))) begin
soc_ddrphy_dfiphasemodel2_read = soc_ddrphy_dfi_p2_we_n;
end
end
always @(*) begin
soc_ddrphy_dfiphasemodel3_activate = 1'd0;
if ((((~soc_ddrphy_dfi_p3_cs_n) & (~soc_ddrphy_dfi_p3_ras_n)) & soc_ddrphy_dfi_p3_cas_n)) begin
soc_ddrphy_dfiphasemodel3_activate = soc_ddrphy_dfi_p3_we_n;
end
end
always @(*) begin
soc_ddrphy_dfiphasemodel3_precharge = 1'd0;
if ((((~soc_ddrphy_dfi_p3_cs_n) & (~soc_ddrphy_dfi_p3_ras_n)) & soc_ddrphy_dfi_p3_cas_n)) begin
soc_ddrphy_dfiphasemodel3_precharge = (~soc_ddrphy_dfi_p3_we_n);
end
end
always @(*) begin
soc_ddrphy_dfiphasemodel3_write = 1'd0;
if ((((~soc_ddrphy_dfi_p3_cs_n) & soc_ddrphy_dfi_p3_ras_n) & (~soc_ddrphy_dfi_p3_cas_n))) begin
soc_ddrphy_dfiphasemodel3_write = (~soc_ddrphy_dfi_p3_we_n);
end
end
always @(*) begin
soc_ddrphy_dfiphasemodel3_read = 1'd0;
if ((((~soc_ddrphy_dfi_p3_cs_n) & soc_ddrphy_dfi_p3_ras_n) & (~soc_ddrphy_dfi_p3_cas_n))) begin
soc_ddrphy_dfiphasemodel3_read = soc_ddrphy_dfi_p3_we_n;
end
end
assign soc_ddrphy_bankmodel0_wraddr = slice_proxy0[24:3];
assign soc_ddrphy_bankmodel0_rdaddr = slice_proxy1[24:3];
always @(*) begin
soc_ddrphy_bankmodel0_read_data = 128'd0;
if (soc_ddrphy_bankmodel0_active) begin
if (soc_ddrphy_bankmodel0_read) begin
soc_ddrphy_bankmodel0_read_data = soc_ddrphy_bankmodel0_read_port_dat_r;
end
end
end
always @(*) begin
soc_ddrphy_bankmodel0_write_port_adr = 21'd0;
if (soc_ddrphy_bankmodel0_active) begin
soc_ddrphy_bankmodel0_write_port_adr = soc_ddrphy_bankmodel0_wraddr;
end
end
always @(*) begin
soc_ddrphy_bankmodel0_write_port_we = 16'd0;
if (soc_ddrphy_bankmodel0_active) begin
if (4'd8) begin
soc_ddrphy_bankmodel0_write_port_we = ({16{soc_ddrphy_bankmodel0_write}} & (~soc_ddrphy_bankmodel0_write_mask));
end else begin
soc_ddrphy_bankmodel0_write_port_we = soc_ddrphy_bankmodel0_write;
end
end
end
always @(*) begin
soc_ddrphy_bankmodel0_write_port_dat_w = 128'd0;
if (soc_ddrphy_bankmodel0_active) begin
soc_ddrphy_bankmodel0_write_port_dat_w = soc_ddrphy_bankmodel0_write_data;
end
end
always @(*) begin
soc_ddrphy_bankmodel0_read_port_adr = 21'd0;
if (soc_ddrphy_bankmodel0_active) begin
if (soc_ddrphy_bankmodel0_read) begin
soc_ddrphy_bankmodel0_read_port_adr = soc_ddrphy_bankmodel0_rdaddr;
end
end
end
assign soc_ddrphy_bankmodel1_wraddr = slice_proxy2[24:3];
assign soc_ddrphy_bankmodel1_rdaddr = slice_proxy3[24:3];
always @(*) begin
soc_ddrphy_bankmodel1_write_port_adr = 21'd0;
if (soc_ddrphy_bankmodel1_active) begin
soc_ddrphy_bankmodel1_write_port_adr = soc_ddrphy_bankmodel1_wraddr;
end
end
always @(*) begin
soc_ddrphy_bankmodel1_write_port_we = 16'd0;
if (soc_ddrphy_bankmodel1_active) begin
if (4'd8) begin
soc_ddrphy_bankmodel1_write_port_we = ({16{soc_ddrphy_bankmodel1_write}} & (~soc_ddrphy_bankmodel1_write_mask));
end else begin
soc_ddrphy_bankmodel1_write_port_we = soc_ddrphy_bankmodel1_write;
end
end
end
always @(*) begin
soc_ddrphy_bankmodel1_write_port_dat_w = 128'd0;
if (soc_ddrphy_bankmodel1_active) begin
soc_ddrphy_bankmodel1_write_port_dat_w = soc_ddrphy_bankmodel1_write_data;
end
end
always @(*) begin
soc_ddrphy_bankmodel1_read_port_adr = 21'd0;
if (soc_ddrphy_bankmodel1_active) begin
if (soc_ddrphy_bankmodel1_read) begin
soc_ddrphy_bankmodel1_read_port_adr = soc_ddrphy_bankmodel1_rdaddr;
end
end
end
always @(*) begin
soc_ddrphy_bankmodel1_read_data = 128'd0;
if (soc_ddrphy_bankmodel1_active) begin
if (soc_ddrphy_bankmodel1_read) begin
soc_ddrphy_bankmodel1_read_data = soc_ddrphy_bankmodel1_read_port_dat_r;
end
end
end
assign soc_ddrphy_bankmodel2_wraddr = slice_proxy4[24:3];
assign soc_ddrphy_bankmodel2_rdaddr = slice_proxy5[24:3];
always @(*) begin
soc_ddrphy_bankmodel2_write_port_adr = 21'd0;
if (soc_ddrphy_bankmodel2_active) begin
soc_ddrphy_bankmodel2_write_port_adr = soc_ddrphy_bankmodel2_wraddr;
end
end
always @(*) begin
soc_ddrphy_bankmodel2_write_port_we = 16'd0;
if (soc_ddrphy_bankmodel2_active) begin
if (4'd8) begin
soc_ddrphy_bankmodel2_write_port_we = ({16{soc_ddrphy_bankmodel2_write}} & (~soc_ddrphy_bankmodel2_write_mask));
end else begin
soc_ddrphy_bankmodel2_write_port_we = soc_ddrphy_bankmodel2_write;
end
end
end
always @(*) begin
soc_ddrphy_bankmodel2_write_port_dat_w = 128'd0;
if (soc_ddrphy_bankmodel2_active) begin
soc_ddrphy_bankmodel2_write_port_dat_w = soc_ddrphy_bankmodel2_write_data;
end
end
always @(*) begin
soc_ddrphy_bankmodel2_read_port_adr = 21'd0;
if (soc_ddrphy_bankmodel2_active) begin
if (soc_ddrphy_bankmodel2_read) begin
soc_ddrphy_bankmodel2_read_port_adr = soc_ddrphy_bankmodel2_rdaddr;
end
end
end
always @(*) begin
soc_ddrphy_bankmodel2_read_data = 128'd0;
if (soc_ddrphy_bankmodel2_active) begin
if (soc_ddrphy_bankmodel2_read) begin
soc_ddrphy_bankmodel2_read_data = soc_ddrphy_bankmodel2_read_port_dat_r;
end
end
end
assign soc_ddrphy_bankmodel3_wraddr = slice_proxy6[24:3];
assign soc_ddrphy_bankmodel3_rdaddr = slice_proxy7[24:3];
always @(*) begin
soc_ddrphy_bankmodel3_write_port_we = 16'd0;
if (soc_ddrphy_bankmodel3_active) begin
if (4'd8) begin
soc_ddrphy_bankmodel3_write_port_we = ({16{soc_ddrphy_bankmodel3_write}} & (~soc_ddrphy_bankmodel3_write_mask));
end else begin
soc_ddrphy_bankmodel3_write_port_we = soc_ddrphy_bankmodel3_write;
end
end
end
always @(*) begin
soc_ddrphy_bankmodel3_write_port_dat_w = 128'd0;
if (soc_ddrphy_bankmodel3_active) begin
soc_ddrphy_bankmodel3_write_port_dat_w = soc_ddrphy_bankmodel3_write_data;
end
end
always @(*) begin
soc_ddrphy_bankmodel3_read_port_adr = 21'd0;
if (soc_ddrphy_bankmodel3_active) begin
if (soc_ddrphy_bankmodel3_read) begin
soc_ddrphy_bankmodel3_read_port_adr = soc_ddrphy_bankmodel3_rdaddr;
end
end
end
always @(*) begin
soc_ddrphy_bankmodel3_read_data = 128'd0;
if (soc_ddrphy_bankmodel3_active) begin
if (soc_ddrphy_bankmodel3_read) begin
soc_ddrphy_bankmodel3_read_data = soc_ddrphy_bankmodel3_read_port_dat_r;
end
end
end
always @(*) begin
soc_ddrphy_bankmodel3_write_port_adr = 21'd0;
if (soc_ddrphy_bankmodel3_active) begin
soc_ddrphy_bankmodel3_write_port_adr = soc_ddrphy_bankmodel3_wraddr;
end
end
assign soc_ddrphy_bankmodel4_wraddr = slice_proxy8[24:3];
assign soc_ddrphy_bankmodel4_rdaddr = slice_proxy9[24:3];
always @(*) begin
soc_ddrphy_bankmodel4_read_port_adr = 21'd0;
if (soc_ddrphy_bankmodel4_active) begin
if (soc_ddrphy_bankmodel4_read) begin
soc_ddrphy_bankmodel4_read_port_adr = soc_ddrphy_bankmodel4_rdaddr;
end
end
end
always @(*) begin
soc_ddrphy_bankmodel4_read_data = 128'd0;
if (soc_ddrphy_bankmodel4_active) begin
if (soc_ddrphy_bankmodel4_read) begin
soc_ddrphy_bankmodel4_read_data = soc_ddrphy_bankmodel4_read_port_dat_r;
end
end
end
always @(*) begin
soc_ddrphy_bankmodel4_write_port_adr = 21'd0;
if (soc_ddrphy_bankmodel4_active) begin
soc_ddrphy_bankmodel4_write_port_adr = soc_ddrphy_bankmodel4_wraddr;
end
end
always @(*) begin
soc_ddrphy_bankmodel4_write_port_we = 16'd0;
if (soc_ddrphy_bankmodel4_active) begin
if (4'd8) begin
soc_ddrphy_bankmodel4_write_port_we = ({16{soc_ddrphy_bankmodel4_write}} & (~soc_ddrphy_bankmodel4_write_mask));
end else begin
soc_ddrphy_bankmodel4_write_port_we = soc_ddrphy_bankmodel4_write;
end
end
end
always @(*) begin
soc_ddrphy_bankmodel4_write_port_dat_w = 128'd0;
if (soc_ddrphy_bankmodel4_active) begin
soc_ddrphy_bankmodel4_write_port_dat_w = soc_ddrphy_bankmodel4_write_data;
end
end
assign soc_ddrphy_bankmodel5_wraddr = slice_proxy10[24:3];
assign soc_ddrphy_bankmodel5_rdaddr = slice_proxy11[24:3];
always @(*) begin
soc_ddrphy_bankmodel5_read_data = 128'd0;
if (soc_ddrphy_bankmodel5_active) begin
if (soc_ddrphy_bankmodel5_read) begin
soc_ddrphy_bankmodel5_read_data = soc_ddrphy_bankmodel5_read_port_dat_r;
end
end
end
always @(*) begin
soc_ddrphy_bankmodel5_write_port_adr = 21'd0;
if (soc_ddrphy_bankmodel5_active) begin
soc_ddrphy_bankmodel5_write_port_adr = soc_ddrphy_bankmodel5_wraddr;
end
end
always @(*) begin
soc_ddrphy_bankmodel5_write_port_we = 16'd0;
if (soc_ddrphy_bankmodel5_active) begin
if (4'd8) begin
soc_ddrphy_bankmodel5_write_port_we = ({16{soc_ddrphy_bankmodel5_write}} & (~soc_ddrphy_bankmodel5_write_mask));
end else begin
soc_ddrphy_bankmodel5_write_port_we = soc_ddrphy_bankmodel5_write;
end
end
end
always @(*) begin
soc_ddrphy_bankmodel5_write_port_dat_w = 128'd0;
if (soc_ddrphy_bankmodel5_active) begin
soc_ddrphy_bankmodel5_write_port_dat_w = soc_ddrphy_bankmodel5_write_data;
end
end
always @(*) begin
soc_ddrphy_bankmodel5_read_port_adr = 21'd0;
if (soc_ddrphy_bankmodel5_active) begin
if (soc_ddrphy_bankmodel5_read) begin
soc_ddrphy_bankmodel5_read_port_adr = soc_ddrphy_bankmodel5_rdaddr;
end
end
end
assign soc_ddrphy_bankmodel6_wraddr = slice_proxy12[24:3];
assign soc_ddrphy_bankmodel6_rdaddr = slice_proxy13[24:3];
always @(*) begin
soc_ddrphy_bankmodel6_read_data = 128'd0;
if (soc_ddrphy_bankmodel6_active) begin
if (soc_ddrphy_bankmodel6_read) begin
soc_ddrphy_bankmodel6_read_data = soc_ddrphy_bankmodel6_read_port_dat_r;
end
end
end
always @(*) begin
soc_ddrphy_bankmodel6_write_port_adr = 21'd0;
if (soc_ddrphy_bankmodel6_active) begin
soc_ddrphy_bankmodel6_write_port_adr = soc_ddrphy_bankmodel6_wraddr;
end
end
always @(*) begin
soc_ddrphy_bankmodel6_write_port_we = 16'd0;
if (soc_ddrphy_bankmodel6_active) begin
if (4'd8) begin
soc_ddrphy_bankmodel6_write_port_we = ({16{soc_ddrphy_bankmodel6_write}} & (~soc_ddrphy_bankmodel6_write_mask));
end else begin
soc_ddrphy_bankmodel6_write_port_we = soc_ddrphy_bankmodel6_write;
end
end
end
always @(*) begin
soc_ddrphy_bankmodel6_write_port_dat_w = 128'd0;
if (soc_ddrphy_bankmodel6_active) begin
soc_ddrphy_bankmodel6_write_port_dat_w = soc_ddrphy_bankmodel6_write_data;
end
end
always @(*) begin
soc_ddrphy_bankmodel6_read_port_adr = 21'd0;
if (soc_ddrphy_bankmodel6_active) begin
if (soc_ddrphy_bankmodel6_read) begin
soc_ddrphy_bankmodel6_read_port_adr = soc_ddrphy_bankmodel6_rdaddr;
end
end
end
assign soc_ddrphy_bankmodel7_wraddr = slice_proxy14[24:3];
assign soc_ddrphy_bankmodel7_rdaddr = slice_proxy15[24:3];
always @(*) begin
soc_ddrphy_bankmodel7_read_data = 128'd0;
if (soc_ddrphy_bankmodel7_active) begin
if (soc_ddrphy_bankmodel7_read) begin
soc_ddrphy_bankmodel7_read_data = soc_ddrphy_bankmodel7_read_port_dat_r;
end
end
end
always @(*) begin
soc_ddrphy_bankmodel7_write_port_adr = 21'd0;
if (soc_ddrphy_bankmodel7_active) begin
soc_ddrphy_bankmodel7_write_port_adr = soc_ddrphy_bankmodel7_wraddr;
end
end
always @(*) begin
soc_ddrphy_bankmodel7_write_port_we = 16'd0;
if (soc_ddrphy_bankmodel7_active) begin
if (4'd8) begin
soc_ddrphy_bankmodel7_write_port_we = ({16{soc_ddrphy_bankmodel7_write}} & (~soc_ddrphy_bankmodel7_write_mask));
end else begin
soc_ddrphy_bankmodel7_write_port_we = soc_ddrphy_bankmodel7_write;
end
end
end
always @(*) begin
soc_ddrphy_bankmodel7_write_port_dat_w = 128'd0;
if (soc_ddrphy_bankmodel7_active) begin
soc_ddrphy_bankmodel7_write_port_dat_w = soc_ddrphy_bankmodel7_write_data;
end
end
always @(*) begin
soc_ddrphy_bankmodel7_read_port_adr = 21'd0;
if (soc_ddrphy_bankmodel7_active) begin
if (soc_ddrphy_bankmodel7_read) begin
soc_ddrphy_bankmodel7_read_port_adr = soc_ddrphy_bankmodel7_rdaddr;
end
end
end
assign soc_ddrphy_dfi_p0_address = soc_litedramcore_master_p0_address;
assign soc_ddrphy_dfi_p0_bank = soc_litedramcore_master_p0_bank;
assign soc_ddrphy_dfi_p0_cas_n = soc_litedramcore_master_p0_cas_n;
assign soc_ddrphy_dfi_p0_cs_n = soc_litedramcore_master_p0_cs_n;
assign soc_ddrphy_dfi_p0_ras_n = soc_litedramcore_master_p0_ras_n;
assign soc_ddrphy_dfi_p0_we_n = soc_litedramcore_master_p0_we_n;
assign soc_ddrphy_dfi_p0_cke = soc_litedramcore_master_p0_cke;
assign soc_ddrphy_dfi_p0_odt = soc_litedramcore_master_p0_odt;
assign soc_ddrphy_dfi_p0_reset_n = soc_litedramcore_master_p0_reset_n;
assign soc_ddrphy_dfi_p0_act_n = soc_litedramcore_master_p0_act_n;
assign soc_ddrphy_dfi_p0_wrdata = soc_litedramcore_master_p0_wrdata;
assign soc_ddrphy_dfi_p0_wrdata_en = soc_litedramcore_master_p0_wrdata_en;
assign soc_ddrphy_dfi_p0_wrdata_mask = soc_litedramcore_master_p0_wrdata_mask;
assign soc_ddrphy_dfi_p0_rddata_en = soc_litedramcore_master_p0_rddata_en;
assign soc_litedramcore_master_p0_rddata = soc_ddrphy_dfi_p0_rddata;
assign soc_litedramcore_master_p0_rddata_valid = soc_ddrphy_dfi_p0_rddata_valid;
assign soc_ddrphy_dfi_p1_address = soc_litedramcore_master_p1_address;
assign soc_ddrphy_dfi_p1_bank = soc_litedramcore_master_p1_bank;
assign soc_ddrphy_dfi_p1_cas_n = soc_litedramcore_master_p1_cas_n;
assign soc_ddrphy_dfi_p1_cs_n = soc_litedramcore_master_p1_cs_n;
assign soc_ddrphy_dfi_p1_ras_n = soc_litedramcore_master_p1_ras_n;
assign soc_ddrphy_dfi_p1_we_n = soc_litedramcore_master_p1_we_n;
assign soc_ddrphy_dfi_p1_cke = soc_litedramcore_master_p1_cke;
assign soc_ddrphy_dfi_p1_odt = soc_litedramcore_master_p1_odt;
assign soc_ddrphy_dfi_p1_reset_n = soc_litedramcore_master_p1_reset_n;
assign soc_ddrphy_dfi_p1_act_n = soc_litedramcore_master_p1_act_n;
assign soc_ddrphy_dfi_p1_wrdata = soc_litedramcore_master_p1_wrdata;
assign soc_ddrphy_dfi_p1_wrdata_en = soc_litedramcore_master_p1_wrdata_en;
assign soc_ddrphy_dfi_p1_wrdata_mask = soc_litedramcore_master_p1_wrdata_mask;
assign soc_ddrphy_dfi_p1_rddata_en = soc_litedramcore_master_p1_rddata_en;
assign soc_litedramcore_master_p1_rddata = soc_ddrphy_dfi_p1_rddata;
assign soc_litedramcore_master_p1_rddata_valid = soc_ddrphy_dfi_p1_rddata_valid;
assign soc_ddrphy_dfi_p2_address = soc_litedramcore_master_p2_address;
assign soc_ddrphy_dfi_p2_bank = soc_litedramcore_master_p2_bank;
assign soc_ddrphy_dfi_p2_cas_n = soc_litedramcore_master_p2_cas_n;
assign soc_ddrphy_dfi_p2_cs_n = soc_litedramcore_master_p2_cs_n;
assign soc_ddrphy_dfi_p2_ras_n = soc_litedramcore_master_p2_ras_n;
assign soc_ddrphy_dfi_p2_we_n = soc_litedramcore_master_p2_we_n;
assign soc_ddrphy_dfi_p2_cke = soc_litedramcore_master_p2_cke;
assign soc_ddrphy_dfi_p2_odt = soc_litedramcore_master_p2_odt;
assign soc_ddrphy_dfi_p2_reset_n = soc_litedramcore_master_p2_reset_n;
assign soc_ddrphy_dfi_p2_act_n = soc_litedramcore_master_p2_act_n;
assign soc_ddrphy_dfi_p2_wrdata = soc_litedramcore_master_p2_wrdata;
assign soc_ddrphy_dfi_p2_wrdata_en = soc_litedramcore_master_p2_wrdata_en;
assign soc_ddrphy_dfi_p2_wrdata_mask = soc_litedramcore_master_p2_wrdata_mask;
assign soc_ddrphy_dfi_p2_rddata_en = soc_litedramcore_master_p2_rddata_en;
assign soc_litedramcore_master_p2_rddata = soc_ddrphy_dfi_p2_rddata;
assign soc_litedramcore_master_p2_rddata_valid = soc_ddrphy_dfi_p2_rddata_valid;
assign soc_ddrphy_dfi_p3_address = soc_litedramcore_master_p3_address;
assign soc_ddrphy_dfi_p3_bank = soc_litedramcore_master_p3_bank;
assign soc_ddrphy_dfi_p3_cas_n = soc_litedramcore_master_p3_cas_n;
assign soc_ddrphy_dfi_p3_cs_n = soc_litedramcore_master_p3_cs_n;
assign soc_ddrphy_dfi_p3_ras_n = soc_litedramcore_master_p3_ras_n;
assign soc_ddrphy_dfi_p3_we_n = soc_litedramcore_master_p3_we_n;
assign soc_ddrphy_dfi_p3_cke = soc_litedramcore_master_p3_cke;
assign soc_ddrphy_dfi_p3_odt = soc_litedramcore_master_p3_odt;
assign soc_ddrphy_dfi_p3_reset_n = soc_litedramcore_master_p3_reset_n;
assign soc_ddrphy_dfi_p3_act_n = soc_litedramcore_master_p3_act_n;
assign soc_ddrphy_dfi_p3_wrdata = soc_litedramcore_master_p3_wrdata;
assign soc_ddrphy_dfi_p3_wrdata_en = soc_litedramcore_master_p3_wrdata_en;
assign soc_ddrphy_dfi_p3_wrdata_mask = soc_litedramcore_master_p3_wrdata_mask;
assign soc_ddrphy_dfi_p3_rddata_en = soc_litedramcore_master_p3_rddata_en;
assign soc_litedramcore_master_p3_rddata = soc_ddrphy_dfi_p3_rddata;
assign soc_litedramcore_master_p3_rddata_valid = soc_ddrphy_dfi_p3_rddata_valid;
assign soc_litedramcore_slave_p0_address = soc_litedramcore_dfi_p0_address;
assign soc_litedramcore_slave_p0_bank = soc_litedramcore_dfi_p0_bank;
assign soc_litedramcore_slave_p0_cas_n = soc_litedramcore_dfi_p0_cas_n;
assign soc_litedramcore_slave_p0_cs_n = soc_litedramcore_dfi_p0_cs_n;
assign soc_litedramcore_slave_p0_ras_n = soc_litedramcore_dfi_p0_ras_n;
assign soc_litedramcore_slave_p0_we_n = soc_litedramcore_dfi_p0_we_n;
assign soc_litedramcore_slave_p0_cke = soc_litedramcore_dfi_p0_cke;
assign soc_litedramcore_slave_p0_odt = soc_litedramcore_dfi_p0_odt;
assign soc_litedramcore_slave_p0_reset_n = soc_litedramcore_dfi_p0_reset_n;
assign soc_litedramcore_slave_p0_act_n = soc_litedramcore_dfi_p0_act_n;
assign soc_litedramcore_slave_p0_wrdata = soc_litedramcore_dfi_p0_wrdata;
assign soc_litedramcore_slave_p0_wrdata_en = soc_litedramcore_dfi_p0_wrdata_en;
assign soc_litedramcore_slave_p0_wrdata_mask = soc_litedramcore_dfi_p0_wrdata_mask;
assign soc_litedramcore_slave_p0_rddata_en = soc_litedramcore_dfi_p0_rddata_en;
assign soc_litedramcore_dfi_p0_rddata = soc_litedramcore_slave_p0_rddata;
assign soc_litedramcore_dfi_p0_rddata_valid = soc_litedramcore_slave_p0_rddata_valid;
assign soc_litedramcore_slave_p1_address = soc_litedramcore_dfi_p1_address;
assign soc_litedramcore_slave_p1_bank = soc_litedramcore_dfi_p1_bank;
assign soc_litedramcore_slave_p1_cas_n = soc_litedramcore_dfi_p1_cas_n;
assign soc_litedramcore_slave_p1_cs_n = soc_litedramcore_dfi_p1_cs_n;
assign soc_litedramcore_slave_p1_ras_n = soc_litedramcore_dfi_p1_ras_n;
assign soc_litedramcore_slave_p1_we_n = soc_litedramcore_dfi_p1_we_n;
assign soc_litedramcore_slave_p1_cke = soc_litedramcore_dfi_p1_cke;
assign soc_litedramcore_slave_p1_odt = soc_litedramcore_dfi_p1_odt;
assign soc_litedramcore_slave_p1_reset_n = soc_litedramcore_dfi_p1_reset_n;
assign soc_litedramcore_slave_p1_act_n = soc_litedramcore_dfi_p1_act_n;
assign soc_litedramcore_slave_p1_wrdata = soc_litedramcore_dfi_p1_wrdata;
assign soc_litedramcore_slave_p1_wrdata_en = soc_litedramcore_dfi_p1_wrdata_en;
assign soc_litedramcore_slave_p1_wrdata_mask = soc_litedramcore_dfi_p1_wrdata_mask;
assign soc_litedramcore_slave_p1_rddata_en = soc_litedramcore_dfi_p1_rddata_en;
assign soc_litedramcore_dfi_p1_rddata = soc_litedramcore_slave_p1_rddata;
assign soc_litedramcore_dfi_p1_rddata_valid = soc_litedramcore_slave_p1_rddata_valid;
assign soc_litedramcore_slave_p2_address = soc_litedramcore_dfi_p2_address;
assign soc_litedramcore_slave_p2_bank = soc_litedramcore_dfi_p2_bank;
assign soc_litedramcore_slave_p2_cas_n = soc_litedramcore_dfi_p2_cas_n;
assign soc_litedramcore_slave_p2_cs_n = soc_litedramcore_dfi_p2_cs_n;
assign soc_litedramcore_slave_p2_ras_n = soc_litedramcore_dfi_p2_ras_n;
assign soc_litedramcore_slave_p2_we_n = soc_litedramcore_dfi_p2_we_n;
assign soc_litedramcore_slave_p2_cke = soc_litedramcore_dfi_p2_cke;
assign soc_litedramcore_slave_p2_odt = soc_litedramcore_dfi_p2_odt;
assign soc_litedramcore_slave_p2_reset_n = soc_litedramcore_dfi_p2_reset_n;
assign soc_litedramcore_slave_p2_act_n = soc_litedramcore_dfi_p2_act_n;
assign soc_litedramcore_slave_p2_wrdata = soc_litedramcore_dfi_p2_wrdata;
assign soc_litedramcore_slave_p2_wrdata_en = soc_litedramcore_dfi_p2_wrdata_en;
assign soc_litedramcore_slave_p2_wrdata_mask = soc_litedramcore_dfi_p2_wrdata_mask;
assign soc_litedramcore_slave_p2_rddata_en = soc_litedramcore_dfi_p2_rddata_en;
assign soc_litedramcore_dfi_p2_rddata = soc_litedramcore_slave_p2_rddata;
assign soc_litedramcore_dfi_p2_rddata_valid = soc_litedramcore_slave_p2_rddata_valid;
assign soc_litedramcore_slave_p3_address = soc_litedramcore_dfi_p3_address;
assign soc_litedramcore_slave_p3_bank = soc_litedramcore_dfi_p3_bank;
assign soc_litedramcore_slave_p3_cas_n = soc_litedramcore_dfi_p3_cas_n;
assign soc_litedramcore_slave_p3_cs_n = soc_litedramcore_dfi_p3_cs_n;
assign soc_litedramcore_slave_p3_ras_n = soc_litedramcore_dfi_p3_ras_n;
assign soc_litedramcore_slave_p3_we_n = soc_litedramcore_dfi_p3_we_n;
assign soc_litedramcore_slave_p3_cke = soc_litedramcore_dfi_p3_cke;
assign soc_litedramcore_slave_p3_odt = soc_litedramcore_dfi_p3_odt;
assign soc_litedramcore_slave_p3_reset_n = soc_litedramcore_dfi_p3_reset_n;
assign soc_litedramcore_slave_p3_act_n = soc_litedramcore_dfi_p3_act_n;
assign soc_litedramcore_slave_p3_wrdata = soc_litedramcore_dfi_p3_wrdata;
assign soc_litedramcore_slave_p3_wrdata_en = soc_litedramcore_dfi_p3_wrdata_en;
assign soc_litedramcore_slave_p3_wrdata_mask = soc_litedramcore_dfi_p3_wrdata_mask;
assign soc_litedramcore_slave_p3_rddata_en = soc_litedramcore_dfi_p3_rddata_en;
assign soc_litedramcore_dfi_p3_rddata = soc_litedramcore_slave_p3_rddata;
assign soc_litedramcore_dfi_p3_rddata_valid = soc_litedramcore_slave_p3_rddata_valid;
always @(*) begin
soc_litedramcore_master_p0_we_n = 1'd1;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p0_we_n = soc_litedramcore_slave_p0_we_n;
end else begin
soc_litedramcore_master_p0_we_n = soc_litedramcore_inti_p0_we_n;
end
end
always @(*) begin
soc_litedramcore_slave_p0_rddata_valid = 1'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_slave_p0_rddata_valid = soc_litedramcore_master_p0_rddata_valid;
end else begin
end
end
always @(*) begin
soc_litedramcore_master_p0_cke = 1'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p0_cke = soc_litedramcore_slave_p0_cke;
end else begin
soc_litedramcore_master_p0_cke = soc_litedramcore_inti_p0_cke;
end
end
always @(*) begin
soc_litedramcore_master_p0_odt = 1'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p0_odt = soc_litedramcore_slave_p0_odt;
end else begin
soc_litedramcore_master_p0_odt = soc_litedramcore_inti_p0_odt;
end
end
always @(*) begin
soc_litedramcore_master_p0_reset_n = 1'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p0_reset_n = soc_litedramcore_slave_p0_reset_n;
end else begin
soc_litedramcore_master_p0_reset_n = soc_litedramcore_inti_p0_reset_n;
end
end
always @(*) begin
soc_litedramcore_master_p0_act_n = 1'd1;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p0_act_n = soc_litedramcore_slave_p0_act_n;
end else begin
soc_litedramcore_master_p0_act_n = soc_litedramcore_inti_p0_act_n;
end
end
always @(*) begin
soc_litedramcore_master_p0_wrdata = 32'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p0_wrdata = soc_litedramcore_slave_p0_wrdata;
end else begin
soc_litedramcore_master_p0_wrdata = soc_litedramcore_inti_p0_wrdata;
end
end
always @(*) begin
soc_litedramcore_inti_p1_rddata = 32'd0;
if (soc_litedramcore_sel) begin
end else begin
soc_litedramcore_inti_p1_rddata = soc_litedramcore_master_p1_rddata;
end
end
always @(*) begin
soc_litedramcore_master_p0_wrdata_en = 1'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p0_wrdata_en = soc_litedramcore_slave_p0_wrdata_en;
end else begin
soc_litedramcore_master_p0_wrdata_en = soc_litedramcore_inti_p0_wrdata_en;
end
end
always @(*) begin
soc_litedramcore_inti_p1_rddata_valid = 1'd0;
if (soc_litedramcore_sel) begin
end else begin
soc_litedramcore_inti_p1_rddata_valid = soc_litedramcore_master_p1_rddata_valid;
end
end
always @(*) begin
soc_litedramcore_master_p0_wrdata_mask = 4'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p0_wrdata_mask = soc_litedramcore_slave_p0_wrdata_mask;
end else begin
soc_litedramcore_master_p0_wrdata_mask = soc_litedramcore_inti_p0_wrdata_mask;
end
end
always @(*) begin
soc_litedramcore_master_p0_rddata_en = 1'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p0_rddata_en = soc_litedramcore_slave_p0_rddata_en;
end else begin
soc_litedramcore_master_p0_rddata_en = soc_litedramcore_inti_p0_rddata_en;
end
end
always @(*) begin
soc_litedramcore_master_p1_address = 14'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p1_address = soc_litedramcore_slave_p1_address;
end else begin
soc_litedramcore_master_p1_address = soc_litedramcore_inti_p1_address;
end
end
always @(*) begin
soc_litedramcore_master_p1_bank = 3'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p1_bank = soc_litedramcore_slave_p1_bank;
end else begin
soc_litedramcore_master_p1_bank = soc_litedramcore_inti_p1_bank;
end
end
always @(*) begin
soc_litedramcore_master_p1_cas_n = 1'd1;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p1_cas_n = soc_litedramcore_slave_p1_cas_n;
end else begin
soc_litedramcore_master_p1_cas_n = soc_litedramcore_inti_p1_cas_n;
end
end
always @(*) begin
soc_litedramcore_master_p1_cs_n = 1'd1;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p1_cs_n = soc_litedramcore_slave_p1_cs_n;
end else begin
soc_litedramcore_master_p1_cs_n = soc_litedramcore_inti_p1_cs_n;
end
end
always @(*) begin
soc_litedramcore_master_p1_ras_n = 1'd1;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p1_ras_n = soc_litedramcore_slave_p1_ras_n;
end else begin
soc_litedramcore_master_p1_ras_n = soc_litedramcore_inti_p1_ras_n;
end
end
always @(*) begin
soc_litedramcore_slave_p1_rddata = 32'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_slave_p1_rddata = soc_litedramcore_master_p1_rddata;
end else begin
end
end
always @(*) begin
soc_litedramcore_master_p1_we_n = 1'd1;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p1_we_n = soc_litedramcore_slave_p1_we_n;
end else begin
soc_litedramcore_master_p1_we_n = soc_litedramcore_inti_p1_we_n;
end
end
always @(*) begin
soc_litedramcore_slave_p1_rddata_valid = 1'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_slave_p1_rddata_valid = soc_litedramcore_master_p1_rddata_valid;
end else begin
end
end
always @(*) begin
soc_litedramcore_master_p1_cke = 1'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p1_cke = soc_litedramcore_slave_p1_cke;
end else begin
soc_litedramcore_master_p1_cke = soc_litedramcore_inti_p1_cke;
end
end
always @(*) begin
soc_litedramcore_master_p1_odt = 1'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p1_odt = soc_litedramcore_slave_p1_odt;
end else begin
soc_litedramcore_master_p1_odt = soc_litedramcore_inti_p1_odt;
end
end
always @(*) begin
soc_litedramcore_master_p1_reset_n = 1'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p1_reset_n = soc_litedramcore_slave_p1_reset_n;
end else begin
soc_litedramcore_master_p1_reset_n = soc_litedramcore_inti_p1_reset_n;
end
end
always @(*) begin
soc_litedramcore_master_p1_act_n = 1'd1;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p1_act_n = soc_litedramcore_slave_p1_act_n;
end else begin
soc_litedramcore_master_p1_act_n = soc_litedramcore_inti_p1_act_n;
end
end
always @(*) begin
soc_litedramcore_master_p1_wrdata = 32'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p1_wrdata = soc_litedramcore_slave_p1_wrdata;
end else begin
soc_litedramcore_master_p1_wrdata = soc_litedramcore_inti_p1_wrdata;
end
end
always @(*) begin
soc_litedramcore_inti_p2_rddata = 32'd0;
if (soc_litedramcore_sel) begin
end else begin
soc_litedramcore_inti_p2_rddata = soc_litedramcore_master_p2_rddata;
end
end
always @(*) begin
soc_litedramcore_master_p1_wrdata_en = 1'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p1_wrdata_en = soc_litedramcore_slave_p1_wrdata_en;
end else begin
soc_litedramcore_master_p1_wrdata_en = soc_litedramcore_inti_p1_wrdata_en;
end
end
always @(*) begin
soc_litedramcore_inti_p2_rddata_valid = 1'd0;
if (soc_litedramcore_sel) begin
end else begin
soc_litedramcore_inti_p2_rddata_valid = soc_litedramcore_master_p2_rddata_valid;
end
end
always @(*) begin
soc_litedramcore_master_p0_ras_n = 1'd1;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p0_ras_n = soc_litedramcore_slave_p0_ras_n;
end else begin
soc_litedramcore_master_p0_ras_n = soc_litedramcore_inti_p0_ras_n;
end
end
always @(*) begin
soc_litedramcore_master_p1_wrdata_mask = 4'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p1_wrdata_mask = soc_litedramcore_slave_p1_wrdata_mask;
end else begin
soc_litedramcore_master_p1_wrdata_mask = soc_litedramcore_inti_p1_wrdata_mask;
end
end
always @(*) begin
soc_litedramcore_master_p1_rddata_en = 1'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p1_rddata_en = soc_litedramcore_slave_p1_rddata_en;
end else begin
soc_litedramcore_master_p1_rddata_en = soc_litedramcore_inti_p1_rddata_en;
end
end
always @(*) begin
soc_litedramcore_master_p2_address = 14'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p2_address = soc_litedramcore_slave_p2_address;
end else begin
soc_litedramcore_master_p2_address = soc_litedramcore_inti_p2_address;
end
end
always @(*) begin
soc_litedramcore_master_p2_bank = 3'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p2_bank = soc_litedramcore_slave_p2_bank;
end else begin
soc_litedramcore_master_p2_bank = soc_litedramcore_inti_p2_bank;
end
end
always @(*) begin
soc_litedramcore_master_p2_cas_n = 1'd1;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p2_cas_n = soc_litedramcore_slave_p2_cas_n;
end else begin
soc_litedramcore_master_p2_cas_n = soc_litedramcore_inti_p2_cas_n;
end
end
always @(*) begin
soc_litedramcore_master_p2_cs_n = 1'd1;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p2_cs_n = soc_litedramcore_slave_p2_cs_n;
end else begin
soc_litedramcore_master_p2_cs_n = soc_litedramcore_inti_p2_cs_n;
end
end
always @(*) begin
soc_litedramcore_master_p2_ras_n = 1'd1;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p2_ras_n = soc_litedramcore_slave_p2_ras_n;
end else begin
soc_litedramcore_master_p2_ras_n = soc_litedramcore_inti_p2_ras_n;
end
end
always @(*) begin
soc_litedramcore_slave_p2_rddata = 32'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_slave_p2_rddata = soc_litedramcore_master_p2_rddata;
end else begin
end
end
always @(*) begin
soc_litedramcore_master_p2_we_n = 1'd1;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p2_we_n = soc_litedramcore_slave_p2_we_n;
end else begin
soc_litedramcore_master_p2_we_n = soc_litedramcore_inti_p2_we_n;
end
end
always @(*) begin
soc_litedramcore_slave_p2_rddata_valid = 1'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_slave_p2_rddata_valid = soc_litedramcore_master_p2_rddata_valid;
end else begin
end
end
always @(*) begin
soc_litedramcore_master_p2_cke = 1'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p2_cke = soc_litedramcore_slave_p2_cke;
end else begin
soc_litedramcore_master_p2_cke = soc_litedramcore_inti_p2_cke;
end
end
always @(*) begin
soc_litedramcore_master_p2_odt = 1'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p2_odt = soc_litedramcore_slave_p2_odt;
end else begin
soc_litedramcore_master_p2_odt = soc_litedramcore_inti_p2_odt;
end
end
always @(*) begin
soc_litedramcore_master_p2_reset_n = 1'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p2_reset_n = soc_litedramcore_slave_p2_reset_n;
end else begin
soc_litedramcore_master_p2_reset_n = soc_litedramcore_inti_p2_reset_n;
end
end
always @(*) begin
soc_litedramcore_master_p2_act_n = 1'd1;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p2_act_n = soc_litedramcore_slave_p2_act_n;
end else begin
soc_litedramcore_master_p2_act_n = soc_litedramcore_inti_p2_act_n;
end
end
always @(*) begin
soc_litedramcore_master_p2_wrdata = 32'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p2_wrdata = soc_litedramcore_slave_p2_wrdata;
end else begin
soc_litedramcore_master_p2_wrdata = soc_litedramcore_inti_p2_wrdata;
end
end
always @(*) begin
soc_litedramcore_inti_p3_rddata = 32'd0;
if (soc_litedramcore_sel) begin
end else begin
soc_litedramcore_inti_p3_rddata = soc_litedramcore_master_p3_rddata;
end
end
always @(*) begin
soc_litedramcore_master_p2_wrdata_en = 1'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p2_wrdata_en = soc_litedramcore_slave_p2_wrdata_en;
end else begin
soc_litedramcore_master_p2_wrdata_en = soc_litedramcore_inti_p2_wrdata_en;
end
end
always @(*) begin
soc_litedramcore_inti_p3_rddata_valid = 1'd0;
if (soc_litedramcore_sel) begin
end else begin
soc_litedramcore_inti_p3_rddata_valid = soc_litedramcore_master_p3_rddata_valid;
end
end
always @(*) begin
soc_litedramcore_master_p2_wrdata_mask = 4'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p2_wrdata_mask = soc_litedramcore_slave_p2_wrdata_mask;
end else begin
soc_litedramcore_master_p2_wrdata_mask = soc_litedramcore_inti_p2_wrdata_mask;
end
end
always @(*) begin
soc_litedramcore_master_p2_rddata_en = 1'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p2_rddata_en = soc_litedramcore_slave_p2_rddata_en;
end else begin
soc_litedramcore_master_p2_rddata_en = soc_litedramcore_inti_p2_rddata_en;
end
end
always @(*) begin
soc_litedramcore_master_p3_address = 14'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p3_address = soc_litedramcore_slave_p3_address;
end else begin
soc_litedramcore_master_p3_address = soc_litedramcore_inti_p3_address;
end
end
always @(*) begin
soc_litedramcore_master_p3_bank = 3'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p3_bank = soc_litedramcore_slave_p3_bank;
end else begin
soc_litedramcore_master_p3_bank = soc_litedramcore_inti_p3_bank;
end
end
always @(*) begin
soc_litedramcore_master_p3_cas_n = 1'd1;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p3_cas_n = soc_litedramcore_slave_p3_cas_n;
end else begin
soc_litedramcore_master_p3_cas_n = soc_litedramcore_inti_p3_cas_n;
end
end
always @(*) begin
soc_litedramcore_master_p3_cs_n = 1'd1;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p3_cs_n = soc_litedramcore_slave_p3_cs_n;
end else begin
soc_litedramcore_master_p3_cs_n = soc_litedramcore_inti_p3_cs_n;
end
end
always @(*) begin
soc_litedramcore_master_p3_ras_n = 1'd1;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p3_ras_n = soc_litedramcore_slave_p3_ras_n;
end else begin
soc_litedramcore_master_p3_ras_n = soc_litedramcore_inti_p3_ras_n;
end
end
always @(*) begin
soc_litedramcore_slave_p3_rddata = 32'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_slave_p3_rddata = soc_litedramcore_master_p3_rddata;
end else begin
end
end
always @(*) begin
soc_litedramcore_master_p3_we_n = 1'd1;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p3_we_n = soc_litedramcore_slave_p3_we_n;
end else begin
soc_litedramcore_master_p3_we_n = soc_litedramcore_inti_p3_we_n;
end
end
always @(*) begin
soc_litedramcore_slave_p3_rddata_valid = 1'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_slave_p3_rddata_valid = soc_litedramcore_master_p3_rddata_valid;
end else begin
end
end
always @(*) begin
soc_litedramcore_master_p3_cke = 1'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p3_cke = soc_litedramcore_slave_p3_cke;
end else begin
soc_litedramcore_master_p3_cke = soc_litedramcore_inti_p3_cke;
end
end
always @(*) begin
soc_litedramcore_master_p3_odt = 1'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p3_odt = soc_litedramcore_slave_p3_odt;
end else begin
soc_litedramcore_master_p3_odt = soc_litedramcore_inti_p3_odt;
end
end
always @(*) begin
soc_litedramcore_master_p3_reset_n = 1'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p3_reset_n = soc_litedramcore_slave_p3_reset_n;
end else begin
soc_litedramcore_master_p3_reset_n = soc_litedramcore_inti_p3_reset_n;
end
end
always @(*) begin
soc_litedramcore_master_p3_act_n = 1'd1;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p3_act_n = soc_litedramcore_slave_p3_act_n;
end else begin
soc_litedramcore_master_p3_act_n = soc_litedramcore_inti_p3_act_n;
end
end
always @(*) begin
soc_litedramcore_master_p3_wrdata = 32'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p3_wrdata = soc_litedramcore_slave_p3_wrdata;
end else begin
soc_litedramcore_master_p3_wrdata = soc_litedramcore_inti_p3_wrdata;
end
end
always @(*) begin
soc_litedramcore_inti_p0_rddata = 32'd0;
if (soc_litedramcore_sel) begin
end else begin
soc_litedramcore_inti_p0_rddata = soc_litedramcore_master_p0_rddata;
end
end
always @(*) begin
soc_litedramcore_master_p3_wrdata_en = 1'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p3_wrdata_en = soc_litedramcore_slave_p3_wrdata_en;
end else begin
soc_litedramcore_master_p3_wrdata_en = soc_litedramcore_inti_p3_wrdata_en;
end
end
always @(*) begin
soc_litedramcore_inti_p0_rddata_valid = 1'd0;
if (soc_litedramcore_sel) begin
end else begin
soc_litedramcore_inti_p0_rddata_valid = soc_litedramcore_master_p0_rddata_valid;
end
end
always @(*) begin
soc_litedramcore_master_p3_wrdata_mask = 4'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p3_wrdata_mask = soc_litedramcore_slave_p3_wrdata_mask;
end else begin
soc_litedramcore_master_p3_wrdata_mask = soc_litedramcore_inti_p3_wrdata_mask;
end
end
always @(*) begin
soc_litedramcore_master_p3_rddata_en = 1'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p3_rddata_en = soc_litedramcore_slave_p3_rddata_en;
end else begin
soc_litedramcore_master_p3_rddata_en = soc_litedramcore_inti_p3_rddata_en;
end
end
always @(*) begin
soc_litedramcore_master_p0_address = 14'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p0_address = soc_litedramcore_slave_p0_address;
end else begin
soc_litedramcore_master_p0_address = soc_litedramcore_inti_p0_address;
end
end
always @(*) begin
soc_litedramcore_master_p0_bank = 3'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p0_bank = soc_litedramcore_slave_p0_bank;
end else begin
soc_litedramcore_master_p0_bank = soc_litedramcore_inti_p0_bank;
end
end
always @(*) begin
soc_litedramcore_master_p0_cas_n = 1'd1;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p0_cas_n = soc_litedramcore_slave_p0_cas_n;
end else begin
soc_litedramcore_master_p0_cas_n = soc_litedramcore_inti_p0_cas_n;
end
end
always @(*) begin
soc_litedramcore_master_p0_cs_n = 1'd1;
if (soc_litedramcore_sel) begin
soc_litedramcore_master_p0_cs_n = soc_litedramcore_slave_p0_cs_n;
end else begin
soc_litedramcore_master_p0_cs_n = soc_litedramcore_inti_p0_cs_n;
end
end
always @(*) begin
soc_litedramcore_slave_p0_rddata = 32'd0;
if (soc_litedramcore_sel) begin
soc_litedramcore_slave_p0_rddata = soc_litedramcore_master_p0_rddata;
end else begin
end
end
assign soc_litedramcore_inti_p0_cke = soc_litedramcore_cke;
assign soc_litedramcore_inti_p1_cke = soc_litedramcore_cke;
assign soc_litedramcore_inti_p2_cke = soc_litedramcore_cke;
assign soc_litedramcore_inti_p3_cke = soc_litedramcore_cke;
assign soc_litedramcore_inti_p0_odt = soc_litedramcore_odt;
assign soc_litedramcore_inti_p1_odt = soc_litedramcore_odt;
assign soc_litedramcore_inti_p2_odt = soc_litedramcore_odt;
assign soc_litedramcore_inti_p3_odt = soc_litedramcore_odt;
assign soc_litedramcore_inti_p0_reset_n = soc_litedramcore_reset_n;
assign soc_litedramcore_inti_p1_reset_n = soc_litedramcore_reset_n;
assign soc_litedramcore_inti_p2_reset_n = soc_litedramcore_reset_n;
assign soc_litedramcore_inti_p3_reset_n = soc_litedramcore_reset_n;
always @(*) begin
soc_litedramcore_inti_p0_we_n = 1'd1;
if (soc_litedramcore_phaseinjector0_command_issue_re) begin
soc_litedramcore_inti_p0_we_n = (~soc_litedramcore_phaseinjector0_command_storage[1]);
end else begin
soc_litedramcore_inti_p0_we_n = 1'd1;
end
end
always @(*) begin
soc_litedramcore_inti_p0_cas_n = 1'd1;
if (soc_litedramcore_phaseinjector0_command_issue_re) begin
soc_litedramcore_inti_p0_cas_n = (~soc_litedramcore_phaseinjector0_command_storage[2]);
end else begin
soc_litedramcore_inti_p0_cas_n = 1'd1;
end
end
always @(*) begin
soc_litedramcore_inti_p0_cs_n = 1'd1;
if (soc_litedramcore_phaseinjector0_command_issue_re) begin
soc_litedramcore_inti_p0_cs_n = {1{(~soc_litedramcore_phaseinjector0_command_storage[0])}};
end else begin
soc_litedramcore_inti_p0_cs_n = {1{1'd1}};
end
end
always @(*) begin
soc_litedramcore_inti_p0_ras_n = 1'd1;
if (soc_litedramcore_phaseinjector0_command_issue_re) begin
soc_litedramcore_inti_p0_ras_n = (~soc_litedramcore_phaseinjector0_command_storage[3]);
end else begin
soc_litedramcore_inti_p0_ras_n = 1'd1;
end
end
assign soc_litedramcore_inti_p0_address = soc_litedramcore_phaseinjector0_address_storage;
assign soc_litedramcore_inti_p0_bank = soc_litedramcore_phaseinjector0_baddress_storage;
assign soc_litedramcore_inti_p0_wrdata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_command_storage[4]);
assign soc_litedramcore_inti_p0_rddata_en = (soc_litedramcore_phaseinjector0_command_issue_re & soc_litedramcore_phaseinjector0_command_storage[5]);
assign soc_litedramcore_inti_p0_wrdata = soc_litedramcore_phaseinjector0_wrdata_storage;
assign soc_litedramcore_inti_p0_wrdata_mask = 1'd0;
always @(*) begin
soc_litedramcore_inti_p1_we_n = 1'd1;
if (soc_litedramcore_phaseinjector1_command_issue_re) begin
soc_litedramcore_inti_p1_we_n = (~soc_litedramcore_phaseinjector1_command_storage[1]);
end else begin
soc_litedramcore_inti_p1_we_n = 1'd1;
end
end
always @(*) begin
soc_litedramcore_inti_p1_cas_n = 1'd1;
if (soc_litedramcore_phaseinjector1_command_issue_re) begin
soc_litedramcore_inti_p1_cas_n = (~soc_litedramcore_phaseinjector1_command_storage[2]);
end else begin
soc_litedramcore_inti_p1_cas_n = 1'd1;
end
end
always @(*) begin
soc_litedramcore_inti_p1_cs_n = 1'd1;
if (soc_litedramcore_phaseinjector1_command_issue_re) begin
soc_litedramcore_inti_p1_cs_n = {1{(~soc_litedramcore_phaseinjector1_command_storage[0])}};
end else begin
soc_litedramcore_inti_p1_cs_n = {1{1'd1}};
end
end
always @(*) begin
soc_litedramcore_inti_p1_ras_n = 1'd1;
if (soc_litedramcore_phaseinjector1_command_issue_re) begin
soc_litedramcore_inti_p1_ras_n = (~soc_litedramcore_phaseinjector1_command_storage[3]);
end else begin
soc_litedramcore_inti_p1_ras_n = 1'd1;
end
end
assign soc_litedramcore_inti_p1_address = soc_litedramcore_phaseinjector1_address_storage;
assign soc_litedramcore_inti_p1_bank = soc_litedramcore_phaseinjector1_baddress_storage;
assign soc_litedramcore_inti_p1_wrdata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_command_storage[4]);
assign soc_litedramcore_inti_p1_rddata_en = (soc_litedramcore_phaseinjector1_command_issue_re & soc_litedramcore_phaseinjector1_command_storage[5]);
assign soc_litedramcore_inti_p1_wrdata = soc_litedramcore_phaseinjector1_wrdata_storage;
assign soc_litedramcore_inti_p1_wrdata_mask = 1'd0;
always @(*) begin
soc_litedramcore_inti_p2_we_n = 1'd1;
if (soc_litedramcore_phaseinjector2_command_issue_re) begin
soc_litedramcore_inti_p2_we_n = (~soc_litedramcore_phaseinjector2_command_storage[1]);
end else begin
soc_litedramcore_inti_p2_we_n = 1'd1;
end
end
always @(*) begin
soc_litedramcore_inti_p2_cas_n = 1'd1;
if (soc_litedramcore_phaseinjector2_command_issue_re) begin
soc_litedramcore_inti_p2_cas_n = (~soc_litedramcore_phaseinjector2_command_storage[2]);
end else begin
soc_litedramcore_inti_p2_cas_n = 1'd1;
end
end
always @(*) begin
soc_litedramcore_inti_p2_cs_n = 1'd1;
if (soc_litedramcore_phaseinjector2_command_issue_re) begin
soc_litedramcore_inti_p2_cs_n = {1{(~soc_litedramcore_phaseinjector2_command_storage[0])}};
end else begin
soc_litedramcore_inti_p2_cs_n = {1{1'd1}};
end
end
always @(*) begin
soc_litedramcore_inti_p2_ras_n = 1'd1;
if (soc_litedramcore_phaseinjector2_command_issue_re) begin
soc_litedramcore_inti_p2_ras_n = (~soc_litedramcore_phaseinjector2_command_storage[3]);
end else begin
soc_litedramcore_inti_p2_ras_n = 1'd1;
end
end
assign soc_litedramcore_inti_p2_address = soc_litedramcore_phaseinjector2_address_storage;
assign soc_litedramcore_inti_p2_bank = soc_litedramcore_phaseinjector2_baddress_storage;
assign soc_litedramcore_inti_p2_wrdata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_command_storage[4]);
assign soc_litedramcore_inti_p2_rddata_en = (soc_litedramcore_phaseinjector2_command_issue_re & soc_litedramcore_phaseinjector2_command_storage[5]);
assign soc_litedramcore_inti_p2_wrdata = soc_litedramcore_phaseinjector2_wrdata_storage;
assign soc_litedramcore_inti_p2_wrdata_mask = 1'd0;
always @(*) begin
soc_litedramcore_inti_p3_we_n = 1'd1;
if (soc_litedramcore_phaseinjector3_command_issue_re) begin
soc_litedramcore_inti_p3_we_n = (~soc_litedramcore_phaseinjector3_command_storage[1]);
end else begin
soc_litedramcore_inti_p3_we_n = 1'd1;
end
end
always @(*) begin
soc_litedramcore_inti_p3_cas_n = 1'd1;
if (soc_litedramcore_phaseinjector3_command_issue_re) begin
soc_litedramcore_inti_p3_cas_n = (~soc_litedramcore_phaseinjector3_command_storage[2]);
end else begin
soc_litedramcore_inti_p3_cas_n = 1'd1;
end
end
always @(*) begin
soc_litedramcore_inti_p3_cs_n = 1'd1;
if (soc_litedramcore_phaseinjector3_command_issue_re) begin
soc_litedramcore_inti_p3_cs_n = {1{(~soc_litedramcore_phaseinjector3_command_storage[0])}};
end else begin
soc_litedramcore_inti_p3_cs_n = {1{1'd1}};
end
end
always @(*) begin
soc_litedramcore_inti_p3_ras_n = 1'd1;
if (soc_litedramcore_phaseinjector3_command_issue_re) begin
soc_litedramcore_inti_p3_ras_n = (~soc_litedramcore_phaseinjector3_command_storage[3]);
end else begin
soc_litedramcore_inti_p3_ras_n = 1'd1;
end
end
assign soc_litedramcore_inti_p3_address = soc_litedramcore_phaseinjector3_address_storage;
assign soc_litedramcore_inti_p3_bank = soc_litedramcore_phaseinjector3_baddress_storage;
assign soc_litedramcore_inti_p3_wrdata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_command_storage[4]);
assign soc_litedramcore_inti_p3_rddata_en = (soc_litedramcore_phaseinjector3_command_issue_re & soc_litedramcore_phaseinjector3_command_storage[5]);
assign soc_litedramcore_inti_p3_wrdata = soc_litedramcore_phaseinjector3_wrdata_storage;
assign soc_litedramcore_inti_p3_wrdata_mask = 1'd0;
assign soc_litedramcore_bankmachine0_req_valid = soc_litedramcore_interface_bank0_valid;
assign soc_litedramcore_interface_bank0_ready = soc_litedramcore_bankmachine0_req_ready;
assign soc_litedramcore_bankmachine0_req_we = soc_litedramcore_interface_bank0_we;
assign soc_litedramcore_bankmachine0_req_addr = soc_litedramcore_interface_bank0_addr;
assign soc_litedramcore_interface_bank0_lock = soc_litedramcore_bankmachine0_req_lock;
assign soc_litedramcore_interface_bank0_wdata_ready = soc_litedramcore_bankmachine0_req_wdata_ready;
assign soc_litedramcore_interface_bank0_rdata_valid = soc_litedramcore_bankmachine0_req_rdata_valid;
assign soc_litedramcore_bankmachine1_req_valid = soc_litedramcore_interface_bank1_valid;
assign soc_litedramcore_interface_bank1_ready = soc_litedramcore_bankmachine1_req_ready;
assign soc_litedramcore_bankmachine1_req_we = soc_litedramcore_interface_bank1_we;
assign soc_litedramcore_bankmachine1_req_addr = soc_litedramcore_interface_bank1_addr;
assign soc_litedramcore_interface_bank1_lock = soc_litedramcore_bankmachine1_req_lock;
assign soc_litedramcore_interface_bank1_wdata_ready = soc_litedramcore_bankmachine1_req_wdata_ready;
assign soc_litedramcore_interface_bank1_rdata_valid = soc_litedramcore_bankmachine1_req_rdata_valid;
assign soc_litedramcore_bankmachine2_req_valid = soc_litedramcore_interface_bank2_valid;
assign soc_litedramcore_interface_bank2_ready = soc_litedramcore_bankmachine2_req_ready;
assign soc_litedramcore_bankmachine2_req_we = soc_litedramcore_interface_bank2_we;
assign soc_litedramcore_bankmachine2_req_addr = soc_litedramcore_interface_bank2_addr;
assign soc_litedramcore_interface_bank2_lock = soc_litedramcore_bankmachine2_req_lock;
assign soc_litedramcore_interface_bank2_wdata_ready = soc_litedramcore_bankmachine2_req_wdata_ready;
assign soc_litedramcore_interface_bank2_rdata_valid = soc_litedramcore_bankmachine2_req_rdata_valid;
assign soc_litedramcore_bankmachine3_req_valid = soc_litedramcore_interface_bank3_valid;
assign soc_litedramcore_interface_bank3_ready = soc_litedramcore_bankmachine3_req_ready;
assign soc_litedramcore_bankmachine3_req_we = soc_litedramcore_interface_bank3_we;
assign soc_litedramcore_bankmachine3_req_addr = soc_litedramcore_interface_bank3_addr;
assign soc_litedramcore_interface_bank3_lock = soc_litedramcore_bankmachine3_req_lock;
assign soc_litedramcore_interface_bank3_wdata_ready = soc_litedramcore_bankmachine3_req_wdata_ready;
assign soc_litedramcore_interface_bank3_rdata_valid = soc_litedramcore_bankmachine3_req_rdata_valid;
assign soc_litedramcore_bankmachine4_req_valid = soc_litedramcore_interface_bank4_valid;
assign soc_litedramcore_interface_bank4_ready = soc_litedramcore_bankmachine4_req_ready;
assign soc_litedramcore_bankmachine4_req_we = soc_litedramcore_interface_bank4_we;
assign soc_litedramcore_bankmachine4_req_addr = soc_litedramcore_interface_bank4_addr;
assign soc_litedramcore_interface_bank4_lock = soc_litedramcore_bankmachine4_req_lock;
assign soc_litedramcore_interface_bank4_wdata_ready = soc_litedramcore_bankmachine4_req_wdata_ready;
assign soc_litedramcore_interface_bank4_rdata_valid = soc_litedramcore_bankmachine4_req_rdata_valid;
assign soc_litedramcore_bankmachine5_req_valid = soc_litedramcore_interface_bank5_valid;
assign soc_litedramcore_interface_bank5_ready = soc_litedramcore_bankmachine5_req_ready;
assign soc_litedramcore_bankmachine5_req_we = soc_litedramcore_interface_bank5_we;
assign soc_litedramcore_bankmachine5_req_addr = soc_litedramcore_interface_bank5_addr;
assign soc_litedramcore_interface_bank5_lock = soc_litedramcore_bankmachine5_req_lock;
assign soc_litedramcore_interface_bank5_wdata_ready = soc_litedramcore_bankmachine5_req_wdata_ready;
assign soc_litedramcore_interface_bank5_rdata_valid = soc_litedramcore_bankmachine5_req_rdata_valid;
assign soc_litedramcore_bankmachine6_req_valid = soc_litedramcore_interface_bank6_valid;
assign soc_litedramcore_interface_bank6_ready = soc_litedramcore_bankmachine6_req_ready;
assign soc_litedramcore_bankmachine6_req_we = soc_litedramcore_interface_bank6_we;
assign soc_litedramcore_bankmachine6_req_addr = soc_litedramcore_interface_bank6_addr;
assign soc_litedramcore_interface_bank6_lock = soc_litedramcore_bankmachine6_req_lock;
assign soc_litedramcore_interface_bank6_wdata_ready = soc_litedramcore_bankmachine6_req_wdata_ready;
assign soc_litedramcore_interface_bank6_rdata_valid = soc_litedramcore_bankmachine6_req_rdata_valid;
assign soc_litedramcore_bankmachine7_req_valid = soc_litedramcore_interface_bank7_valid;
assign soc_litedramcore_interface_bank7_ready = soc_litedramcore_bankmachine7_req_ready;
assign soc_litedramcore_bankmachine7_req_we = soc_litedramcore_interface_bank7_we;
assign soc_litedramcore_bankmachine7_req_addr = soc_litedramcore_interface_bank7_addr;
assign soc_litedramcore_interface_bank7_lock = soc_litedramcore_bankmachine7_req_lock;
assign soc_litedramcore_interface_bank7_wdata_ready = soc_litedramcore_bankmachine7_req_wdata_ready;
assign soc_litedramcore_interface_bank7_rdata_valid = soc_litedramcore_bankmachine7_req_rdata_valid;
assign soc_litedramcore_timer_wait = (~soc_litedramcore_timer_done0);
assign soc_litedramcore_postponer_req_i = soc_litedramcore_timer_done0;
assign soc_litedramcore_wants_refresh = soc_litedramcore_postponer_req_o;
assign soc_litedramcore_wants_zqcs = soc_litedramcore_zqcs_timer_done0;
assign soc_litedramcore_zqcs_timer_wait = (~soc_litedramcore_zqcs_executer_done);
assign soc_litedramcore_timer_done1 = (soc_litedramcore_timer_count1 == 1'd0);
assign soc_litedramcore_timer_done0 = soc_litedramcore_timer_done1;
assign soc_litedramcore_timer_count0 = soc_litedramcore_timer_count1;
assign soc_litedramcore_sequencer_start1 = (soc_litedramcore_sequencer_start0 | (soc_litedramcore_sequencer_count != 1'd0));
assign soc_litedramcore_sequencer_done0 = (soc_litedramcore_sequencer_done1 & (soc_litedramcore_sequencer_count == 1'd0));
assign soc_litedramcore_zqcs_timer_done1 = (soc_litedramcore_zqcs_timer_count1 == 1'd0);
assign soc_litedramcore_zqcs_timer_done0 = soc_litedramcore_zqcs_timer_done1;
assign soc_litedramcore_zqcs_timer_count0 = soc_litedramcore_zqcs_timer_count1;
always @(*) begin
refresher_next_state = 2'd0;
refresher_next_state = refresher_state;
case (refresher_state)
1'd1: begin
if (soc_litedramcore_cmd_ready) begin
refresher_next_state = 2'd2;
end
end
2'd2: begin
if (soc_litedramcore_sequencer_done0) begin
if (soc_litedramcore_wants_zqcs) begin
refresher_next_state = 2'd3;
end else begin
refresher_next_state = 1'd0;
end
end
end
2'd3: begin
if (soc_litedramcore_zqcs_executer_done) begin
refresher_next_state = 1'd0;
end
end
default: begin
if (1'd1) begin
if (soc_litedramcore_wants_refresh) begin
refresher_next_state = 1'd1;
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_sequencer_start0 = 1'd0;
case (refresher_state)
1'd1: begin
if (soc_litedramcore_cmd_ready) begin
soc_litedramcore_sequencer_start0 = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_cmd_valid = 1'd0;
case (refresher_state)
1'd1: begin
soc_litedramcore_cmd_valid = 1'd1;
end
2'd2: begin
soc_litedramcore_cmd_valid = 1'd1;
if (soc_litedramcore_sequencer_done0) begin
if (soc_litedramcore_wants_zqcs) begin
end else begin
soc_litedramcore_cmd_valid = 1'd0;
end
end
end
2'd3: begin
soc_litedramcore_cmd_valid = 1'd1;
if (soc_litedramcore_zqcs_executer_done) begin
soc_litedramcore_cmd_valid = 1'd0;
end
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_zqcs_executer_start = 1'd0;
case (refresher_state)
1'd1: begin
end
2'd2: begin
if (soc_litedramcore_sequencer_done0) begin
if (soc_litedramcore_wants_zqcs) begin
soc_litedramcore_zqcs_executer_start = 1'd1;
end else begin
end
end
end
2'd3: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_cmd_last = 1'd0;
case (refresher_state)
1'd1: begin
end
2'd2: begin
if (soc_litedramcore_sequencer_done0) begin
if (soc_litedramcore_wants_zqcs) begin
end else begin
soc_litedramcore_cmd_last = 1'd1;
end
end
end
2'd3: begin
if (soc_litedramcore_zqcs_executer_done) begin
soc_litedramcore_cmd_last = 1'd1;
end
end
default: begin
end
endcase
end
assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine0_req_valid;
assign soc_litedramcore_bankmachine0_req_ready = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine0_req_we;
assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine0_req_addr;
assign soc_litedramcore_bankmachine0_cmd_buffer_sink_valid = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine0_cmd_buffer_sink_ready;
assign soc_litedramcore_bankmachine0_cmd_buffer_sink_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
assign soc_litedramcore_bankmachine0_cmd_buffer_sink_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
assign soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
assign soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
assign soc_litedramcore_bankmachine0_cmd_buffer_source_ready = (soc_litedramcore_bankmachine0_req_wdata_ready | soc_litedramcore_bankmachine0_req_rdata_valid);
assign soc_litedramcore_bankmachine0_req_lock = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine0_cmd_buffer_source_valid);
assign soc_litedramcore_bankmachine0_row_hit = (soc_litedramcore_bankmachine0_row == soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]);
assign soc_litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
always @(*) begin
soc_litedramcore_bankmachine0_cmd_payload_a = 14'd0;
if (soc_litedramcore_bankmachine0_row_col_n_addr_sel) begin
soc_litedramcore_bankmachine0_cmd_payload_a = soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
end else begin
soc_litedramcore_bankmachine0_cmd_payload_a = ((soc_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
end
assign soc_litedramcore_bankmachine0_twtpcon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_cmd_payload_is_write);
assign soc_litedramcore_bankmachine0_trccon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open);
assign soc_litedramcore_bankmachine0_trascon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open);
always @(*) begin
soc_litedramcore_bankmachine0_auto_precharge = 1'd0;
if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin
soc_litedramcore_bankmachine0_auto_precharge = (soc_litedramcore_bankmachine0_row_close == 1'd0);
end
end
end
assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
always @(*) begin
soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
end else begin
soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
end
end
assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
assign soc_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready);
always @(*) begin
bankmachine0_next_state = 4'd0;
bankmachine0_next_state = bankmachine0_state;
case (bankmachine0_state)
1'd1: begin
if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
if (soc_litedramcore_bankmachine0_cmd_ready) begin
bankmachine0_next_state = 3'd5;
end
end
end
2'd2: begin
if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
bankmachine0_next_state = 3'd5;
end
end
2'd3: begin
if (soc_litedramcore_bankmachine0_trccon_ready) begin
if (soc_litedramcore_bankmachine0_cmd_ready) begin
bankmachine0_next_state = 3'd7;
end
end
end
3'd4: begin
if ((~soc_litedramcore_bankmachine0_refresh_req)) begin
bankmachine0_next_state = 1'd0;
end
end
3'd5: begin
bankmachine0_next_state = 3'd6;
end
3'd6: begin
bankmachine0_next_state = 2'd3;
end
3'd7: begin
bankmachine0_next_state = 4'd8;
end
4'd8: begin
bankmachine0_next_state = 1'd0;
end
default: begin
if (soc_litedramcore_bankmachine0_refresh_req) begin
bankmachine0_next_state = 3'd4;
end else begin
if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine0_row_opened) begin
if (soc_litedramcore_bankmachine0_row_hit) begin
if ((soc_litedramcore_bankmachine0_cmd_ready & soc_litedramcore_bankmachine0_auto_precharge)) begin
bankmachine0_next_state = 2'd2;
end
end else begin
bankmachine0_next_state = 1'd1;
end
end else begin
bankmachine0_next_state = 2'd3;
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
case (bankmachine0_state)
1'd1: begin
if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
soc_litedramcore_bankmachine0_cmd_payload_we = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine0_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine0_row_opened) begin
if (soc_litedramcore_bankmachine0_row_hit) begin
if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
soc_litedramcore_bankmachine0_cmd_payload_we = 1'd1;
end else begin
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
case (bankmachine0_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine0_trccon_ready) begin
soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
case (bankmachine0_state)
1'd1: begin
if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine0_trccon_ready) begin
soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1;
end
end
3'd4: begin
soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1;
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
case (bankmachine0_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine0_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine0_row_opened) begin
if (soc_litedramcore_bankmachine0_row_hit) begin
if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
end else begin
soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd1;
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
case (bankmachine0_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine0_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine0_row_opened) begin
if (soc_litedramcore_bankmachine0_row_hit) begin
if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd1;
end else begin
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
case (bankmachine0_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine0_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine0_row_opened) begin
if (soc_litedramcore_bankmachine0_row_hit) begin
if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
soc_litedramcore_bankmachine0_req_wdata_ready = soc_litedramcore_bankmachine0_cmd_ready;
end else begin
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
case (bankmachine0_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine0_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine0_row_opened) begin
if (soc_litedramcore_bankmachine0_row_hit) begin
if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
end else begin
soc_litedramcore_bankmachine0_req_rdata_valid = soc_litedramcore_bankmachine0_cmd_ready;
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine0_refresh_gnt = 1'd0;
case (bankmachine0_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
if (soc_litedramcore_bankmachine0_twtpcon_ready) begin
soc_litedramcore_bankmachine0_refresh_gnt = 1'd1;
end
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine0_cmd_valid = 1'd0;
case (bankmachine0_state)
1'd1: begin
if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
soc_litedramcore_bankmachine0_cmd_valid = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine0_trccon_ready) begin
soc_litedramcore_bankmachine0_cmd_valid = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine0_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine0_row_opened) begin
if (soc_litedramcore_bankmachine0_row_hit) begin
soc_litedramcore_bankmachine0_cmd_valid = 1'd1;
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine0_row_open = 1'd0;
case (bankmachine0_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine0_trccon_ready) begin
soc_litedramcore_bankmachine0_row_open = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine0_row_close = 1'd0;
case (bankmachine0_state)
1'd1: begin
soc_litedramcore_bankmachine0_row_close = 1'd1;
end
2'd2: begin
soc_litedramcore_bankmachine0_row_close = 1'd1;
end
2'd3: begin
end
3'd4: begin
soc_litedramcore_bankmachine0_row_close = 1'd1;
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
case (bankmachine0_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine0_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine0_row_opened) begin
if (soc_litedramcore_bankmachine0_row_hit) begin
soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd1;
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
case (bankmachine0_state)
1'd1: begin
if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine0_trccon_ready) begin
soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine1_req_valid;
assign soc_litedramcore_bankmachine1_req_ready = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine1_req_we;
assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine1_req_addr;
assign soc_litedramcore_bankmachine1_cmd_buffer_sink_valid = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine1_cmd_buffer_sink_ready;
assign soc_litedramcore_bankmachine1_cmd_buffer_sink_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
assign soc_litedramcore_bankmachine1_cmd_buffer_sink_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
assign soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
assign soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
assign soc_litedramcore_bankmachine1_cmd_buffer_source_ready = (soc_litedramcore_bankmachine1_req_wdata_ready | soc_litedramcore_bankmachine1_req_rdata_valid);
assign soc_litedramcore_bankmachine1_req_lock = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine1_cmd_buffer_source_valid);
assign soc_litedramcore_bankmachine1_row_hit = (soc_litedramcore_bankmachine1_row == soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]);
assign soc_litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
always @(*) begin
soc_litedramcore_bankmachine1_cmd_payload_a = 14'd0;
if (soc_litedramcore_bankmachine1_row_col_n_addr_sel) begin
soc_litedramcore_bankmachine1_cmd_payload_a = soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
end else begin
soc_litedramcore_bankmachine1_cmd_payload_a = ((soc_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
end
assign soc_litedramcore_bankmachine1_twtpcon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_cmd_payload_is_write);
assign soc_litedramcore_bankmachine1_trccon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open);
assign soc_litedramcore_bankmachine1_trascon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open);
always @(*) begin
soc_litedramcore_bankmachine1_auto_precharge = 1'd0;
if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin
soc_litedramcore_bankmachine1_auto_precharge = (soc_litedramcore_bankmachine1_row_close == 1'd0);
end
end
end
assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
always @(*) begin
soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
end else begin
soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
end
end
assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
assign soc_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready);
always @(*) begin
bankmachine1_next_state = 4'd0;
bankmachine1_next_state = bankmachine1_state;
case (bankmachine1_state)
1'd1: begin
if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
if (soc_litedramcore_bankmachine1_cmd_ready) begin
bankmachine1_next_state = 3'd5;
end
end
end
2'd2: begin
if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
bankmachine1_next_state = 3'd5;
end
end
2'd3: begin
if (soc_litedramcore_bankmachine1_trccon_ready) begin
if (soc_litedramcore_bankmachine1_cmd_ready) begin
bankmachine1_next_state = 3'd7;
end
end
end
3'd4: begin
if ((~soc_litedramcore_bankmachine1_refresh_req)) begin
bankmachine1_next_state = 1'd0;
end
end
3'd5: begin
bankmachine1_next_state = 3'd6;
end
3'd6: begin
bankmachine1_next_state = 2'd3;
end
3'd7: begin
bankmachine1_next_state = 4'd8;
end
4'd8: begin
bankmachine1_next_state = 1'd0;
end
default: begin
if (soc_litedramcore_bankmachine1_refresh_req) begin
bankmachine1_next_state = 3'd4;
end else begin
if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine1_row_opened) begin
if (soc_litedramcore_bankmachine1_row_hit) begin
if ((soc_litedramcore_bankmachine1_cmd_ready & soc_litedramcore_bankmachine1_auto_precharge)) begin
bankmachine1_next_state = 2'd2;
end
end else begin
bankmachine1_next_state = 1'd1;
end
end else begin
bankmachine1_next_state = 2'd3;
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
case (bankmachine1_state)
1'd1: begin
if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
soc_litedramcore_bankmachine1_cmd_payload_we = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine1_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine1_row_opened) begin
if (soc_litedramcore_bankmachine1_row_hit) begin
if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
soc_litedramcore_bankmachine1_cmd_payload_we = 1'd1;
end else begin
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
case (bankmachine1_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine1_trccon_ready) begin
soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
case (bankmachine1_state)
1'd1: begin
if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine1_trccon_ready) begin
soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1;
end
end
3'd4: begin
soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1;
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
case (bankmachine1_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine1_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine1_row_opened) begin
if (soc_litedramcore_bankmachine1_row_hit) begin
if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
end else begin
soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd1;
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
case (bankmachine1_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine1_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine1_row_opened) begin
if (soc_litedramcore_bankmachine1_row_hit) begin
if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd1;
end else begin
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
case (bankmachine1_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine1_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine1_row_opened) begin
if (soc_litedramcore_bankmachine1_row_hit) begin
if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
soc_litedramcore_bankmachine1_req_wdata_ready = soc_litedramcore_bankmachine1_cmd_ready;
end else begin
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
case (bankmachine1_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine1_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine1_row_opened) begin
if (soc_litedramcore_bankmachine1_row_hit) begin
if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
end else begin
soc_litedramcore_bankmachine1_req_rdata_valid = soc_litedramcore_bankmachine1_cmd_ready;
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine1_refresh_gnt = 1'd0;
case (bankmachine1_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
if (soc_litedramcore_bankmachine1_twtpcon_ready) begin
soc_litedramcore_bankmachine1_refresh_gnt = 1'd1;
end
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine1_cmd_valid = 1'd0;
case (bankmachine1_state)
1'd1: begin
if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
soc_litedramcore_bankmachine1_cmd_valid = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine1_trccon_ready) begin
soc_litedramcore_bankmachine1_cmd_valid = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine1_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine1_row_opened) begin
if (soc_litedramcore_bankmachine1_row_hit) begin
soc_litedramcore_bankmachine1_cmd_valid = 1'd1;
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine1_row_open = 1'd0;
case (bankmachine1_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine1_trccon_ready) begin
soc_litedramcore_bankmachine1_row_open = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine1_row_close = 1'd0;
case (bankmachine1_state)
1'd1: begin
soc_litedramcore_bankmachine1_row_close = 1'd1;
end
2'd2: begin
soc_litedramcore_bankmachine1_row_close = 1'd1;
end
2'd3: begin
end
3'd4: begin
soc_litedramcore_bankmachine1_row_close = 1'd1;
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
case (bankmachine1_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine1_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine1_row_opened) begin
if (soc_litedramcore_bankmachine1_row_hit) begin
soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd1;
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
case (bankmachine1_state)
1'd1: begin
if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine1_trccon_ready) begin
soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine2_req_valid;
assign soc_litedramcore_bankmachine2_req_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine2_req_we;
assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine2_req_addr;
assign soc_litedramcore_bankmachine2_cmd_buffer_sink_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine2_cmd_buffer_sink_ready;
assign soc_litedramcore_bankmachine2_cmd_buffer_sink_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
assign soc_litedramcore_bankmachine2_cmd_buffer_sink_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
assign soc_litedramcore_bankmachine2_cmd_buffer_source_ready = (soc_litedramcore_bankmachine2_req_wdata_ready | soc_litedramcore_bankmachine2_req_rdata_valid);
assign soc_litedramcore_bankmachine2_req_lock = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine2_cmd_buffer_source_valid);
assign soc_litedramcore_bankmachine2_row_hit = (soc_litedramcore_bankmachine2_row == soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]);
assign soc_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
always @(*) begin
soc_litedramcore_bankmachine2_cmd_payload_a = 14'd0;
if (soc_litedramcore_bankmachine2_row_col_n_addr_sel) begin
soc_litedramcore_bankmachine2_cmd_payload_a = soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
end else begin
soc_litedramcore_bankmachine2_cmd_payload_a = ((soc_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
end
assign soc_litedramcore_bankmachine2_twtpcon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_cmd_payload_is_write);
assign soc_litedramcore_bankmachine2_trccon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open);
assign soc_litedramcore_bankmachine2_trascon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open);
always @(*) begin
soc_litedramcore_bankmachine2_auto_precharge = 1'd0;
if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin
soc_litedramcore_bankmachine2_auto_precharge = (soc_litedramcore_bankmachine2_row_close == 1'd0);
end
end
end
assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
always @(*) begin
soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
end else begin
soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
end
end
assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
assign soc_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready);
always @(*) begin
bankmachine2_next_state = 4'd0;
bankmachine2_next_state = bankmachine2_state;
case (bankmachine2_state)
1'd1: begin
if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
if (soc_litedramcore_bankmachine2_cmd_ready) begin
bankmachine2_next_state = 3'd5;
end
end
end
2'd2: begin
if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
bankmachine2_next_state = 3'd5;
end
end
2'd3: begin
if (soc_litedramcore_bankmachine2_trccon_ready) begin
if (soc_litedramcore_bankmachine2_cmd_ready) begin
bankmachine2_next_state = 3'd7;
end
end
end
3'd4: begin
if ((~soc_litedramcore_bankmachine2_refresh_req)) begin
bankmachine2_next_state = 1'd0;
end
end
3'd5: begin
bankmachine2_next_state = 3'd6;
end
3'd6: begin
bankmachine2_next_state = 2'd3;
end
3'd7: begin
bankmachine2_next_state = 4'd8;
end
4'd8: begin
bankmachine2_next_state = 1'd0;
end
default: begin
if (soc_litedramcore_bankmachine2_refresh_req) begin
bankmachine2_next_state = 3'd4;
end else begin
if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine2_row_opened) begin
if (soc_litedramcore_bankmachine2_row_hit) begin
if ((soc_litedramcore_bankmachine2_cmd_ready & soc_litedramcore_bankmachine2_auto_precharge)) begin
bankmachine2_next_state = 2'd2;
end
end else begin
bankmachine2_next_state = 1'd1;
end
end else begin
bankmachine2_next_state = 2'd3;
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
case (bankmachine2_state)
1'd1: begin
if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
soc_litedramcore_bankmachine2_cmd_payload_we = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine2_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine2_row_opened) begin
if (soc_litedramcore_bankmachine2_row_hit) begin
if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
soc_litedramcore_bankmachine2_cmd_payload_we = 1'd1;
end else begin
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
case (bankmachine2_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine2_trccon_ready) begin
soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
case (bankmachine2_state)
1'd1: begin
if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine2_trccon_ready) begin
soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1;
end
end
3'd4: begin
soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1;
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
case (bankmachine2_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine2_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine2_row_opened) begin
if (soc_litedramcore_bankmachine2_row_hit) begin
if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
end else begin
soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd1;
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
case (bankmachine2_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine2_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine2_row_opened) begin
if (soc_litedramcore_bankmachine2_row_hit) begin
if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd1;
end else begin
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
case (bankmachine2_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine2_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine2_row_opened) begin
if (soc_litedramcore_bankmachine2_row_hit) begin
if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
soc_litedramcore_bankmachine2_req_wdata_ready = soc_litedramcore_bankmachine2_cmd_ready;
end else begin
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
case (bankmachine2_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine2_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine2_row_opened) begin
if (soc_litedramcore_bankmachine2_row_hit) begin
if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
end else begin
soc_litedramcore_bankmachine2_req_rdata_valid = soc_litedramcore_bankmachine2_cmd_ready;
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine2_refresh_gnt = 1'd0;
case (bankmachine2_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
if (soc_litedramcore_bankmachine2_twtpcon_ready) begin
soc_litedramcore_bankmachine2_refresh_gnt = 1'd1;
end
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine2_cmd_valid = 1'd0;
case (bankmachine2_state)
1'd1: begin
if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
soc_litedramcore_bankmachine2_cmd_valid = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine2_trccon_ready) begin
soc_litedramcore_bankmachine2_cmd_valid = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine2_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine2_row_opened) begin
if (soc_litedramcore_bankmachine2_row_hit) begin
soc_litedramcore_bankmachine2_cmd_valid = 1'd1;
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine2_row_open = 1'd0;
case (bankmachine2_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine2_trccon_ready) begin
soc_litedramcore_bankmachine2_row_open = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine2_row_close = 1'd0;
case (bankmachine2_state)
1'd1: begin
soc_litedramcore_bankmachine2_row_close = 1'd1;
end
2'd2: begin
soc_litedramcore_bankmachine2_row_close = 1'd1;
end
2'd3: begin
end
3'd4: begin
soc_litedramcore_bankmachine2_row_close = 1'd1;
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
case (bankmachine2_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine2_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine2_row_opened) begin
if (soc_litedramcore_bankmachine2_row_hit) begin
soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd1;
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
case (bankmachine2_state)
1'd1: begin
if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine2_trccon_ready) begin
soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine3_req_valid;
assign soc_litedramcore_bankmachine3_req_ready = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine3_req_we;
assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine3_req_addr;
assign soc_litedramcore_bankmachine3_cmd_buffer_sink_valid = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine3_cmd_buffer_sink_ready;
assign soc_litedramcore_bankmachine3_cmd_buffer_sink_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
assign soc_litedramcore_bankmachine3_cmd_buffer_sink_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
assign soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
assign soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
assign soc_litedramcore_bankmachine3_cmd_buffer_source_ready = (soc_litedramcore_bankmachine3_req_wdata_ready | soc_litedramcore_bankmachine3_req_rdata_valid);
assign soc_litedramcore_bankmachine3_req_lock = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine3_cmd_buffer_source_valid);
assign soc_litedramcore_bankmachine3_row_hit = (soc_litedramcore_bankmachine3_row == soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]);
assign soc_litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
always @(*) begin
soc_litedramcore_bankmachine3_cmd_payload_a = 14'd0;
if (soc_litedramcore_bankmachine3_row_col_n_addr_sel) begin
soc_litedramcore_bankmachine3_cmd_payload_a = soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
end else begin
soc_litedramcore_bankmachine3_cmd_payload_a = ((soc_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
end
assign soc_litedramcore_bankmachine3_twtpcon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_cmd_payload_is_write);
assign soc_litedramcore_bankmachine3_trccon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open);
assign soc_litedramcore_bankmachine3_trascon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open);
always @(*) begin
soc_litedramcore_bankmachine3_auto_precharge = 1'd0;
if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin
soc_litedramcore_bankmachine3_auto_precharge = (soc_litedramcore_bankmachine3_row_close == 1'd0);
end
end
end
assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
always @(*) begin
soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
end else begin
soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
end
end
assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
assign soc_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready);
always @(*) begin
bankmachine3_next_state = 4'd0;
bankmachine3_next_state = bankmachine3_state;
case (bankmachine3_state)
1'd1: begin
if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
if (soc_litedramcore_bankmachine3_cmd_ready) begin
bankmachine3_next_state = 3'd5;
end
end
end
2'd2: begin
if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
bankmachine3_next_state = 3'd5;
end
end
2'd3: begin
if (soc_litedramcore_bankmachine3_trccon_ready) begin
if (soc_litedramcore_bankmachine3_cmd_ready) begin
bankmachine3_next_state = 3'd7;
end
end
end
3'd4: begin
if ((~soc_litedramcore_bankmachine3_refresh_req)) begin
bankmachine3_next_state = 1'd0;
end
end
3'd5: begin
bankmachine3_next_state = 3'd6;
end
3'd6: begin
bankmachine3_next_state = 2'd3;
end
3'd7: begin
bankmachine3_next_state = 4'd8;
end
4'd8: begin
bankmachine3_next_state = 1'd0;
end
default: begin
if (soc_litedramcore_bankmachine3_refresh_req) begin
bankmachine3_next_state = 3'd4;
end else begin
if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine3_row_opened) begin
if (soc_litedramcore_bankmachine3_row_hit) begin
if ((soc_litedramcore_bankmachine3_cmd_ready & soc_litedramcore_bankmachine3_auto_precharge)) begin
bankmachine3_next_state = 2'd2;
end
end else begin
bankmachine3_next_state = 1'd1;
end
end else begin
bankmachine3_next_state = 2'd3;
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
case (bankmachine3_state)
1'd1: begin
if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
soc_litedramcore_bankmachine3_cmd_payload_we = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine3_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine3_row_opened) begin
if (soc_litedramcore_bankmachine3_row_hit) begin
if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
soc_litedramcore_bankmachine3_cmd_payload_we = 1'd1;
end else begin
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
case (bankmachine3_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine3_trccon_ready) begin
soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
case (bankmachine3_state)
1'd1: begin
if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine3_trccon_ready) begin
soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1;
end
end
3'd4: begin
soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1;
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
case (bankmachine3_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine3_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine3_row_opened) begin
if (soc_litedramcore_bankmachine3_row_hit) begin
if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
end else begin
soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd1;
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
case (bankmachine3_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine3_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine3_row_opened) begin
if (soc_litedramcore_bankmachine3_row_hit) begin
if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd1;
end else begin
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
case (bankmachine3_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine3_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine3_row_opened) begin
if (soc_litedramcore_bankmachine3_row_hit) begin
if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
soc_litedramcore_bankmachine3_req_wdata_ready = soc_litedramcore_bankmachine3_cmd_ready;
end else begin
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
case (bankmachine3_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine3_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine3_row_opened) begin
if (soc_litedramcore_bankmachine3_row_hit) begin
if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
end else begin
soc_litedramcore_bankmachine3_req_rdata_valid = soc_litedramcore_bankmachine3_cmd_ready;
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine3_refresh_gnt = 1'd0;
case (bankmachine3_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
if (soc_litedramcore_bankmachine3_twtpcon_ready) begin
soc_litedramcore_bankmachine3_refresh_gnt = 1'd1;
end
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine3_cmd_valid = 1'd0;
case (bankmachine3_state)
1'd1: begin
if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
soc_litedramcore_bankmachine3_cmd_valid = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine3_trccon_ready) begin
soc_litedramcore_bankmachine3_cmd_valid = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine3_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine3_row_opened) begin
if (soc_litedramcore_bankmachine3_row_hit) begin
soc_litedramcore_bankmachine3_cmd_valid = 1'd1;
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine3_row_open = 1'd0;
case (bankmachine3_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine3_trccon_ready) begin
soc_litedramcore_bankmachine3_row_open = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine3_row_close = 1'd0;
case (bankmachine3_state)
1'd1: begin
soc_litedramcore_bankmachine3_row_close = 1'd1;
end
2'd2: begin
soc_litedramcore_bankmachine3_row_close = 1'd1;
end
2'd3: begin
end
3'd4: begin
soc_litedramcore_bankmachine3_row_close = 1'd1;
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
case (bankmachine3_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine3_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine3_row_opened) begin
if (soc_litedramcore_bankmachine3_row_hit) begin
soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd1;
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
case (bankmachine3_state)
1'd1: begin
if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine3_trccon_ready) begin
soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine4_req_valid;
assign soc_litedramcore_bankmachine4_req_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine4_req_we;
assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine4_req_addr;
assign soc_litedramcore_bankmachine4_cmd_buffer_sink_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine4_cmd_buffer_sink_ready;
assign soc_litedramcore_bankmachine4_cmd_buffer_sink_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
assign soc_litedramcore_bankmachine4_cmd_buffer_sink_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
assign soc_litedramcore_bankmachine4_cmd_buffer_source_ready = (soc_litedramcore_bankmachine4_req_wdata_ready | soc_litedramcore_bankmachine4_req_rdata_valid);
assign soc_litedramcore_bankmachine4_req_lock = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine4_cmd_buffer_source_valid);
assign soc_litedramcore_bankmachine4_row_hit = (soc_litedramcore_bankmachine4_row == soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]);
assign soc_litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
always @(*) begin
soc_litedramcore_bankmachine4_cmd_payload_a = 14'd0;
if (soc_litedramcore_bankmachine4_row_col_n_addr_sel) begin
soc_litedramcore_bankmachine4_cmd_payload_a = soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
end else begin
soc_litedramcore_bankmachine4_cmd_payload_a = ((soc_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
end
assign soc_litedramcore_bankmachine4_twtpcon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_cmd_payload_is_write);
assign soc_litedramcore_bankmachine4_trccon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open);
assign soc_litedramcore_bankmachine4_trascon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open);
always @(*) begin
soc_litedramcore_bankmachine4_auto_precharge = 1'd0;
if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin
soc_litedramcore_bankmachine4_auto_precharge = (soc_litedramcore_bankmachine4_row_close == 1'd0);
end
end
end
assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
always @(*) begin
soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
end else begin
soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
end
end
assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
assign soc_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready);
always @(*) begin
bankmachine4_next_state = 4'd0;
bankmachine4_next_state = bankmachine4_state;
case (bankmachine4_state)
1'd1: begin
if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
if (soc_litedramcore_bankmachine4_cmd_ready) begin
bankmachine4_next_state = 3'd5;
end
end
end
2'd2: begin
if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
bankmachine4_next_state = 3'd5;
end
end
2'd3: begin
if (soc_litedramcore_bankmachine4_trccon_ready) begin
if (soc_litedramcore_bankmachine4_cmd_ready) begin
bankmachine4_next_state = 3'd7;
end
end
end
3'd4: begin
if ((~soc_litedramcore_bankmachine4_refresh_req)) begin
bankmachine4_next_state = 1'd0;
end
end
3'd5: begin
bankmachine4_next_state = 3'd6;
end
3'd6: begin
bankmachine4_next_state = 2'd3;
end
3'd7: begin
bankmachine4_next_state = 4'd8;
end
4'd8: begin
bankmachine4_next_state = 1'd0;
end
default: begin
if (soc_litedramcore_bankmachine4_refresh_req) begin
bankmachine4_next_state = 3'd4;
end else begin
if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine4_row_opened) begin
if (soc_litedramcore_bankmachine4_row_hit) begin
if ((soc_litedramcore_bankmachine4_cmd_ready & soc_litedramcore_bankmachine4_auto_precharge)) begin
bankmachine4_next_state = 2'd2;
end
end else begin
bankmachine4_next_state = 1'd1;
end
end else begin
bankmachine4_next_state = 2'd3;
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
case (bankmachine4_state)
1'd1: begin
if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
soc_litedramcore_bankmachine4_cmd_payload_we = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine4_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine4_row_opened) begin
if (soc_litedramcore_bankmachine4_row_hit) begin
if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
soc_litedramcore_bankmachine4_cmd_payload_we = 1'd1;
end else begin
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
case (bankmachine4_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine4_trccon_ready) begin
soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
case (bankmachine4_state)
1'd1: begin
if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine4_trccon_ready) begin
soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1;
end
end
3'd4: begin
soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1;
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
case (bankmachine4_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine4_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine4_row_opened) begin
if (soc_litedramcore_bankmachine4_row_hit) begin
if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
end else begin
soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd1;
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
case (bankmachine4_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine4_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine4_row_opened) begin
if (soc_litedramcore_bankmachine4_row_hit) begin
if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd1;
end else begin
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
case (bankmachine4_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine4_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine4_row_opened) begin
if (soc_litedramcore_bankmachine4_row_hit) begin
if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
soc_litedramcore_bankmachine4_req_wdata_ready = soc_litedramcore_bankmachine4_cmd_ready;
end else begin
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
case (bankmachine4_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine4_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine4_row_opened) begin
if (soc_litedramcore_bankmachine4_row_hit) begin
if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
end else begin
soc_litedramcore_bankmachine4_req_rdata_valid = soc_litedramcore_bankmachine4_cmd_ready;
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine4_refresh_gnt = 1'd0;
case (bankmachine4_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
if (soc_litedramcore_bankmachine4_twtpcon_ready) begin
soc_litedramcore_bankmachine4_refresh_gnt = 1'd1;
end
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine4_cmd_valid = 1'd0;
case (bankmachine4_state)
1'd1: begin
if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
soc_litedramcore_bankmachine4_cmd_valid = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine4_trccon_ready) begin
soc_litedramcore_bankmachine4_cmd_valid = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine4_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine4_row_opened) begin
if (soc_litedramcore_bankmachine4_row_hit) begin
soc_litedramcore_bankmachine4_cmd_valid = 1'd1;
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine4_row_open = 1'd0;
case (bankmachine4_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine4_trccon_ready) begin
soc_litedramcore_bankmachine4_row_open = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine4_row_close = 1'd0;
case (bankmachine4_state)
1'd1: begin
soc_litedramcore_bankmachine4_row_close = 1'd1;
end
2'd2: begin
soc_litedramcore_bankmachine4_row_close = 1'd1;
end
2'd3: begin
end
3'd4: begin
soc_litedramcore_bankmachine4_row_close = 1'd1;
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
case (bankmachine4_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine4_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine4_row_opened) begin
if (soc_litedramcore_bankmachine4_row_hit) begin
soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd1;
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
case (bankmachine4_state)
1'd1: begin
if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine4_trccon_ready) begin
soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine5_req_valid;
assign soc_litedramcore_bankmachine5_req_ready = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine5_req_we;
assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine5_req_addr;
assign soc_litedramcore_bankmachine5_cmd_buffer_sink_valid = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine5_cmd_buffer_sink_ready;
assign soc_litedramcore_bankmachine5_cmd_buffer_sink_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
assign soc_litedramcore_bankmachine5_cmd_buffer_sink_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
assign soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
assign soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
assign soc_litedramcore_bankmachine5_cmd_buffer_source_ready = (soc_litedramcore_bankmachine5_req_wdata_ready | soc_litedramcore_bankmachine5_req_rdata_valid);
assign soc_litedramcore_bankmachine5_req_lock = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine5_cmd_buffer_source_valid);
assign soc_litedramcore_bankmachine5_row_hit = (soc_litedramcore_bankmachine5_row == soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]);
assign soc_litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
always @(*) begin
soc_litedramcore_bankmachine5_cmd_payload_a = 14'd0;
if (soc_litedramcore_bankmachine5_row_col_n_addr_sel) begin
soc_litedramcore_bankmachine5_cmd_payload_a = soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
end else begin
soc_litedramcore_bankmachine5_cmd_payload_a = ((soc_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
end
assign soc_litedramcore_bankmachine5_twtpcon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_cmd_payload_is_write);
assign soc_litedramcore_bankmachine5_trccon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open);
assign soc_litedramcore_bankmachine5_trascon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open);
always @(*) begin
soc_litedramcore_bankmachine5_auto_precharge = 1'd0;
if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin
soc_litedramcore_bankmachine5_auto_precharge = (soc_litedramcore_bankmachine5_row_close == 1'd0);
end
end
end
assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
always @(*) begin
soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
end else begin
soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
end
end
assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
assign soc_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready);
always @(*) begin
bankmachine5_next_state = 4'd0;
bankmachine5_next_state = bankmachine5_state;
case (bankmachine5_state)
1'd1: begin
if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
if (soc_litedramcore_bankmachine5_cmd_ready) begin
bankmachine5_next_state = 3'd5;
end
end
end
2'd2: begin
if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
bankmachine5_next_state = 3'd5;
end
end
2'd3: begin
if (soc_litedramcore_bankmachine5_trccon_ready) begin
if (soc_litedramcore_bankmachine5_cmd_ready) begin
bankmachine5_next_state = 3'd7;
end
end
end
3'd4: begin
if ((~soc_litedramcore_bankmachine5_refresh_req)) begin
bankmachine5_next_state = 1'd0;
end
end
3'd5: begin
bankmachine5_next_state = 3'd6;
end
3'd6: begin
bankmachine5_next_state = 2'd3;
end
3'd7: begin
bankmachine5_next_state = 4'd8;
end
4'd8: begin
bankmachine5_next_state = 1'd0;
end
default: begin
if (soc_litedramcore_bankmachine5_refresh_req) begin
bankmachine5_next_state = 3'd4;
end else begin
if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine5_row_opened) begin
if (soc_litedramcore_bankmachine5_row_hit) begin
if ((soc_litedramcore_bankmachine5_cmd_ready & soc_litedramcore_bankmachine5_auto_precharge)) begin
bankmachine5_next_state = 2'd2;
end
end else begin
bankmachine5_next_state = 1'd1;
end
end else begin
bankmachine5_next_state = 2'd3;
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
case (bankmachine5_state)
1'd1: begin
if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
soc_litedramcore_bankmachine5_cmd_payload_we = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine5_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine5_row_opened) begin
if (soc_litedramcore_bankmachine5_row_hit) begin
if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
soc_litedramcore_bankmachine5_cmd_payload_we = 1'd1;
end else begin
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
case (bankmachine5_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine5_trccon_ready) begin
soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
case (bankmachine5_state)
1'd1: begin
if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine5_trccon_ready) begin
soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1;
end
end
3'd4: begin
soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1;
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
case (bankmachine5_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine5_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine5_row_opened) begin
if (soc_litedramcore_bankmachine5_row_hit) begin
if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
end else begin
soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd1;
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
case (bankmachine5_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine5_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine5_row_opened) begin
if (soc_litedramcore_bankmachine5_row_hit) begin
if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd1;
end else begin
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
case (bankmachine5_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine5_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine5_row_opened) begin
if (soc_litedramcore_bankmachine5_row_hit) begin
if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
soc_litedramcore_bankmachine5_req_wdata_ready = soc_litedramcore_bankmachine5_cmd_ready;
end else begin
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
case (bankmachine5_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine5_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine5_row_opened) begin
if (soc_litedramcore_bankmachine5_row_hit) begin
if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
end else begin
soc_litedramcore_bankmachine5_req_rdata_valid = soc_litedramcore_bankmachine5_cmd_ready;
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine5_refresh_gnt = 1'd0;
case (bankmachine5_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
if (soc_litedramcore_bankmachine5_twtpcon_ready) begin
soc_litedramcore_bankmachine5_refresh_gnt = 1'd1;
end
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine5_cmd_valid = 1'd0;
case (bankmachine5_state)
1'd1: begin
if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
soc_litedramcore_bankmachine5_cmd_valid = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine5_trccon_ready) begin
soc_litedramcore_bankmachine5_cmd_valid = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine5_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine5_row_opened) begin
if (soc_litedramcore_bankmachine5_row_hit) begin
soc_litedramcore_bankmachine5_cmd_valid = 1'd1;
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine5_row_open = 1'd0;
case (bankmachine5_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine5_trccon_ready) begin
soc_litedramcore_bankmachine5_row_open = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine5_row_close = 1'd0;
case (bankmachine5_state)
1'd1: begin
soc_litedramcore_bankmachine5_row_close = 1'd1;
end
2'd2: begin
soc_litedramcore_bankmachine5_row_close = 1'd1;
end
2'd3: begin
end
3'd4: begin
soc_litedramcore_bankmachine5_row_close = 1'd1;
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
case (bankmachine5_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine5_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine5_row_opened) begin
if (soc_litedramcore_bankmachine5_row_hit) begin
soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd1;
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
case (bankmachine5_state)
1'd1: begin
if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine5_trccon_ready) begin
soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine6_req_valid;
assign soc_litedramcore_bankmachine6_req_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine6_req_we;
assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine6_req_addr;
assign soc_litedramcore_bankmachine6_cmd_buffer_sink_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine6_cmd_buffer_sink_ready;
assign soc_litedramcore_bankmachine6_cmd_buffer_sink_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
assign soc_litedramcore_bankmachine6_cmd_buffer_sink_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
assign soc_litedramcore_bankmachine6_cmd_buffer_source_ready = (soc_litedramcore_bankmachine6_req_wdata_ready | soc_litedramcore_bankmachine6_req_rdata_valid);
assign soc_litedramcore_bankmachine6_req_lock = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine6_cmd_buffer_source_valid);
assign soc_litedramcore_bankmachine6_row_hit = (soc_litedramcore_bankmachine6_row == soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]);
assign soc_litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
always @(*) begin
soc_litedramcore_bankmachine6_cmd_payload_a = 14'd0;
if (soc_litedramcore_bankmachine6_row_col_n_addr_sel) begin
soc_litedramcore_bankmachine6_cmd_payload_a = soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
end else begin
soc_litedramcore_bankmachine6_cmd_payload_a = ((soc_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
end
assign soc_litedramcore_bankmachine6_twtpcon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_cmd_payload_is_write);
assign soc_litedramcore_bankmachine6_trccon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open);
assign soc_litedramcore_bankmachine6_trascon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open);
always @(*) begin
soc_litedramcore_bankmachine6_auto_precharge = 1'd0;
if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin
soc_litedramcore_bankmachine6_auto_precharge = (soc_litedramcore_bankmachine6_row_close == 1'd0);
end
end
end
assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
always @(*) begin
soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
end else begin
soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
end
end
assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
assign soc_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready);
always @(*) begin
bankmachine6_next_state = 4'd0;
bankmachine6_next_state = bankmachine6_state;
case (bankmachine6_state)
1'd1: begin
if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
if (soc_litedramcore_bankmachine6_cmd_ready) begin
bankmachine6_next_state = 3'd5;
end
end
end
2'd2: begin
if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
bankmachine6_next_state = 3'd5;
end
end
2'd3: begin
if (soc_litedramcore_bankmachine6_trccon_ready) begin
if (soc_litedramcore_bankmachine6_cmd_ready) begin
bankmachine6_next_state = 3'd7;
end
end
end
3'd4: begin
if ((~soc_litedramcore_bankmachine6_refresh_req)) begin
bankmachine6_next_state = 1'd0;
end
end
3'd5: begin
bankmachine6_next_state = 3'd6;
end
3'd6: begin
bankmachine6_next_state = 2'd3;
end
3'd7: begin
bankmachine6_next_state = 4'd8;
end
4'd8: begin
bankmachine6_next_state = 1'd0;
end
default: begin
if (soc_litedramcore_bankmachine6_refresh_req) begin
bankmachine6_next_state = 3'd4;
end else begin
if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine6_row_opened) begin
if (soc_litedramcore_bankmachine6_row_hit) begin
if ((soc_litedramcore_bankmachine6_cmd_ready & soc_litedramcore_bankmachine6_auto_precharge)) begin
bankmachine6_next_state = 2'd2;
end
end else begin
bankmachine6_next_state = 1'd1;
end
end else begin
bankmachine6_next_state = 2'd3;
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
case (bankmachine6_state)
1'd1: begin
if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
soc_litedramcore_bankmachine6_cmd_payload_we = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine6_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine6_row_opened) begin
if (soc_litedramcore_bankmachine6_row_hit) begin
if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
soc_litedramcore_bankmachine6_cmd_payload_we = 1'd1;
end else begin
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
case (bankmachine6_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine6_trccon_ready) begin
soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
case (bankmachine6_state)
1'd1: begin
if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine6_trccon_ready) begin
soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1;
end
end
3'd4: begin
soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1;
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
case (bankmachine6_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine6_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine6_row_opened) begin
if (soc_litedramcore_bankmachine6_row_hit) begin
if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
end else begin
soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd1;
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
case (bankmachine6_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine6_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine6_row_opened) begin
if (soc_litedramcore_bankmachine6_row_hit) begin
if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd1;
end else begin
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
case (bankmachine6_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine6_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine6_row_opened) begin
if (soc_litedramcore_bankmachine6_row_hit) begin
if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
soc_litedramcore_bankmachine6_req_wdata_ready = soc_litedramcore_bankmachine6_cmd_ready;
end else begin
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
case (bankmachine6_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine6_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine6_row_opened) begin
if (soc_litedramcore_bankmachine6_row_hit) begin
if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
end else begin
soc_litedramcore_bankmachine6_req_rdata_valid = soc_litedramcore_bankmachine6_cmd_ready;
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine6_refresh_gnt = 1'd0;
case (bankmachine6_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
if (soc_litedramcore_bankmachine6_twtpcon_ready) begin
soc_litedramcore_bankmachine6_refresh_gnt = 1'd1;
end
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine6_cmd_valid = 1'd0;
case (bankmachine6_state)
1'd1: begin
if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
soc_litedramcore_bankmachine6_cmd_valid = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine6_trccon_ready) begin
soc_litedramcore_bankmachine6_cmd_valid = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine6_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine6_row_opened) begin
if (soc_litedramcore_bankmachine6_row_hit) begin
soc_litedramcore_bankmachine6_cmd_valid = 1'd1;
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine6_row_open = 1'd0;
case (bankmachine6_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine6_trccon_ready) begin
soc_litedramcore_bankmachine6_row_open = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine6_row_close = 1'd0;
case (bankmachine6_state)
1'd1: begin
soc_litedramcore_bankmachine6_row_close = 1'd1;
end
2'd2: begin
soc_litedramcore_bankmachine6_row_close = 1'd1;
end
2'd3: begin
end
3'd4: begin
soc_litedramcore_bankmachine6_row_close = 1'd1;
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
case (bankmachine6_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine6_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine6_row_opened) begin
if (soc_litedramcore_bankmachine6_row_hit) begin
soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd1;
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
case (bankmachine6_state)
1'd1: begin
if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine6_trccon_ready) begin
soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine7_req_valid;
assign soc_litedramcore_bankmachine7_req_ready = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine7_req_we;
assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine7_req_addr;
assign soc_litedramcore_bankmachine7_cmd_buffer_sink_valid = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine7_cmd_buffer_sink_ready;
assign soc_litedramcore_bankmachine7_cmd_buffer_sink_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
assign soc_litedramcore_bankmachine7_cmd_buffer_sink_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
assign soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
assign soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
assign soc_litedramcore_bankmachine7_cmd_buffer_source_ready = (soc_litedramcore_bankmachine7_req_wdata_ready | soc_litedramcore_bankmachine7_req_rdata_valid);
assign soc_litedramcore_bankmachine7_req_lock = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine7_cmd_buffer_source_valid);
assign soc_litedramcore_bankmachine7_row_hit = (soc_litedramcore_bankmachine7_row == soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]);
assign soc_litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
always @(*) begin
soc_litedramcore_bankmachine7_cmd_payload_a = 14'd0;
if (soc_litedramcore_bankmachine7_row_col_n_addr_sel) begin
soc_litedramcore_bankmachine7_cmd_payload_a = soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
end else begin
soc_litedramcore_bankmachine7_cmd_payload_a = ((soc_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
end
assign soc_litedramcore_bankmachine7_twtpcon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_cmd_payload_is_write);
assign soc_litedramcore_bankmachine7_trccon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open);
assign soc_litedramcore_bankmachine7_trascon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open);
always @(*) begin
soc_litedramcore_bankmachine7_auto_precharge = 1'd0;
if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin
soc_litedramcore_bankmachine7_auto_precharge = (soc_litedramcore_bankmachine7_row_close == 1'd0);
end
end
end
assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
always @(*) begin
soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
end else begin
soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
end
end
assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
assign soc_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready);
always @(*) begin
bankmachine7_next_state = 4'd0;
bankmachine7_next_state = bankmachine7_state;
case (bankmachine7_state)
1'd1: begin
if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
if (soc_litedramcore_bankmachine7_cmd_ready) begin
bankmachine7_next_state = 3'd5;
end
end
end
2'd2: begin
if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
bankmachine7_next_state = 3'd5;
end
end
2'd3: begin
if (soc_litedramcore_bankmachine7_trccon_ready) begin
if (soc_litedramcore_bankmachine7_cmd_ready) begin
bankmachine7_next_state = 3'd7;
end
end
end
3'd4: begin
if ((~soc_litedramcore_bankmachine7_refresh_req)) begin
bankmachine7_next_state = 1'd0;
end
end
3'd5: begin
bankmachine7_next_state = 3'd6;
end
3'd6: begin
bankmachine7_next_state = 2'd3;
end
3'd7: begin
bankmachine7_next_state = 4'd8;
end
4'd8: begin
bankmachine7_next_state = 1'd0;
end
default: begin
if (soc_litedramcore_bankmachine7_refresh_req) begin
bankmachine7_next_state = 3'd4;
end else begin
if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine7_row_opened) begin
if (soc_litedramcore_bankmachine7_row_hit) begin
if ((soc_litedramcore_bankmachine7_cmd_ready & soc_litedramcore_bankmachine7_auto_precharge)) begin
bankmachine7_next_state = 2'd2;
end
end else begin
bankmachine7_next_state = 1'd1;
end
end else begin
bankmachine7_next_state = 2'd3;
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
case (bankmachine7_state)
1'd1: begin
if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
soc_litedramcore_bankmachine7_cmd_payload_we = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine7_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine7_row_opened) begin
if (soc_litedramcore_bankmachine7_row_hit) begin
if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
soc_litedramcore_bankmachine7_cmd_payload_we = 1'd1;
end else begin
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
case (bankmachine7_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine7_trccon_ready) begin
soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
case (bankmachine7_state)
1'd1: begin
if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine7_trccon_ready) begin
soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1;
end
end
3'd4: begin
soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1;
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
case (bankmachine7_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine7_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine7_row_opened) begin
if (soc_litedramcore_bankmachine7_row_hit) begin
if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
end else begin
soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd1;
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
case (bankmachine7_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine7_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine7_row_opened) begin
if (soc_litedramcore_bankmachine7_row_hit) begin
if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd1;
end else begin
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
case (bankmachine7_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine7_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine7_row_opened) begin
if (soc_litedramcore_bankmachine7_row_hit) begin
if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
soc_litedramcore_bankmachine7_req_wdata_ready = soc_litedramcore_bankmachine7_cmd_ready;
end else begin
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
case (bankmachine7_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine7_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine7_row_opened) begin
if (soc_litedramcore_bankmachine7_row_hit) begin
if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
end else begin
soc_litedramcore_bankmachine7_req_rdata_valid = soc_litedramcore_bankmachine7_cmd_ready;
end
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine7_refresh_gnt = 1'd0;
case (bankmachine7_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
if (soc_litedramcore_bankmachine7_twtpcon_ready) begin
soc_litedramcore_bankmachine7_refresh_gnt = 1'd1;
end
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine7_cmd_valid = 1'd0;
case (bankmachine7_state)
1'd1: begin
if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
soc_litedramcore_bankmachine7_cmd_valid = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine7_trccon_ready) begin
soc_litedramcore_bankmachine7_cmd_valid = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine7_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine7_row_opened) begin
if (soc_litedramcore_bankmachine7_row_hit) begin
soc_litedramcore_bankmachine7_cmd_valid = 1'd1;
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine7_row_open = 1'd0;
case (bankmachine7_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine7_trccon_ready) begin
soc_litedramcore_bankmachine7_row_open = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine7_row_close = 1'd0;
case (bankmachine7_state)
1'd1: begin
soc_litedramcore_bankmachine7_row_close = 1'd1;
end
2'd2: begin
soc_litedramcore_bankmachine7_row_close = 1'd1;
end
2'd3: begin
end
3'd4: begin
soc_litedramcore_bankmachine7_row_close = 1'd1;
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
case (bankmachine7_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
if (soc_litedramcore_bankmachine7_refresh_req) begin
end else begin
if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
if (soc_litedramcore_bankmachine7_row_opened) begin
if (soc_litedramcore_bankmachine7_row_hit) begin
soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd1;
end else begin
end
end else begin
end
end
end
end
endcase
end
always @(*) begin
soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
case (bankmachine7_state)
1'd1: begin
if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (soc_litedramcore_bankmachine7_trccon_ready) begin
soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd1;
end
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
default: begin
end
endcase
end
assign soc_litedramcore_trrdcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we)));
assign soc_litedramcore_tfawcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we)));
assign soc_litedramcore_ras_allowed = (soc_litedramcore_trrdcon_ready & soc_litedramcore_tfawcon_ready);
assign soc_litedramcore_tccdcon_valid = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_cmd_payload_is_write | soc_litedramcore_choose_req_cmd_payload_is_read));
assign soc_litedramcore_cas_allowed = soc_litedramcore_tccdcon_ready;
assign soc_litedramcore_twtrcon_valid = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
assign soc_litedramcore_read_available = ((((((((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_payload_is_read) | (soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_payload_is_read)) | (soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_payload_is_read)) | (soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_payload_is_read)) | (soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_payload_is_read)) | (soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_payload_is_read)) | (soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_payload_is_read)) | (soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_payload_is_read));
assign soc_litedramcore_write_available = ((((((((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_payload_is_write) | (soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_payload_is_write)) | (soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_payload_is_write)) | (soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_payload_is_write)) | (soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_payload_is_write)) | (soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_payload_is_write)) | (soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_payload_is_write)) | (soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_payload_is_write));
assign soc_litedramcore_max_time0 = (soc_litedramcore_time0 == 1'd0);
assign soc_litedramcore_max_time1 = (soc_litedramcore_time1 == 1'd0);
assign soc_litedramcore_bankmachine0_refresh_req = soc_litedramcore_cmd_valid;
assign soc_litedramcore_bankmachine1_refresh_req = soc_litedramcore_cmd_valid;
assign soc_litedramcore_bankmachine2_refresh_req = soc_litedramcore_cmd_valid;
assign soc_litedramcore_bankmachine3_refresh_req = soc_litedramcore_cmd_valid;
assign soc_litedramcore_bankmachine4_refresh_req = soc_litedramcore_cmd_valid;
assign soc_litedramcore_bankmachine5_refresh_req = soc_litedramcore_cmd_valid;
assign soc_litedramcore_bankmachine6_refresh_req = soc_litedramcore_cmd_valid;
assign soc_litedramcore_bankmachine7_refresh_req = soc_litedramcore_cmd_valid;
assign soc_litedramcore_go_to_refresh = (((((((soc_litedramcore_bankmachine0_refresh_gnt & soc_litedramcore_bankmachine1_refresh_gnt) & soc_litedramcore_bankmachine2_refresh_gnt) & soc_litedramcore_bankmachine3_refresh_gnt) & soc_litedramcore_bankmachine4_refresh_gnt) & soc_litedramcore_bankmachine5_refresh_gnt) & soc_litedramcore_bankmachine6_refresh_gnt) & soc_litedramcore_bankmachine7_refresh_gnt);
assign soc_litedramcore_interface_rdata = {soc_litedramcore_dfi_p3_rddata, soc_litedramcore_dfi_p2_rddata, soc_litedramcore_dfi_p1_rddata, soc_litedramcore_dfi_p0_rddata};
assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata;
assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata;
assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata;
assign {soc_litedramcore_dfi_p3_wrdata, soc_litedramcore_dfi_p2_wrdata, soc_litedramcore_dfi_p1_wrdata, soc_litedramcore_dfi_p0_wrdata} = soc_litedramcore_interface_wdata;
assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we);
assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we);
assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we);
assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we);
always @(*) begin
soc_litedramcore_choose_cmd_valids = 8'd0;
soc_litedramcore_choose_cmd_valids[0] = (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
soc_litedramcore_choose_cmd_valids[1] = (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
soc_litedramcore_choose_cmd_valids[2] = (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
soc_litedramcore_choose_cmd_valids[3] = (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
soc_litedramcore_choose_cmd_valids[4] = (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
soc_litedramcore_choose_cmd_valids[5] = (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
soc_litedramcore_choose_cmd_valids[6] = (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
soc_litedramcore_choose_cmd_valids[7] = (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
end
assign soc_litedramcore_choose_cmd_request = soc_litedramcore_choose_cmd_valids;
assign soc_litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
assign soc_litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1;
assign soc_litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2;
assign soc_litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
assign soc_litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
assign soc_litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
always @(*) begin
soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
if (soc_litedramcore_choose_cmd_cmd_valid) begin
soc_litedramcore_choose_cmd_cmd_payload_cas = t_array_muxed0;
end
end
always @(*) begin
soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
if (soc_litedramcore_choose_cmd_cmd_valid) begin
soc_litedramcore_choose_cmd_cmd_payload_ras = t_array_muxed1;
end
end
always @(*) begin
soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
if (soc_litedramcore_choose_cmd_cmd_valid) begin
soc_litedramcore_choose_cmd_cmd_payload_we = t_array_muxed2;
end
end
always @(*) begin
soc_litedramcore_bankmachine0_cmd_ready = 1'd0;
if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd0))) begin
soc_litedramcore_bankmachine0_cmd_ready = 1'd1;
end
if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd0))) begin
soc_litedramcore_bankmachine0_cmd_ready = 1'd1;
end
end
always @(*) begin
soc_litedramcore_bankmachine1_cmd_ready = 1'd0;
if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd1))) begin
soc_litedramcore_bankmachine1_cmd_ready = 1'd1;
end
if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd1))) begin
soc_litedramcore_bankmachine1_cmd_ready = 1'd1;
end
end
always @(*) begin
soc_litedramcore_bankmachine2_cmd_ready = 1'd0;
if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd2))) begin
soc_litedramcore_bankmachine2_cmd_ready = 1'd1;
end
if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd2))) begin
soc_litedramcore_bankmachine2_cmd_ready = 1'd1;
end
end
always @(*) begin
soc_litedramcore_bankmachine3_cmd_ready = 1'd0;
if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd3))) begin
soc_litedramcore_bankmachine3_cmd_ready = 1'd1;
end
if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd3))) begin
soc_litedramcore_bankmachine3_cmd_ready = 1'd1;
end
end
always @(*) begin
soc_litedramcore_bankmachine4_cmd_ready = 1'd0;
if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd4))) begin
soc_litedramcore_bankmachine4_cmd_ready = 1'd1;
end
if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd4))) begin
soc_litedramcore_bankmachine4_cmd_ready = 1'd1;
end
end
always @(*) begin
soc_litedramcore_bankmachine5_cmd_ready = 1'd0;
if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd5))) begin
soc_litedramcore_bankmachine5_cmd_ready = 1'd1;
end
if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd5))) begin
soc_litedramcore_bankmachine5_cmd_ready = 1'd1;
end
end
always @(*) begin
soc_litedramcore_bankmachine6_cmd_ready = 1'd0;
if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd6))) begin
soc_litedramcore_bankmachine6_cmd_ready = 1'd1;
end
if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd6))) begin
soc_litedramcore_bankmachine6_cmd_ready = 1'd1;
end
end
always @(*) begin
soc_litedramcore_bankmachine7_cmd_ready = 1'd0;
if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd7))) begin
soc_litedramcore_bankmachine7_cmd_ready = 1'd1;
end
if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd7))) begin
soc_litedramcore_bankmachine7_cmd_ready = 1'd1;
end
end
assign soc_litedramcore_choose_cmd_ce = (soc_litedramcore_choose_cmd_cmd_ready | (~soc_litedramcore_choose_cmd_cmd_valid));
always @(*) begin
soc_litedramcore_choose_req_valids = 8'd0;
soc_litedramcore_choose_req_valids[0] = (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
soc_litedramcore_choose_req_valids[1] = (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
soc_litedramcore_choose_req_valids[2] = (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
soc_litedramcore_choose_req_valids[3] = (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
soc_litedramcore_choose_req_valids[4] = (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
soc_litedramcore_choose_req_valids[5] = (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
soc_litedramcore_choose_req_valids[6] = (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
soc_litedramcore_choose_req_valids[7] = (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
end
assign soc_litedramcore_choose_req_request = soc_litedramcore_choose_req_valids;
assign soc_litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
assign soc_litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7;
assign soc_litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8;
assign soc_litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9;
assign soc_litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
assign soc_litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
always @(*) begin
soc_litedramcore_choose_req_cmd_payload_cas = 1'd0;
if (soc_litedramcore_choose_req_cmd_valid) begin
soc_litedramcore_choose_req_cmd_payload_cas = t_array_muxed3;
end
end
always @(*) begin
soc_litedramcore_choose_req_cmd_payload_ras = 1'd0;
if (soc_litedramcore_choose_req_cmd_valid) begin
soc_litedramcore_choose_req_cmd_payload_ras = t_array_muxed4;
end
end
always @(*) begin
soc_litedramcore_choose_req_cmd_payload_we = 1'd0;
if (soc_litedramcore_choose_req_cmd_valid) begin
soc_litedramcore_choose_req_cmd_payload_we = t_array_muxed5;
end
end
assign soc_litedramcore_choose_req_ce = (soc_litedramcore_choose_req_cmd_ready | (~soc_litedramcore_choose_req_cmd_valid));
assign soc_litedramcore_dfi_p0_reset_n = 1'd1;
assign soc_litedramcore_dfi_p0_cke = {1{soc_litedramcore_steerer0}};
assign soc_litedramcore_dfi_p0_odt = {1{soc_litedramcore_steerer1}};
assign soc_litedramcore_dfi_p1_reset_n = 1'd1;
assign soc_litedramcore_dfi_p1_cke = {1{soc_litedramcore_steerer2}};
assign soc_litedramcore_dfi_p1_odt = {1{soc_litedramcore_steerer3}};
assign soc_litedramcore_dfi_p2_reset_n = 1'd1;
assign soc_litedramcore_dfi_p2_cke = {1{soc_litedramcore_steerer4}};
assign soc_litedramcore_dfi_p2_odt = {1{soc_litedramcore_steerer5}};
assign soc_litedramcore_dfi_p3_reset_n = 1'd1;
assign soc_litedramcore_dfi_p3_cke = {1{soc_litedramcore_steerer6}};
assign soc_litedramcore_dfi_p3_odt = {1{soc_litedramcore_steerer7}};
assign soc_litedramcore_tfawcon_count = ((((soc_litedramcore_tfawcon_window[0] + soc_litedramcore_tfawcon_window[1]) + soc_litedramcore_tfawcon_window[2]) + soc_litedramcore_tfawcon_window[3]) + soc_litedramcore_tfawcon_window[4]);
always @(*) begin
multiplexer_next_state = 4'd0;
multiplexer_next_state = multiplexer_state;
case (multiplexer_state)
1'd1: begin
if (soc_litedramcore_read_available) begin
if (((~soc_litedramcore_write_available) | soc_litedramcore_max_time1)) begin
multiplexer_next_state = 2'd3;
end
end
if (soc_litedramcore_go_to_refresh) begin
multiplexer_next_state = 2'd2;
end
end
2'd2: begin
if (soc_litedramcore_cmd_last) begin
multiplexer_next_state = 1'd0;
end
end
2'd3: begin
if (soc_litedramcore_twtrcon_ready) begin
multiplexer_next_state = 1'd0;
end
end
3'd4: begin
multiplexer_next_state = 3'd5;
end
3'd5: begin
multiplexer_next_state = 3'd6;
end
3'd6: begin
multiplexer_next_state = 3'd7;
end
3'd7: begin
multiplexer_next_state = 4'd8;
end
4'd8: begin
multiplexer_next_state = 4'd9;
end
4'd9: begin
multiplexer_next_state = 4'd10;
end
4'd10: begin
multiplexer_next_state = 1'd1;
end
default: begin
if (soc_litedramcore_write_available) begin
if (((~soc_litedramcore_read_available) | soc_litedramcore_max_time0)) begin
multiplexer_next_state = 3'd4;
end
end
if (soc_litedramcore_go_to_refresh) begin
multiplexer_next_state = 2'd2;
end
end
endcase
end
always @(*) begin
soc_litedramcore_steerer_sel0 = 2'd0;
case (multiplexer_state)
1'd1: begin
soc_litedramcore_steerer_sel0 = 1'd0;
if (1'd0) begin
soc_litedramcore_steerer_sel0 = 2'd2;
end
if (1'd0) begin
soc_litedramcore_steerer_sel0 = 1'd1;
end
end
2'd2: begin
soc_litedramcore_steerer_sel0 = 2'd3;
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
4'd9: begin
end
4'd10: begin
end
default: begin
soc_litedramcore_steerer_sel0 = 1'd0;
if (1'd0) begin
soc_litedramcore_steerer_sel0 = 2'd2;
end
if (1'd0) begin
soc_litedramcore_steerer_sel0 = 1'd1;
end
end
endcase
end
always @(*) begin
soc_litedramcore_steerer_sel1 = 2'd0;
case (multiplexer_state)
1'd1: begin
soc_litedramcore_steerer_sel1 = 1'd0;
if (1'd0) begin
soc_litedramcore_steerer_sel1 = 2'd2;
end
if (1'd0) begin
soc_litedramcore_steerer_sel1 = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
4'd9: begin
end
4'd10: begin
end
default: begin
soc_litedramcore_steerer_sel1 = 1'd0;
if (1'd0) begin
soc_litedramcore_steerer_sel1 = 2'd2;
end
if (1'd1) begin
soc_litedramcore_steerer_sel1 = 1'd1;
end
end
endcase
end
always @(*) begin
soc_litedramcore_steerer_sel2 = 2'd0;
case (multiplexer_state)
1'd1: begin
soc_litedramcore_steerer_sel2 = 1'd0;
if (1'd0) begin
soc_litedramcore_steerer_sel2 = 2'd2;
end
if (1'd1) begin
soc_litedramcore_steerer_sel2 = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
4'd9: begin
end
4'd10: begin
end
default: begin
soc_litedramcore_steerer_sel2 = 1'd0;
if (1'd1) begin
soc_litedramcore_steerer_sel2 = 2'd2;
end
if (1'd0) begin
soc_litedramcore_steerer_sel2 = 1'd1;
end
end
endcase
end
always @(*) begin
soc_litedramcore_choose_cmd_want_activates = 1'd0;
case (multiplexer_state)
1'd1: begin
if (1'd0) begin
end else begin
soc_litedramcore_choose_cmd_want_activates = soc_litedramcore_ras_allowed;
end
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
4'd9: begin
end
4'd10: begin
end
default: begin
if (1'd0) begin
end else begin
soc_litedramcore_choose_cmd_want_activates = soc_litedramcore_ras_allowed;
end
end
endcase
end
always @(*) begin
soc_litedramcore_steerer_sel3 = 2'd0;
case (multiplexer_state)
1'd1: begin
soc_litedramcore_steerer_sel3 = 1'd0;
if (1'd1) begin
soc_litedramcore_steerer_sel3 = 2'd2;
end
if (1'd0) begin
soc_litedramcore_steerer_sel3 = 1'd1;
end
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
4'd9: begin
end
4'd10: begin
end
default: begin
soc_litedramcore_steerer_sel3 = 1'd0;
if (1'd0) begin
soc_litedramcore_steerer_sel3 = 2'd2;
end
if (1'd0) begin
soc_litedramcore_steerer_sel3 = 1'd1;
end
end
endcase
end
always @(*) begin
soc_litedramcore_en0 = 1'd0;
case (multiplexer_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
4'd9: begin
end
4'd10: begin
end
default: begin
soc_litedramcore_en0 = 1'd1;
end
endcase
end
always @(*) begin
soc_litedramcore_cmd_ready = 1'd0;
case (multiplexer_state)
1'd1: begin
end
2'd2: begin
soc_litedramcore_cmd_ready = 1'd1;
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
4'd9: begin
end
4'd10: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_choose_cmd_cmd_ready = 1'd0;
case (multiplexer_state)
1'd1: begin
if (1'd0) begin
end else begin
soc_litedramcore_choose_cmd_cmd_ready = ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed);
end
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
4'd9: begin
end
4'd10: begin
end
default: begin
if (1'd0) begin
end else begin
soc_litedramcore_choose_cmd_cmd_ready = ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed);
end
end
endcase
end
always @(*) begin
soc_litedramcore_choose_req_want_reads = 1'd0;
case (multiplexer_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
4'd9: begin
end
4'd10: begin
end
default: begin
soc_litedramcore_choose_req_want_reads = 1'd1;
end
endcase
end
always @(*) begin
soc_litedramcore_en1 = 1'd0;
case (multiplexer_state)
1'd1: begin
soc_litedramcore_en1 = 1'd1;
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
4'd9: begin
end
4'd10: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_choose_req_want_writes = 1'd0;
case (multiplexer_state)
1'd1: begin
soc_litedramcore_choose_req_want_writes = 1'd1;
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
4'd9: begin
end
4'd10: begin
end
default: begin
end
endcase
end
always @(*) begin
soc_litedramcore_choose_req_cmd_ready = 1'd0;
case (multiplexer_state)
1'd1: begin
if (1'd0) begin
soc_litedramcore_choose_req_cmd_ready = (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
end else begin
soc_litedramcore_choose_req_cmd_ready = soc_litedramcore_cas_allowed;
end
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
end
3'd5: begin
end
3'd6: begin
end
3'd7: begin
end
4'd8: begin
end
4'd9: begin
end
4'd10: begin
end
default: begin
if (1'd0) begin
soc_litedramcore_choose_req_cmd_ready = (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
end else begin
soc_litedramcore_choose_req_cmd_ready = soc_litedramcore_cas_allowed;
end
end
endcase
end
assign roundrobin0_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
assign roundrobin0_ce = ((~soc_litedramcore_interface_bank0_valid) & (~soc_litedramcore_interface_bank0_lock));
assign soc_litedramcore_interface_bank0_addr = rhs_array_muxed12;
assign soc_litedramcore_interface_bank0_we = rhs_array_muxed13;
assign soc_litedramcore_interface_bank0_valid = rhs_array_muxed14;
assign roundrobin1_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
assign roundrobin1_ce = ((~soc_litedramcore_interface_bank1_valid) & (~soc_litedramcore_interface_bank1_lock));
assign soc_litedramcore_interface_bank1_addr = rhs_array_muxed15;
assign soc_litedramcore_interface_bank1_we = rhs_array_muxed16;
assign soc_litedramcore_interface_bank1_valid = rhs_array_muxed17;
assign roundrobin2_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
assign roundrobin2_ce = ((~soc_litedramcore_interface_bank2_valid) & (~soc_litedramcore_interface_bank2_lock));
assign soc_litedramcore_interface_bank2_addr = rhs_array_muxed18;
assign soc_litedramcore_interface_bank2_we = rhs_array_muxed19;
assign soc_litedramcore_interface_bank2_valid = rhs_array_muxed20;
assign roundrobin3_request = {(((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
assign roundrobin3_ce = ((~soc_litedramcore_interface_bank3_valid) & (~soc_litedramcore_interface_bank3_lock));
assign soc_litedramcore_interface_bank3_addr = rhs_array_muxed21;
assign soc_litedramcore_interface_bank3_we = rhs_array_muxed22;
assign soc_litedramcore_interface_bank3_valid = rhs_array_muxed23;
assign roundrobin4_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
assign roundrobin4_ce = ((~soc_litedramcore_interface_bank4_valid) & (~soc_litedramcore_interface_bank4_lock));
assign soc_litedramcore_interface_bank4_addr = rhs_array_muxed24;
assign soc_litedramcore_interface_bank4_we = rhs_array_muxed25;
assign soc_litedramcore_interface_bank4_valid = rhs_array_muxed26;
assign roundrobin5_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
assign roundrobin5_ce = ((~soc_litedramcore_interface_bank5_valid) & (~soc_litedramcore_interface_bank5_lock));
assign soc_litedramcore_interface_bank5_addr = rhs_array_muxed27;
assign soc_litedramcore_interface_bank5_we = rhs_array_muxed28;
assign soc_litedramcore_interface_bank5_valid = rhs_array_muxed29;
assign roundrobin6_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
assign roundrobin6_ce = ((~soc_litedramcore_interface_bank6_valid) & (~soc_litedramcore_interface_bank6_lock));
assign soc_litedramcore_interface_bank6_addr = rhs_array_muxed30;
assign soc_litedramcore_interface_bank6_we = rhs_array_muxed31;
assign soc_litedramcore_interface_bank6_valid = rhs_array_muxed32;
assign roundrobin7_request = {(((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid)};
assign roundrobin7_ce = ((~soc_litedramcore_interface_bank7_valid) & (~soc_litedramcore_interface_bank7_lock));
assign soc_litedramcore_interface_bank7_addr = rhs_array_muxed33;
assign soc_litedramcore_interface_bank7_we = rhs_array_muxed34;
assign soc_litedramcore_interface_bank7_valid = rhs_array_muxed35;
assign soc_user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank0_ready)) | (((roundrobin1_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank1_ready)) | (((roundrobin2_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank2_ready)) | (((roundrobin3_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank3_ready)) | (((roundrobin4_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank4_ready)) | (((roundrobin5_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank5_ready)) | (((roundrobin6_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & soc_litedramcore_interface_bank6_ready)) | (((roundrobin7_grant == 1'd0) & ((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0)))))) & soc_litedramcore_interface_bank7_ready));
assign soc_user_port_wdata_ready = new_master_wdata_ready1;
assign soc_user_port_rdata_valid = new_master_rdata_valid8;
always @(*) begin
soc_litedramcore_interface_wdata_we = 16'd0;
case ({new_master_wdata_ready1})
1'd1: begin
soc_litedramcore_interface_wdata_we = soc_user_port_wdata_payload_we;
end
default: begin
soc_litedramcore_interface_wdata_we = 1'd0;
end
endcase
end
always @(*) begin
soc_litedramcore_interface_wdata = 128'd0;
case ({new_master_wdata_ready1})
1'd1: begin
soc_litedramcore_interface_wdata = soc_user_port_wdata_payload_data;
end
default: begin
soc_litedramcore_interface_wdata = 1'd0;
end
endcase
end
assign soc_user_port_rdata_payload_data = soc_litedramcore_interface_rdata;
assign roundrobin0_grant = 1'd0;
assign roundrobin1_grant = 1'd0;
assign roundrobin2_grant = 1'd0;
assign roundrobin3_grant = 1'd0;
assign roundrobin4_grant = 1'd0;
assign roundrobin5_grant = 1'd0;
assign roundrobin6_grant = 1'd0;
assign roundrobin7_grant = 1'd0;
always @(*) begin
next_state = 2'd0;
next_state = state;
case (state)
1'd1: begin
next_state = 2'd2;
end
2'd2: begin
next_state = 1'd0;
end
default: begin
if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
next_state = 1'd1;
end
end
endcase
end
always @(*) begin
litedramcore_adr_next_value_ce1 = 1'd0;
case (state)
1'd1: begin
litedramcore_adr_next_value_ce1 = 1'd1;
end
2'd2: begin
end
default: begin
if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
litedramcore_adr_next_value_ce1 = 1'd1;
end
end
endcase
end
always @(*) begin
litedramcore_we_next_value2 = 1'd0;
case (state)
1'd1: begin
litedramcore_we_next_value2 = 1'd0;
end
2'd2: begin
end
default: begin
if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
litedramcore_we_next_value2 = (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
end
end
endcase
end
always @(*) begin
litedramcore_we_next_value_ce2 = 1'd0;
case (state)
1'd1: begin
litedramcore_we_next_value_ce2 = 1'd1;
end
2'd2: begin
end
default: begin
if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
litedramcore_we_next_value_ce2 = 1'd1;
end
end
endcase
end
always @(*) begin
litedramcore_wishbone_dat_r = 32'd0;
case (state)
1'd1: begin
end
2'd2: begin
litedramcore_wishbone_dat_r = litedramcore_dat_r;
end
default: begin
end
endcase
end
always @(*) begin
litedramcore_dat_w_next_value0 = 8'd0;
case (state)
1'd1: begin
end
2'd2: begin
end
default: begin
litedramcore_dat_w_next_value0 = litedramcore_wishbone_dat_w;
end
endcase
end
always @(*) begin
litedramcore_dat_w_next_value_ce0 = 1'd0;
case (state)
1'd1: begin
end
2'd2: begin
end
default: begin
litedramcore_dat_w_next_value_ce0 = 1'd1;
end
endcase
end
always @(*) begin
litedramcore_wishbone_ack = 1'd0;
case (state)
1'd1: begin
end
2'd2: begin
litedramcore_wishbone_ack = 1'd1;
end
default: begin
end
endcase
end
always @(*) begin
litedramcore_adr_next_value1 = 14'd0;
case (state)
1'd1: begin
litedramcore_adr_next_value1 = 1'd0;
end
2'd2: begin
end
default: begin
if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
litedramcore_adr_next_value1 = litedramcore_wishbone_adr;
end
end
endcase
end
assign litedramcore_wishbone_adr = soc_wb_bus_adr;
assign litedramcore_wishbone_dat_w = soc_wb_bus_dat_w;
assign soc_wb_bus_dat_r = litedramcore_wishbone_dat_r;
assign litedramcore_wishbone_sel = soc_wb_bus_sel;
assign litedramcore_wishbone_cyc = soc_wb_bus_cyc;
assign litedramcore_wishbone_stb = soc_wb_bus_stb;
assign soc_wb_bus_ack = litedramcore_wishbone_ack;
assign litedramcore_wishbone_we = soc_wb_bus_we;
assign litedramcore_wishbone_cti = soc_wb_bus_cti;
assign litedramcore_wishbone_bte = soc_wb_bus_bte;
assign soc_wb_bus_err = litedramcore_wishbone_err;
assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
always @(*) begin
csrbank0_init_done0_we = 1'd0;
if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
csrbank0_init_done0_we = (~interface0_bank_bus_we);
end
end
always @(*) begin
csrbank0_init_done0_re = 1'd0;
if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
csrbank0_init_done0_re = interface0_bank_bus_we;
end
end
assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
always @(*) begin
csrbank0_init_error0_re = 1'd0;
if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
csrbank0_init_error0_re = interface0_bank_bus_we;
end
end
always @(*) begin
csrbank0_init_error0_we = 1'd0;
if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
csrbank0_init_error0_we = (~interface0_bank_bus_we);
end
end
assign csrbank0_init_done0_w = soc_init_done_storage;
assign csrbank0_init_error0_w = soc_init_error_storage;
assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0];
always @(*) begin
csrbank1_dfii_control0_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
csrbank1_dfii_control0_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_control0_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
csrbank1_dfii_control0_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[5:0];
always @(*) begin
csrbank1_dfii_pi0_command0_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
csrbank1_dfii_pi0_command0_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi0_command0_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
csrbank1_dfii_pi0_command0_we = (~interface1_bank_bus_we);
end
end
assign soc_litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0];
always @(*) begin
soc_litedramcore_phaseinjector0_command_issue_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
soc_litedramcore_phaseinjector0_command_issue_re = interface1_bank_bus_we;
end
end
always @(*) begin
soc_litedramcore_phaseinjector0_command_issue_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
soc_litedramcore_phaseinjector0_command_issue_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi0_address1_r = interface1_bank_bus_dat_w[5:0];
always @(*) begin
csrbank1_dfii_pi0_address1_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
csrbank1_dfii_pi0_address1_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi0_address1_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
csrbank1_dfii_pi0_address1_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi0_address0_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
csrbank1_dfii_pi0_address0_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi0_address0_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
csrbank1_dfii_pi0_address0_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi0_baddress0_r = interface1_bank_bus_dat_w[2:0];
always @(*) begin
csrbank1_dfii_pi0_baddress0_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
csrbank1_dfii_pi0_baddress0_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi0_baddress0_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
csrbank1_dfii_pi0_baddress0_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi0_wrdata3_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi0_wrdata3_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
csrbank1_dfii_pi0_wrdata3_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi0_wrdata3_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
csrbank1_dfii_pi0_wrdata3_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi0_wrdata2_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi0_wrdata2_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
csrbank1_dfii_pi0_wrdata2_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi0_wrdata2_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
csrbank1_dfii_pi0_wrdata2_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi0_wrdata1_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi0_wrdata1_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
csrbank1_dfii_pi0_wrdata1_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi0_wrdata1_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
csrbank1_dfii_pi0_wrdata1_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi0_wrdata0_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
csrbank1_dfii_pi0_wrdata0_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi0_wrdata0_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
csrbank1_dfii_pi0_wrdata0_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi0_rddata3_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi0_rddata3_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
csrbank1_dfii_pi0_rddata3_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi0_rddata3_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
csrbank1_dfii_pi0_rddata3_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi0_rddata2_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi0_rddata2_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
csrbank1_dfii_pi0_rddata2_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi0_rddata2_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
csrbank1_dfii_pi0_rddata2_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi0_rddata1_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi0_rddata1_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
csrbank1_dfii_pi0_rddata1_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi0_rddata1_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
csrbank1_dfii_pi0_rddata1_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi0_rddata0_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi0_rddata0_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin
csrbank1_dfii_pi0_rddata0_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi0_rddata0_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin
csrbank1_dfii_pi0_rddata0_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[5:0];
always @(*) begin
csrbank1_dfii_pi1_command0_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
csrbank1_dfii_pi1_command0_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi1_command0_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
csrbank1_dfii_pi1_command0_we = (~interface1_bank_bus_we);
end
end
assign soc_litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0];
always @(*) begin
soc_litedramcore_phaseinjector1_command_issue_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin
soc_litedramcore_phaseinjector1_command_issue_re = interface1_bank_bus_we;
end
end
always @(*) begin
soc_litedramcore_phaseinjector1_command_issue_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin
soc_litedramcore_phaseinjector1_command_issue_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi1_address1_r = interface1_bank_bus_dat_w[5:0];
always @(*) begin
csrbank1_dfii_pi1_address1_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin
csrbank1_dfii_pi1_address1_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi1_address1_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin
csrbank1_dfii_pi1_address1_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi1_address0_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin
csrbank1_dfii_pi1_address0_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi1_address0_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin
csrbank1_dfii_pi1_address0_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi1_baddress0_r = interface1_bank_bus_dat_w[2:0];
always @(*) begin
csrbank1_dfii_pi1_baddress0_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin
csrbank1_dfii_pi1_baddress0_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi1_baddress0_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin
csrbank1_dfii_pi1_baddress0_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi1_wrdata3_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi1_wrdata3_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin
csrbank1_dfii_pi1_wrdata3_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi1_wrdata3_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin
csrbank1_dfii_pi1_wrdata3_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi1_wrdata2_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi1_wrdata2_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd20))) begin
csrbank1_dfii_pi1_wrdata2_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi1_wrdata2_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd20))) begin
csrbank1_dfii_pi1_wrdata2_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi1_wrdata1_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi1_wrdata1_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin
csrbank1_dfii_pi1_wrdata1_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi1_wrdata1_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin
csrbank1_dfii_pi1_wrdata1_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi1_wrdata0_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin
csrbank1_dfii_pi1_wrdata0_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi1_wrdata0_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin
csrbank1_dfii_pi1_wrdata0_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi1_rddata3_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi1_rddata3_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin
csrbank1_dfii_pi1_rddata3_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi1_rddata3_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin
csrbank1_dfii_pi1_rddata3_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi1_rddata2_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi1_rddata2_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd24))) begin
csrbank1_dfii_pi1_rddata2_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi1_rddata2_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd24))) begin
csrbank1_dfii_pi1_rddata2_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi1_rddata1_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi1_rddata1_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd25))) begin
csrbank1_dfii_pi1_rddata1_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi1_rddata1_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd25))) begin
csrbank1_dfii_pi1_rddata1_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi1_rddata0_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi1_rddata0_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd26))) begin
csrbank1_dfii_pi1_rddata0_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi1_rddata0_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd26))) begin
csrbank1_dfii_pi1_rddata0_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[5:0];
always @(*) begin
csrbank1_dfii_pi2_command0_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd27))) begin
csrbank1_dfii_pi2_command0_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi2_command0_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd27))) begin
csrbank1_dfii_pi2_command0_we = (~interface1_bank_bus_we);
end
end
assign soc_litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0];
always @(*) begin
soc_litedramcore_phaseinjector2_command_issue_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd28))) begin
soc_litedramcore_phaseinjector2_command_issue_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
soc_litedramcore_phaseinjector2_command_issue_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd28))) begin
soc_litedramcore_phaseinjector2_command_issue_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi2_address1_r = interface1_bank_bus_dat_w[5:0];
always @(*) begin
csrbank1_dfii_pi2_address1_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd29))) begin
csrbank1_dfii_pi2_address1_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi2_address1_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd29))) begin
csrbank1_dfii_pi2_address1_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi2_address0_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd30))) begin
csrbank1_dfii_pi2_address0_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi2_address0_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd30))) begin
csrbank1_dfii_pi2_address0_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi2_baddress0_r = interface1_bank_bus_dat_w[2:0];
always @(*) begin
csrbank1_dfii_pi2_baddress0_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd31))) begin
csrbank1_dfii_pi2_baddress0_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi2_baddress0_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd31))) begin
csrbank1_dfii_pi2_baddress0_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi2_wrdata3_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi2_wrdata3_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd32))) begin
csrbank1_dfii_pi2_wrdata3_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi2_wrdata3_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd32))) begin
csrbank1_dfii_pi2_wrdata3_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi2_wrdata2_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi2_wrdata2_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd33))) begin
csrbank1_dfii_pi2_wrdata2_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi2_wrdata2_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd33))) begin
csrbank1_dfii_pi2_wrdata2_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi2_wrdata1_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi2_wrdata1_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd34))) begin
csrbank1_dfii_pi2_wrdata1_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi2_wrdata1_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd34))) begin
csrbank1_dfii_pi2_wrdata1_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi2_wrdata0_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd35))) begin
csrbank1_dfii_pi2_wrdata0_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi2_wrdata0_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd35))) begin
csrbank1_dfii_pi2_wrdata0_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi2_rddata3_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi2_rddata3_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd36))) begin
csrbank1_dfii_pi2_rddata3_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi2_rddata3_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd36))) begin
csrbank1_dfii_pi2_rddata3_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi2_rddata2_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi2_rddata2_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd37))) begin
csrbank1_dfii_pi2_rddata2_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi2_rddata2_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd37))) begin
csrbank1_dfii_pi2_rddata2_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi2_rddata1_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi2_rddata1_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd38))) begin
csrbank1_dfii_pi2_rddata1_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi2_rddata1_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd38))) begin
csrbank1_dfii_pi2_rddata1_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi2_rddata0_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi2_rddata0_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd39))) begin
csrbank1_dfii_pi2_rddata0_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi2_rddata0_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd39))) begin
csrbank1_dfii_pi2_rddata0_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[5:0];
always @(*) begin
csrbank1_dfii_pi3_command0_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd40))) begin
csrbank1_dfii_pi3_command0_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi3_command0_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd40))) begin
csrbank1_dfii_pi3_command0_we = (~interface1_bank_bus_we);
end
end
assign soc_litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0];
always @(*) begin
soc_litedramcore_phaseinjector3_command_issue_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd41))) begin
soc_litedramcore_phaseinjector3_command_issue_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
soc_litedramcore_phaseinjector3_command_issue_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd41))) begin
soc_litedramcore_phaseinjector3_command_issue_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi3_address1_r = interface1_bank_bus_dat_w[5:0];
always @(*) begin
csrbank1_dfii_pi3_address1_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd42))) begin
csrbank1_dfii_pi3_address1_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi3_address1_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd42))) begin
csrbank1_dfii_pi3_address1_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi3_address0_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd43))) begin
csrbank1_dfii_pi3_address0_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi3_address0_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd43))) begin
csrbank1_dfii_pi3_address0_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi3_baddress0_r = interface1_bank_bus_dat_w[2:0];
always @(*) begin
csrbank1_dfii_pi3_baddress0_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd44))) begin
csrbank1_dfii_pi3_baddress0_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi3_baddress0_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd44))) begin
csrbank1_dfii_pi3_baddress0_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi3_wrdata3_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi3_wrdata3_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd45))) begin
csrbank1_dfii_pi3_wrdata3_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi3_wrdata3_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd45))) begin
csrbank1_dfii_pi3_wrdata3_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi3_wrdata2_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi3_wrdata2_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd46))) begin
csrbank1_dfii_pi3_wrdata2_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi3_wrdata2_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd46))) begin
csrbank1_dfii_pi3_wrdata2_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi3_wrdata1_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi3_wrdata1_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd47))) begin
csrbank1_dfii_pi3_wrdata1_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi3_wrdata1_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd47))) begin
csrbank1_dfii_pi3_wrdata1_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi3_wrdata0_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd48))) begin
csrbank1_dfii_pi3_wrdata0_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi3_wrdata0_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd48))) begin
csrbank1_dfii_pi3_wrdata0_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi3_rddata3_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi3_rddata3_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd49))) begin
csrbank1_dfii_pi3_rddata3_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi3_rddata3_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd49))) begin
csrbank1_dfii_pi3_rddata3_we = (~interface1_bank_bus_we);
end
end
assign csrbank1_dfii_pi3_rddata2_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi3_rddata2_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd50))) begin
csrbank1_dfii_pi3_rddata2_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi3_rddata2_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd50))) begin
csrbank1_dfii_pi3_rddata2_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi3_rddata1_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi3_rddata1_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd51))) begin
csrbank1_dfii_pi3_rddata1_we = (~interface1_bank_bus_we);
end
end
always @(*) begin
csrbank1_dfii_pi3_rddata1_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd51))) begin
csrbank1_dfii_pi3_rddata1_re = interface1_bank_bus_we;
end
end
assign csrbank1_dfii_pi3_rddata0_r = interface1_bank_bus_dat_w[7:0];
always @(*) begin
csrbank1_dfii_pi3_rddata0_re = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd52))) begin
csrbank1_dfii_pi3_rddata0_re = interface1_bank_bus_we;
end
end
always @(*) begin
csrbank1_dfii_pi3_rddata0_we = 1'd0;
if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd52))) begin
csrbank1_dfii_pi3_rddata0_we = (~interface1_bank_bus_we);
end
end
assign soc_litedramcore_sel = soc_litedramcore_storage[0];
assign soc_litedramcore_cke = soc_litedramcore_storage[1];
assign soc_litedramcore_odt = soc_litedramcore_storage[2];
assign soc_litedramcore_reset_n = soc_litedramcore_storage[3];
assign csrbank1_dfii_control0_w = soc_litedramcore_storage[3:0];
assign csrbank1_dfii_pi0_command0_w = soc_litedramcore_phaseinjector0_command_storage[5:0];
assign csrbank1_dfii_pi0_address1_w = soc_litedramcore_phaseinjector0_address_storage[13:8];
assign csrbank1_dfii_pi0_address0_w = soc_litedramcore_phaseinjector0_address_storage[7:0];
assign csrbank1_dfii_pi0_baddress0_w = soc_litedramcore_phaseinjector0_baddress_storage[2:0];
assign csrbank1_dfii_pi0_wrdata3_w = soc_litedramcore_phaseinjector0_wrdata_storage[31:24];
assign csrbank1_dfii_pi0_wrdata2_w = soc_litedramcore_phaseinjector0_wrdata_storage[23:16];
assign csrbank1_dfii_pi0_wrdata1_w = soc_litedramcore_phaseinjector0_wrdata_storage[15:8];
assign csrbank1_dfii_pi0_wrdata0_w = soc_litedramcore_phaseinjector0_wrdata_storage[7:0];
assign csrbank1_dfii_pi0_rddata3_w = soc_litedramcore_phaseinjector0_rddata_status[31:24];
assign csrbank1_dfii_pi0_rddata2_w = soc_litedramcore_phaseinjector0_rddata_status[23:16];
assign csrbank1_dfii_pi0_rddata1_w = soc_litedramcore_phaseinjector0_rddata_status[15:8];
assign csrbank1_dfii_pi0_rddata0_w = soc_litedramcore_phaseinjector0_rddata_status[7:0];
assign soc_litedramcore_phaseinjector0_rddata_we = csrbank1_dfii_pi0_rddata0_we;
assign csrbank1_dfii_pi1_command0_w = soc_litedramcore_phaseinjector1_command_storage[5:0];
assign csrbank1_dfii_pi1_address1_w = soc_litedramcore_phaseinjector1_address_storage[13:8];
assign csrbank1_dfii_pi1_address0_w = soc_litedramcore_phaseinjector1_address_storage[7:0];
assign csrbank1_dfii_pi1_baddress0_w = soc_litedramcore_phaseinjector1_baddress_storage[2:0];
assign csrbank1_dfii_pi1_wrdata3_w = soc_litedramcore_phaseinjector1_wrdata_storage[31:24];
assign csrbank1_dfii_pi1_wrdata2_w = soc_litedramcore_phaseinjector1_wrdata_storage[23:16];
assign csrbank1_dfii_pi1_wrdata1_w = soc_litedramcore_phaseinjector1_wrdata_storage[15:8];
assign csrbank1_dfii_pi1_wrdata0_w = soc_litedramcore_phaseinjector1_wrdata_storage[7:0];
assign csrbank1_dfii_pi1_rddata3_w = soc_litedramcore_phaseinjector1_rddata_status[31:24];
assign csrbank1_dfii_pi1_rddata2_w = soc_litedramcore_phaseinjector1_rddata_status[23:16];
assign csrbank1_dfii_pi1_rddata1_w = soc_litedramcore_phaseinjector1_rddata_status[15:8];
assign csrbank1_dfii_pi1_rddata0_w = soc_litedramcore_phaseinjector1_rddata_status[7:0];
assign soc_litedramcore_phaseinjector1_rddata_we = csrbank1_dfii_pi1_rddata0_we;
assign csrbank1_dfii_pi2_command0_w = soc_litedramcore_phaseinjector2_command_storage[5:0];
assign csrbank1_dfii_pi2_address1_w = soc_litedramcore_phaseinjector2_address_storage[13:8];
assign csrbank1_dfii_pi2_address0_w = soc_litedramcore_phaseinjector2_address_storage[7:0];
assign csrbank1_dfii_pi2_baddress0_w = soc_litedramcore_phaseinjector2_baddress_storage[2:0];
assign csrbank1_dfii_pi2_wrdata3_w = soc_litedramcore_phaseinjector2_wrdata_storage[31:24];
assign csrbank1_dfii_pi2_wrdata2_w = soc_litedramcore_phaseinjector2_wrdata_storage[23:16];
assign csrbank1_dfii_pi2_wrdata1_w = soc_litedramcore_phaseinjector2_wrdata_storage[15:8];
assign csrbank1_dfii_pi2_wrdata0_w = soc_litedramcore_phaseinjector2_wrdata_storage[7:0];
assign csrbank1_dfii_pi2_rddata3_w = soc_litedramcore_phaseinjector2_rddata_status[31:24];
assign csrbank1_dfii_pi2_rddata2_w = soc_litedramcore_phaseinjector2_rddata_status[23:16];
assign csrbank1_dfii_pi2_rddata1_w = soc_litedramcore_phaseinjector2_rddata_status[15:8];
assign csrbank1_dfii_pi2_rddata0_w = soc_litedramcore_phaseinjector2_rddata_status[7:0];
assign soc_litedramcore_phaseinjector2_rddata_we = csrbank1_dfii_pi2_rddata0_we;
assign csrbank1_dfii_pi3_command0_w = soc_litedramcore_phaseinjector3_command_storage[5:0];
assign csrbank1_dfii_pi3_address1_w = soc_litedramcore_phaseinjector3_address_storage[13:8];
assign csrbank1_dfii_pi3_address0_w = soc_litedramcore_phaseinjector3_address_storage[7:0];
assign csrbank1_dfii_pi3_baddress0_w = soc_litedramcore_phaseinjector3_baddress_storage[2:0];
assign csrbank1_dfii_pi3_wrdata3_w = soc_litedramcore_phaseinjector3_wrdata_storage[31:24];
assign csrbank1_dfii_pi3_wrdata2_w = soc_litedramcore_phaseinjector3_wrdata_storage[23:16];
assign csrbank1_dfii_pi3_wrdata1_w = soc_litedramcore_phaseinjector3_wrdata_storage[15:8];
assign csrbank1_dfii_pi3_wrdata0_w = soc_litedramcore_phaseinjector3_wrdata_storage[7:0];
assign csrbank1_dfii_pi3_rddata3_w = soc_litedramcore_phaseinjector3_rddata_status[31:24];
assign csrbank1_dfii_pi3_rddata2_w = soc_litedramcore_phaseinjector3_rddata_status[23:16];
assign csrbank1_dfii_pi3_rddata1_w = soc_litedramcore_phaseinjector3_rddata_status[15:8];
assign csrbank1_dfii_pi3_rddata0_w = soc_litedramcore_phaseinjector3_rddata_status[7:0];
assign soc_litedramcore_phaseinjector3_rddata_we = csrbank1_dfii_pi3_rddata0_we;
assign csr_interconnect_adr = litedramcore_adr;
assign csr_interconnect_we = litedramcore_we;
assign csr_interconnect_dat_w = litedramcore_dat_w;
assign litedramcore_dat_r = csr_interconnect_dat_r;
assign interface0_bank_bus_adr = csr_interconnect_adr;
assign interface1_bank_bus_adr = csr_interconnect_adr;
assign interface0_bank_bus_we = csr_interconnect_we;
assign interface1_bank_bus_we = csr_interconnect_we;
assign interface0_bank_bus_dat_w = csr_interconnect_dat_w;
assign interface1_bank_bus_dat_w = csr_interconnect_dat_w;
assign csr_interconnect_dat_r = (interface0_bank_bus_dat_r | interface1_bank_bus_dat_r);
assign slice_proxy0 = ((soc_ddrphy_bankmodel0_row * 11'd1024) | soc_ddrphy_bankmodel0_write_col);
assign slice_proxy1 = ((soc_ddrphy_bankmodel0_row * 11'd1024) | soc_ddrphy_bankmodel0_read_col);
assign slice_proxy2 = ((soc_ddrphy_bankmodel1_row * 11'd1024) | soc_ddrphy_bankmodel1_write_col);
assign slice_proxy3 = ((soc_ddrphy_bankmodel1_row * 11'd1024) | soc_ddrphy_bankmodel1_read_col);
assign slice_proxy4 = ((soc_ddrphy_bankmodel2_row * 11'd1024) | soc_ddrphy_bankmodel2_write_col);
assign slice_proxy5 = ((soc_ddrphy_bankmodel2_row * 11'd1024) | soc_ddrphy_bankmodel2_read_col);
assign slice_proxy6 = ((soc_ddrphy_bankmodel3_row * 11'd1024) | soc_ddrphy_bankmodel3_write_col);
assign slice_proxy7 = ((soc_ddrphy_bankmodel3_row * 11'd1024) | soc_ddrphy_bankmodel3_read_col);
assign slice_proxy8 = ((soc_ddrphy_bankmodel4_row * 11'd1024) | soc_ddrphy_bankmodel4_write_col);
assign slice_proxy9 = ((soc_ddrphy_bankmodel4_row * 11'd1024) | soc_ddrphy_bankmodel4_read_col);
assign slice_proxy10 = ((soc_ddrphy_bankmodel5_row * 11'd1024) | soc_ddrphy_bankmodel5_write_col);
assign slice_proxy11 = ((soc_ddrphy_bankmodel5_row * 11'd1024) | soc_ddrphy_bankmodel5_read_col);
assign slice_proxy12 = ((soc_ddrphy_bankmodel6_row * 11'd1024) | soc_ddrphy_bankmodel6_write_col);
assign slice_proxy13 = ((soc_ddrphy_bankmodel6_row * 11'd1024) | soc_ddrphy_bankmodel6_read_col);
assign slice_proxy14 = ((soc_ddrphy_bankmodel7_row * 11'd1024) | soc_ddrphy_bankmodel7_write_col);
assign slice_proxy15 = ((soc_ddrphy_bankmodel7_row * 11'd1024) | soc_ddrphy_bankmodel7_read_col);
always @(*) begin
rhs_array_muxed0 = 1'd0;
case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[0];
end
1'd1: begin
rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[1];
end
2'd2: begin
rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[2];
end
2'd3: begin
rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[3];
end
3'd4: begin
rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[4];
end
3'd5: begin
rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[5];
end
3'd6: begin
rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[6];
end
default: begin
rhs_array_muxed0 = soc_litedramcore_choose_cmd_valids[7];
end
endcase
end
always @(*) begin
rhs_array_muxed1 = 14'd0;
case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
rhs_array_muxed1 = soc_litedramcore_bankmachine0_cmd_payload_a;
end
1'd1: begin
rhs_array_muxed1 = soc_litedramcore_bankmachine1_cmd_payload_a;
end
2'd2: begin
rhs_array_muxed1 = soc_litedramcore_bankmachine2_cmd_payload_a;
end
2'd3: begin
rhs_array_muxed1 = soc_litedramcore_bankmachine3_cmd_payload_a;
end
3'd4: begin
rhs_array_muxed1 = soc_litedramcore_bankmachine4_cmd_payload_a;
end
3'd5: begin
rhs_array_muxed1 = soc_litedramcore_bankmachine5_cmd_payload_a;
end
3'd6: begin
rhs_array_muxed1 = soc_litedramcore_bankmachine6_cmd_payload_a;
end
default: begin
rhs_array_muxed1 = soc_litedramcore_bankmachine7_cmd_payload_a;
end
endcase
end
always @(*) begin
rhs_array_muxed2 = 3'd0;
case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
rhs_array_muxed2 = soc_litedramcore_bankmachine0_cmd_payload_ba;
end
1'd1: begin
rhs_array_muxed2 = soc_litedramcore_bankmachine1_cmd_payload_ba;
end
2'd2: begin
rhs_array_muxed2 = soc_litedramcore_bankmachine2_cmd_payload_ba;
end
2'd3: begin
rhs_array_muxed2 = soc_litedramcore_bankmachine3_cmd_payload_ba;
end
3'd4: begin
rhs_array_muxed2 = soc_litedramcore_bankmachine4_cmd_payload_ba;
end
3'd5: begin
rhs_array_muxed2 = soc_litedramcore_bankmachine5_cmd_payload_ba;
end
3'd6: begin
rhs_array_muxed2 = soc_litedramcore_bankmachine6_cmd_payload_ba;
end
default: begin
rhs_array_muxed2 = soc_litedramcore_bankmachine7_cmd_payload_ba;
end
endcase
end
always @(*) begin
rhs_array_muxed3 = 1'd0;
case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
rhs_array_muxed3 = soc_litedramcore_bankmachine0_cmd_payload_is_read;
end
1'd1: begin
rhs_array_muxed3 = soc_litedramcore_bankmachine1_cmd_payload_is_read;
end
2'd2: begin
rhs_array_muxed3 = soc_litedramcore_bankmachine2_cmd_payload_is_read;
end
2'd3: begin
rhs_array_muxed3 = soc_litedramcore_bankmachine3_cmd_payload_is_read;
end
3'd4: begin
rhs_array_muxed3 = soc_litedramcore_bankmachine4_cmd_payload_is_read;
end
3'd5: begin
rhs_array_muxed3 = soc_litedramcore_bankmachine5_cmd_payload_is_read;
end
3'd6: begin
rhs_array_muxed3 = soc_litedramcore_bankmachine6_cmd_payload_is_read;
end
default: begin
rhs_array_muxed3 = soc_litedramcore_bankmachine7_cmd_payload_is_read;
end
endcase
end
always @(*) begin
rhs_array_muxed4 = 1'd0;
case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
rhs_array_muxed4 = soc_litedramcore_bankmachine0_cmd_payload_is_write;
end
1'd1: begin
rhs_array_muxed4 = soc_litedramcore_bankmachine1_cmd_payload_is_write;
end
2'd2: begin
rhs_array_muxed4 = soc_litedramcore_bankmachine2_cmd_payload_is_write;
end
2'd3: begin
rhs_array_muxed4 = soc_litedramcore_bankmachine3_cmd_payload_is_write;
end
3'd4: begin
rhs_array_muxed4 = soc_litedramcore_bankmachine4_cmd_payload_is_write;
end
3'd5: begin
rhs_array_muxed4 = soc_litedramcore_bankmachine5_cmd_payload_is_write;
end
3'd6: begin
rhs_array_muxed4 = soc_litedramcore_bankmachine6_cmd_payload_is_write;
end
default: begin
rhs_array_muxed4 = soc_litedramcore_bankmachine7_cmd_payload_is_write;
end
endcase
end
always @(*) begin
rhs_array_muxed5 = 1'd0;
case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
rhs_array_muxed5 = soc_litedramcore_bankmachine0_cmd_payload_is_cmd;
end
1'd1: begin
rhs_array_muxed5 = soc_litedramcore_bankmachine1_cmd_payload_is_cmd;
end
2'd2: begin
rhs_array_muxed5 = soc_litedramcore_bankmachine2_cmd_payload_is_cmd;
end
2'd3: begin
rhs_array_muxed5 = soc_litedramcore_bankmachine3_cmd_payload_is_cmd;
end
3'd4: begin
rhs_array_muxed5 = soc_litedramcore_bankmachine4_cmd_payload_is_cmd;
end
3'd5: begin
rhs_array_muxed5 = soc_litedramcore_bankmachine5_cmd_payload_is_cmd;
end
3'd6: begin
rhs_array_muxed5 = soc_litedramcore_bankmachine6_cmd_payload_is_cmd;
end
default: begin
rhs_array_muxed5 = soc_litedramcore_bankmachine7_cmd_payload_is_cmd;
end
endcase
end
always @(*) begin
t_array_muxed0 = 1'd0;
case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
t_array_muxed0 = soc_litedramcore_bankmachine0_cmd_payload_cas;
end
1'd1: begin
t_array_muxed0 = soc_litedramcore_bankmachine1_cmd_payload_cas;
end
2'd2: begin
t_array_muxed0 = soc_litedramcore_bankmachine2_cmd_payload_cas;
end
2'd3: begin
t_array_muxed0 = soc_litedramcore_bankmachine3_cmd_payload_cas;
end
3'd4: begin
t_array_muxed0 = soc_litedramcore_bankmachine4_cmd_payload_cas;
end
3'd5: begin
t_array_muxed0 = soc_litedramcore_bankmachine5_cmd_payload_cas;
end
3'd6: begin
t_array_muxed0 = soc_litedramcore_bankmachine6_cmd_payload_cas;
end
default: begin
t_array_muxed0 = soc_litedramcore_bankmachine7_cmd_payload_cas;
end
endcase
end
always @(*) begin
t_array_muxed1 = 1'd0;
case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
t_array_muxed1 = soc_litedramcore_bankmachine0_cmd_payload_ras;
end
1'd1: begin
t_array_muxed1 = soc_litedramcore_bankmachine1_cmd_payload_ras;
end
2'd2: begin
t_array_muxed1 = soc_litedramcore_bankmachine2_cmd_payload_ras;
end
2'd3: begin
t_array_muxed1 = soc_litedramcore_bankmachine3_cmd_payload_ras;
end
3'd4: begin
t_array_muxed1 = soc_litedramcore_bankmachine4_cmd_payload_ras;
end
3'd5: begin
t_array_muxed1 = soc_litedramcore_bankmachine5_cmd_payload_ras;
end
3'd6: begin
t_array_muxed1 = soc_litedramcore_bankmachine6_cmd_payload_ras;
end
default: begin
t_array_muxed1 = soc_litedramcore_bankmachine7_cmd_payload_ras;
end
endcase
end
always @(*) begin
t_array_muxed2 = 1'd0;
case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
t_array_muxed2 = soc_litedramcore_bankmachine0_cmd_payload_we;
end
1'd1: begin
t_array_muxed2 = soc_litedramcore_bankmachine1_cmd_payload_we;
end
2'd2: begin
t_array_muxed2 = soc_litedramcore_bankmachine2_cmd_payload_we;
end
2'd3: begin
t_array_muxed2 = soc_litedramcore_bankmachine3_cmd_payload_we;
end
3'd4: begin
t_array_muxed2 = soc_litedramcore_bankmachine4_cmd_payload_we;
end
3'd5: begin
t_array_muxed2 = soc_litedramcore_bankmachine5_cmd_payload_we;
end
3'd6: begin
t_array_muxed2 = soc_litedramcore_bankmachine6_cmd_payload_we;
end
default: begin
t_array_muxed2 = soc_litedramcore_bankmachine7_cmd_payload_we;
end
endcase
end
always @(*) begin
rhs_array_muxed6 = 1'd0;
case (soc_litedramcore_choose_req_grant)
1'd0: begin
rhs_array_muxed6 = soc_litedramcore_choose_req_valids[0];
end
1'd1: begin
rhs_array_muxed6 = soc_litedramcore_choose_req_valids[1];
end
2'd2: begin
rhs_array_muxed6 = soc_litedramcore_choose_req_valids[2];
end
2'd3: begin
rhs_array_muxed6 = soc_litedramcore_choose_req_valids[3];
end
3'd4: begin
rhs_array_muxed6 = soc_litedramcore_choose_req_valids[4];
end
3'd5: begin
rhs_array_muxed6 = soc_litedramcore_choose_req_valids[5];
end
3'd6: begin
rhs_array_muxed6 = soc_litedramcore_choose_req_valids[6];
end
default: begin
rhs_array_muxed6 = soc_litedramcore_choose_req_valids[7];
end
endcase
end
always @(*) begin
rhs_array_muxed7 = 14'd0;
case (soc_litedramcore_choose_req_grant)
1'd0: begin
rhs_array_muxed7 = soc_litedramcore_bankmachine0_cmd_payload_a;
end
1'd1: begin
rhs_array_muxed7 = soc_litedramcore_bankmachine1_cmd_payload_a;
end
2'd2: begin
rhs_array_muxed7 = soc_litedramcore_bankmachine2_cmd_payload_a;
end
2'd3: begin
rhs_array_muxed7 = soc_litedramcore_bankmachine3_cmd_payload_a;
end
3'd4: begin
rhs_array_muxed7 = soc_litedramcore_bankmachine4_cmd_payload_a;
end
3'd5: begin
rhs_array_muxed7 = soc_litedramcore_bankmachine5_cmd_payload_a;
end
3'd6: begin
rhs_array_muxed7 = soc_litedramcore_bankmachine6_cmd_payload_a;
end
default: begin
rhs_array_muxed7 = soc_litedramcore_bankmachine7_cmd_payload_a;
end
endcase
end
always @(*) begin
rhs_array_muxed8 = 3'd0;
case (soc_litedramcore_choose_req_grant)
1'd0: begin
rhs_array_muxed8 = soc_litedramcore_bankmachine0_cmd_payload_ba;
end
1'd1: begin
rhs_array_muxed8 = soc_litedramcore_bankmachine1_cmd_payload_ba;
end
2'd2: begin
rhs_array_muxed8 = soc_litedramcore_bankmachine2_cmd_payload_ba;
end
2'd3: begin
rhs_array_muxed8 = soc_litedramcore_bankmachine3_cmd_payload_ba;
end
3'd4: begin
rhs_array_muxed8 = soc_litedramcore_bankmachine4_cmd_payload_ba;
end
3'd5: begin
rhs_array_muxed8 = soc_litedramcore_bankmachine5_cmd_payload_ba;
end
3'd6: begin
rhs_array_muxed8 = soc_litedramcore_bankmachine6_cmd_payload_ba;
end
default: begin
rhs_array_muxed8 = soc_litedramcore_bankmachine7_cmd_payload_ba;
end
endcase
end
always @(*) begin
rhs_array_muxed9 = 1'd0;
case (soc_litedramcore_choose_req_grant)
1'd0: begin
rhs_array_muxed9 = soc_litedramcore_bankmachine0_cmd_payload_is_read;
end
1'd1: begin
rhs_array_muxed9 = soc_litedramcore_bankmachine1_cmd_payload_is_read;
end
2'd2: begin
rhs_array_muxed9 = soc_litedramcore_bankmachine2_cmd_payload_is_read;
end
2'd3: begin
rhs_array_muxed9 = soc_litedramcore_bankmachine3_cmd_payload_is_read;
end
3'd4: begin
rhs_array_muxed9 = soc_litedramcore_bankmachine4_cmd_payload_is_read;
end
3'd5: begin
rhs_array_muxed9 = soc_litedramcore_bankmachine5_cmd_payload_is_read;
end
3'd6: begin
rhs_array_muxed9 = soc_litedramcore_bankmachine6_cmd_payload_is_read;
end
default: begin
rhs_array_muxed9 = soc_litedramcore_bankmachine7_cmd_payload_is_read;
end
endcase
end
always @(*) begin
rhs_array_muxed10 = 1'd0;
case (soc_litedramcore_choose_req_grant)
1'd0: begin
rhs_array_muxed10 = soc_litedramcore_bankmachine0_cmd_payload_is_write;
end
1'd1: begin
rhs_array_muxed10 = soc_litedramcore_bankmachine1_cmd_payload_is_write;
end
2'd2: begin
rhs_array_muxed10 = soc_litedramcore_bankmachine2_cmd_payload_is_write;
end
2'd3: begin
rhs_array_muxed10 = soc_litedramcore_bankmachine3_cmd_payload_is_write;
end
3'd4: begin
rhs_array_muxed10 = soc_litedramcore_bankmachine4_cmd_payload_is_write;
end
3'd5: begin
rhs_array_muxed10 = soc_litedramcore_bankmachine5_cmd_payload_is_write;
end
3'd6: begin
rhs_array_muxed10 = soc_litedramcore_bankmachine6_cmd_payload_is_write;
end
default: begin
rhs_array_muxed10 = soc_litedramcore_bankmachine7_cmd_payload_is_write;
end
endcase
end
always @(*) begin
rhs_array_muxed11 = 1'd0;
case (soc_litedramcore_choose_req_grant)
1'd0: begin
rhs_array_muxed11 = soc_litedramcore_bankmachine0_cmd_payload_is_cmd;
end
1'd1: begin
rhs_array_muxed11 = soc_litedramcore_bankmachine1_cmd_payload_is_cmd;
end
2'd2: begin
rhs_array_muxed11 = soc_litedramcore_bankmachine2_cmd_payload_is_cmd;
end
2'd3: begin
rhs_array_muxed11 = soc_litedramcore_bankmachine3_cmd_payload_is_cmd;
end
3'd4: begin
rhs_array_muxed11 = soc_litedramcore_bankmachine4_cmd_payload_is_cmd;
end
3'd5: begin
rhs_array_muxed11 = soc_litedramcore_bankmachine5_cmd_payload_is_cmd;
end
3'd6: begin
rhs_array_muxed11 = soc_litedramcore_bankmachine6_cmd_payload_is_cmd;
end
default: begin
rhs_array_muxed11 = soc_litedramcore_bankmachine7_cmd_payload_is_cmd;
end
endcase
end
always @(*) begin
t_array_muxed3 = 1'd0;
case (soc_litedramcore_choose_req_grant)
1'd0: begin
t_array_muxed3 = soc_litedramcore_bankmachine0_cmd_payload_cas;
end
1'd1: begin
t_array_muxed3 = soc_litedramcore_bankmachine1_cmd_payload_cas;
end
2'd2: begin
t_array_muxed3 = soc_litedramcore_bankmachine2_cmd_payload_cas;
end
2'd3: begin
t_array_muxed3 = soc_litedramcore_bankmachine3_cmd_payload_cas;
end
3'd4: begin
t_array_muxed3 = soc_litedramcore_bankmachine4_cmd_payload_cas;
end
3'd5: begin
t_array_muxed3 = soc_litedramcore_bankmachine5_cmd_payload_cas;
end
3'd6: begin
t_array_muxed3 = soc_litedramcore_bankmachine6_cmd_payload_cas;
end
default: begin
t_array_muxed3 = soc_litedramcore_bankmachine7_cmd_payload_cas;
end
endcase
end
always @(*) begin
t_array_muxed4 = 1'd0;
case (soc_litedramcore_choose_req_grant)
1'd0: begin
t_array_muxed4 = soc_litedramcore_bankmachine0_cmd_payload_ras;
end
1'd1: begin
t_array_muxed4 = soc_litedramcore_bankmachine1_cmd_payload_ras;
end
2'd2: begin
t_array_muxed4 = soc_litedramcore_bankmachine2_cmd_payload_ras;
end
2'd3: begin
t_array_muxed4 = soc_litedramcore_bankmachine3_cmd_payload_ras;
end
3'd4: begin
t_array_muxed4 = soc_litedramcore_bankmachine4_cmd_payload_ras;
end
3'd5: begin
t_array_muxed4 = soc_litedramcore_bankmachine5_cmd_payload_ras;
end
3'd6: begin
t_array_muxed4 = soc_litedramcore_bankmachine6_cmd_payload_ras;
end
default: begin
t_array_muxed4 = soc_litedramcore_bankmachine7_cmd_payload_ras;
end
endcase
end
always @(*) begin
t_array_muxed5 = 1'd0;
case (soc_litedramcore_choose_req_grant)
1'd0: begin
t_array_muxed5 = soc_litedramcore_bankmachine0_cmd_payload_we;
end
1'd1: begin
t_array_muxed5 = soc_litedramcore_bankmachine1_cmd_payload_we;
end
2'd2: begin
t_array_muxed5 = soc_litedramcore_bankmachine2_cmd_payload_we;
end
2'd3: begin
t_array_muxed5 = soc_litedramcore_bankmachine3_cmd_payload_we;
end
3'd4: begin
t_array_muxed5 = soc_litedramcore_bankmachine4_cmd_payload_we;
end
3'd5: begin
t_array_muxed5 = soc_litedramcore_bankmachine5_cmd_payload_we;
end
3'd6: begin
t_array_muxed5 = soc_litedramcore_bankmachine6_cmd_payload_we;
end
default: begin
t_array_muxed5 = soc_litedramcore_bankmachine7_cmd_payload_we;
end
endcase
end
always @(*) begin
rhs_array_muxed12 = 21'd0;
case (roundrobin0_grant)
default: begin
rhs_array_muxed12 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
rhs_array_muxed13 = 1'd0;
case (roundrobin0_grant)
default: begin
rhs_array_muxed13 = soc_user_port_cmd_payload_we;
end
endcase
end
always @(*) begin
rhs_array_muxed14 = 1'd0;
case (roundrobin0_grant)
default: begin
rhs_array_muxed14 = (((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
end
endcase
end
always @(*) begin
rhs_array_muxed15 = 21'd0;
case (roundrobin1_grant)
default: begin
rhs_array_muxed15 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
rhs_array_muxed16 = 1'd0;
case (roundrobin1_grant)
default: begin
rhs_array_muxed16 = soc_user_port_cmd_payload_we;
end
endcase
end
always @(*) begin
rhs_array_muxed17 = 1'd0;
case (roundrobin1_grant)
default: begin
rhs_array_muxed17 = (((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
end
endcase
end
always @(*) begin
rhs_array_muxed18 = 21'd0;
case (roundrobin2_grant)
default: begin
rhs_array_muxed18 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
rhs_array_muxed19 = 1'd0;
case (roundrobin2_grant)
default: begin
rhs_array_muxed19 = soc_user_port_cmd_payload_we;
end
endcase
end
always @(*) begin
rhs_array_muxed20 = 1'd0;
case (roundrobin2_grant)
default: begin
rhs_array_muxed20 = (((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
end
endcase
end
always @(*) begin
rhs_array_muxed21 = 21'd0;
case (roundrobin3_grant)
default: begin
rhs_array_muxed21 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
rhs_array_muxed22 = 1'd0;
case (roundrobin3_grant)
default: begin
rhs_array_muxed22 = soc_user_port_cmd_payload_we;
end
endcase
end
always @(*) begin
rhs_array_muxed23 = 1'd0;
case (roundrobin3_grant)
default: begin
rhs_array_muxed23 = (((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
end
endcase
end
always @(*) begin
rhs_array_muxed24 = 21'd0;
case (roundrobin4_grant)
default: begin
rhs_array_muxed24 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
rhs_array_muxed25 = 1'd0;
case (roundrobin4_grant)
default: begin
rhs_array_muxed25 = soc_user_port_cmd_payload_we;
end
endcase
end
always @(*) begin
rhs_array_muxed26 = 1'd0;
case (roundrobin4_grant)
default: begin
rhs_array_muxed26 = (((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
end
endcase
end
always @(*) begin
rhs_array_muxed27 = 21'd0;
case (roundrobin5_grant)
default: begin
rhs_array_muxed27 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
rhs_array_muxed28 = 1'd0;
case (roundrobin5_grant)
default: begin
rhs_array_muxed28 = soc_user_port_cmd_payload_we;
end
endcase
end
always @(*) begin
rhs_array_muxed29 = 1'd0;
case (roundrobin5_grant)
default: begin
rhs_array_muxed29 = (((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
end
endcase
end
always @(*) begin
rhs_array_muxed30 = 21'd0;
case (roundrobin6_grant)
default: begin
rhs_array_muxed30 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
rhs_array_muxed31 = 1'd0;
case (roundrobin6_grant)
default: begin
rhs_array_muxed31 = soc_user_port_cmd_payload_we;
end
endcase
end
always @(*) begin
rhs_array_muxed32 = 1'd0;
case (roundrobin6_grant)
default: begin
rhs_array_muxed32 = (((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
end
endcase
end
always @(*) begin
rhs_array_muxed33 = 21'd0;
case (roundrobin7_grant)
default: begin
rhs_array_muxed33 = {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
rhs_array_muxed34 = 1'd0;
case (roundrobin7_grant)
default: begin
rhs_array_muxed34 = soc_user_port_cmd_payload_we;
end
endcase
end
always @(*) begin
rhs_array_muxed35 = 1'd0;
case (roundrobin7_grant)
default: begin
rhs_array_muxed35 = (((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (soc_litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid);
end
endcase
end
always @(*) begin
array_muxed0 = 3'd0;
case (soc_litedramcore_steerer_sel0)
1'd0: begin
array_muxed0 = soc_litedramcore_nop_ba[2:0];
end
1'd1: begin
array_muxed0 = soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
array_muxed0 = soc_litedramcore_choose_req_cmd_payload_ba[2:0];
end
default: begin
array_muxed0 = soc_litedramcore_cmd_payload_ba[2:0];
end
endcase
end
always @(*) begin
array_muxed1 = 14'd0;
case (soc_litedramcore_steerer_sel0)
1'd0: begin
array_muxed1 = soc_litedramcore_nop_a;
end
1'd1: begin
array_muxed1 = soc_litedramcore_choose_cmd_cmd_payload_a;
end
2'd2: begin
array_muxed1 = soc_litedramcore_choose_req_cmd_payload_a;
end
default: begin
array_muxed1 = soc_litedramcore_cmd_payload_a;
end
endcase
end
always @(*) begin
array_muxed2 = 1'd0;
case (soc_litedramcore_steerer_sel0)
1'd0: begin
array_muxed2 = 1'd0;
end
1'd1: begin
array_muxed2 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
end
2'd2: begin
array_muxed2 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
end
default: begin
array_muxed2 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
end
endcase
end
always @(*) begin
array_muxed3 = 1'd0;
case (soc_litedramcore_steerer_sel0)
1'd0: begin
array_muxed3 = 1'd0;
end
1'd1: begin
array_muxed3 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
end
2'd2: begin
array_muxed3 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
end
default: begin
array_muxed3 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
end
endcase
end
always @(*) begin
array_muxed4 = 1'd0;
case (soc_litedramcore_steerer_sel0)
1'd0: begin
array_muxed4 = 1'd0;
end
1'd1: begin
array_muxed4 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
end
2'd2: begin
array_muxed4 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
end
default: begin
array_muxed4 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
end
endcase
end
always @(*) begin
array_muxed5 = 1'd0;
case (soc_litedramcore_steerer_sel0)
1'd0: begin
array_muxed5 = 1'd0;
end
1'd1: begin
array_muxed5 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
end
2'd2: begin
array_muxed5 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
end
default: begin
array_muxed5 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
end
endcase
end
always @(*) begin
array_muxed6 = 1'd0;
case (soc_litedramcore_steerer_sel0)
1'd0: begin
array_muxed6 = 1'd0;
end
1'd1: begin
array_muxed6 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
end
2'd2: begin
array_muxed6 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
end
default: begin
array_muxed6 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
end
endcase
end
always @(*) begin
array_muxed7 = 3'd0;
case (soc_litedramcore_steerer_sel1)
1'd0: begin
array_muxed7 = soc_litedramcore_nop_ba[2:0];
end
1'd1: begin
array_muxed7 = soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
array_muxed7 = soc_litedramcore_choose_req_cmd_payload_ba[2:0];
end
default: begin
array_muxed7 = soc_litedramcore_cmd_payload_ba[2:0];
end
endcase
end
always @(*) begin
array_muxed8 = 14'd0;
case (soc_litedramcore_steerer_sel1)
1'd0: begin
array_muxed8 = soc_litedramcore_nop_a;
end
1'd1: begin
array_muxed8 = soc_litedramcore_choose_cmd_cmd_payload_a;
end
2'd2: begin
array_muxed8 = soc_litedramcore_choose_req_cmd_payload_a;
end
default: begin
array_muxed8 = soc_litedramcore_cmd_payload_a;
end
endcase
end
always @(*) begin
array_muxed9 = 1'd0;
case (soc_litedramcore_steerer_sel1)
1'd0: begin
array_muxed9 = 1'd0;
end
1'd1: begin
array_muxed9 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
end
2'd2: begin
array_muxed9 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
end
default: begin
array_muxed9 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
end
endcase
end
always @(*) begin
array_muxed10 = 1'd0;
case (soc_litedramcore_steerer_sel1)
1'd0: begin
array_muxed10 = 1'd0;
end
1'd1: begin
array_muxed10 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
end
2'd2: begin
array_muxed10 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
end
default: begin
array_muxed10 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
end
endcase
end
always @(*) begin
array_muxed11 = 1'd0;
case (soc_litedramcore_steerer_sel1)
1'd0: begin
array_muxed11 = 1'd0;
end
1'd1: begin
array_muxed11 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
end
2'd2: begin
array_muxed11 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
end
default: begin
array_muxed11 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
end
endcase
end
always @(*) begin
array_muxed12 = 1'd0;
case (soc_litedramcore_steerer_sel1)
1'd0: begin
array_muxed12 = 1'd0;
end
1'd1: begin
array_muxed12 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
end
2'd2: begin
array_muxed12 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
end
default: begin
array_muxed12 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
end
endcase
end
always @(*) begin
array_muxed13 = 1'd0;
case (soc_litedramcore_steerer_sel1)
1'd0: begin
array_muxed13 = 1'd0;
end
1'd1: begin
array_muxed13 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
end
2'd2: begin
array_muxed13 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
end
default: begin
array_muxed13 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
end
endcase
end
always @(*) begin
array_muxed14 = 3'd0;
case (soc_litedramcore_steerer_sel2)
1'd0: begin
array_muxed14 = soc_litedramcore_nop_ba[2:0];
end
1'd1: begin
array_muxed14 = soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
array_muxed14 = soc_litedramcore_choose_req_cmd_payload_ba[2:0];
end
default: begin
array_muxed14 = soc_litedramcore_cmd_payload_ba[2:0];
end
endcase
end
always @(*) begin
array_muxed15 = 14'd0;
case (soc_litedramcore_steerer_sel2)
1'd0: begin
array_muxed15 = soc_litedramcore_nop_a;
end
1'd1: begin
array_muxed15 = soc_litedramcore_choose_cmd_cmd_payload_a;
end
2'd2: begin
array_muxed15 = soc_litedramcore_choose_req_cmd_payload_a;
end
default: begin
array_muxed15 = soc_litedramcore_cmd_payload_a;
end
endcase
end
always @(*) begin
array_muxed16 = 1'd0;
case (soc_litedramcore_steerer_sel2)
1'd0: begin
array_muxed16 = 1'd0;
end
1'd1: begin
array_muxed16 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
end
2'd2: begin
array_muxed16 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
end
default: begin
array_muxed16 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
end
endcase
end
always @(*) begin
array_muxed17 = 1'd0;
case (soc_litedramcore_steerer_sel2)
1'd0: begin
array_muxed17 = 1'd0;
end
1'd1: begin
array_muxed17 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
end
2'd2: begin
array_muxed17 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
end
default: begin
array_muxed17 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
end
endcase
end
always @(*) begin
array_muxed18 = 1'd0;
case (soc_litedramcore_steerer_sel2)
1'd0: begin
array_muxed18 = 1'd0;
end
1'd1: begin
array_muxed18 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
end
2'd2: begin
array_muxed18 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
end
default: begin
array_muxed18 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
end
endcase
end
always @(*) begin
array_muxed19 = 1'd0;
case (soc_litedramcore_steerer_sel2)
1'd0: begin
array_muxed19 = 1'd0;
end
1'd1: begin
array_muxed19 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
end
2'd2: begin
array_muxed19 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
end
default: begin
array_muxed19 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
end
endcase
end
always @(*) begin
array_muxed20 = 1'd0;
case (soc_litedramcore_steerer_sel2)
1'd0: begin
array_muxed20 = 1'd0;
end
1'd1: begin
array_muxed20 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
end
2'd2: begin
array_muxed20 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
end
default: begin
array_muxed20 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
end
endcase
end
always @(*) begin
array_muxed21 = 3'd0;
case (soc_litedramcore_steerer_sel3)
1'd0: begin
array_muxed21 = soc_litedramcore_nop_ba[2:0];
end
1'd1: begin
array_muxed21 = soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
array_muxed21 = soc_litedramcore_choose_req_cmd_payload_ba[2:0];
end
default: begin
array_muxed21 = soc_litedramcore_cmd_payload_ba[2:0];
end
endcase
end
always @(*) begin
array_muxed22 = 14'd0;
case (soc_litedramcore_steerer_sel3)
1'd0: begin
array_muxed22 = soc_litedramcore_nop_a;
end
1'd1: begin
array_muxed22 = soc_litedramcore_choose_cmd_cmd_payload_a;
end
2'd2: begin
array_muxed22 = soc_litedramcore_choose_req_cmd_payload_a;
end
default: begin
array_muxed22 = soc_litedramcore_cmd_payload_a;
end
endcase
end
always @(*) begin
array_muxed23 = 1'd0;
case (soc_litedramcore_steerer_sel3)
1'd0: begin
array_muxed23 = 1'd0;
end
1'd1: begin
array_muxed23 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
end
2'd2: begin
array_muxed23 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
end
default: begin
array_muxed23 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
end
endcase
end
always @(*) begin
array_muxed24 = 1'd0;
case (soc_litedramcore_steerer_sel3)
1'd0: begin
array_muxed24 = 1'd0;
end
1'd1: begin
array_muxed24 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
end
2'd2: begin
array_muxed24 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
end
default: begin
array_muxed24 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
end
endcase
end
always @(*) begin
array_muxed25 = 1'd0;
case (soc_litedramcore_steerer_sel3)
1'd0: begin
array_muxed25 = 1'd0;
end
1'd1: begin
array_muxed25 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
end
2'd2: begin
array_muxed25 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
end
default: begin
array_muxed25 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
end
endcase
end
always @(*) begin
array_muxed26 = 1'd0;
case (soc_litedramcore_steerer_sel3)
1'd0: begin
array_muxed26 = 1'd0;
end
1'd1: begin
array_muxed26 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
end
2'd2: begin
array_muxed26 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
end
default: begin
array_muxed26 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
end
endcase
end
always @(*) begin
array_muxed27 = 1'd0;
case (soc_litedramcore_steerer_sel3)
1'd0: begin
array_muxed27 = 1'd0;
end
1'd1: begin
array_muxed27 = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
end
2'd2: begin
array_muxed27 = ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
end
default: begin
array_muxed27 = ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
end
endcase
end
always @(posedge por_clk) begin
soc_int_rst <= 1'd0;
end
always @(posedge sys_clk) begin
soc_ddrphy_new_bank_write0 <= soc_ddrphy_bank_write0;
soc_ddrphy_new_bank_write_col0 <= soc_ddrphy_bank_write_col0;
soc_ddrphy_new_bank_write1 <= soc_ddrphy_bank_write1;
soc_ddrphy_new_bank_write_col1 <= soc_ddrphy_bank_write_col1;
soc_ddrphy_new_bank_write2 <= soc_ddrphy_bank_write2;
soc_ddrphy_new_bank_write_col2 <= soc_ddrphy_bank_write_col2;
soc_ddrphy_new_bank_write3 <= soc_ddrphy_bank_write3;
soc_ddrphy_new_bank_write_col3 <= soc_ddrphy_bank_write_col3;
soc_ddrphy_new_bank_write4 <= soc_ddrphy_bank_write4;
soc_ddrphy_new_bank_write_col4 <= soc_ddrphy_bank_write_col4;
soc_ddrphy_new_bank_write5 <= soc_ddrphy_bank_write5;
soc_ddrphy_new_bank_write_col5 <= soc_ddrphy_bank_write_col5;
soc_ddrphy_new_bank_write6 <= soc_ddrphy_bank_write6;
soc_ddrphy_new_bank_write_col6 <= soc_ddrphy_bank_write_col6;
soc_ddrphy_new_bank_write7 <= soc_ddrphy_bank_write7;
soc_ddrphy_new_bank_write_col7 <= soc_ddrphy_bank_write_col7;
soc_ddrphy_new_banks_read0 <= soc_ddrphy_banks_read;
soc_ddrphy_new_banks_read_data0 <= soc_ddrphy_banks_read_data;
soc_ddrphy_new_banks_read1 <= soc_ddrphy_new_banks_read0;
soc_ddrphy_new_banks_read_data1 <= soc_ddrphy_new_banks_read_data0;
soc_ddrphy_new_banks_read2 <= soc_ddrphy_new_banks_read1;
soc_ddrphy_new_banks_read_data2 <= soc_ddrphy_new_banks_read_data1;
soc_ddrphy_new_banks_read3 <= soc_ddrphy_new_banks_read2;
soc_ddrphy_new_banks_read_data3 <= soc_ddrphy_new_banks_read_data2;
soc_ddrphy_new_banks_read4 <= soc_ddrphy_new_banks_read3;
soc_ddrphy_new_banks_read_data4 <= soc_ddrphy_new_banks_read_data3;
soc_ddrphy_new_banks_read5 <= soc_ddrphy_new_banks_read4;
soc_ddrphy_new_banks_read_data5 <= soc_ddrphy_new_banks_read_data4;
soc_ddrphy_new_banks_read6 <= soc_ddrphy_new_banks_read5;
soc_ddrphy_new_banks_read_data6 <= soc_ddrphy_new_banks_read_data5;
soc_ddrphy_new_banks_read7 <= soc_ddrphy_new_banks_read6;
soc_ddrphy_new_banks_read_data7 <= soc_ddrphy_new_banks_read_data6;
if (soc_ddrphy_bankmodel0_precharge) begin
soc_ddrphy_bankmodel0_active <= 1'd0;
end else begin
if (soc_ddrphy_bankmodel0_activate) begin
soc_ddrphy_bankmodel0_active <= 1'd1;
soc_ddrphy_bankmodel0_row <= soc_ddrphy_bankmodel0_activate_row;
end
end
if (soc_ddrphy_bankmodel1_precharge) begin
soc_ddrphy_bankmodel1_active <= 1'd0;
end else begin
if (soc_ddrphy_bankmodel1_activate) begin
soc_ddrphy_bankmodel1_active <= 1'd1;
soc_ddrphy_bankmodel1_row <= soc_ddrphy_bankmodel1_activate_row;
end
end
if (soc_ddrphy_bankmodel2_precharge) begin
soc_ddrphy_bankmodel2_active <= 1'd0;
end else begin
if (soc_ddrphy_bankmodel2_activate) begin
soc_ddrphy_bankmodel2_active <= 1'd1;
soc_ddrphy_bankmodel2_row <= soc_ddrphy_bankmodel2_activate_row;
end
end
if (soc_ddrphy_bankmodel3_precharge) begin
soc_ddrphy_bankmodel3_active <= 1'd0;
end else begin
if (soc_ddrphy_bankmodel3_activate) begin
soc_ddrphy_bankmodel3_active <= 1'd1;
soc_ddrphy_bankmodel3_row <= soc_ddrphy_bankmodel3_activate_row;
end
end
if (soc_ddrphy_bankmodel4_precharge) begin
soc_ddrphy_bankmodel4_active <= 1'd0;
end else begin
if (soc_ddrphy_bankmodel4_activate) begin
soc_ddrphy_bankmodel4_active <= 1'd1;
soc_ddrphy_bankmodel4_row <= soc_ddrphy_bankmodel4_activate_row;
end
end
if (soc_ddrphy_bankmodel5_precharge) begin
soc_ddrphy_bankmodel5_active <= 1'd0;
end else begin
if (soc_ddrphy_bankmodel5_activate) begin
soc_ddrphy_bankmodel5_active <= 1'd1;
soc_ddrphy_bankmodel5_row <= soc_ddrphy_bankmodel5_activate_row;
end
end
if (soc_ddrphy_bankmodel6_precharge) begin
soc_ddrphy_bankmodel6_active <= 1'd0;
end else begin
if (soc_ddrphy_bankmodel6_activate) begin
soc_ddrphy_bankmodel6_active <= 1'd1;
soc_ddrphy_bankmodel6_row <= soc_ddrphy_bankmodel6_activate_row;
end
end
if (soc_ddrphy_bankmodel7_precharge) begin
soc_ddrphy_bankmodel7_active <= 1'd0;
end else begin
if (soc_ddrphy_bankmodel7_activate) begin
soc_ddrphy_bankmodel7_active <= 1'd1;
soc_ddrphy_bankmodel7_row <= soc_ddrphy_bankmodel7_activate_row;
end
end
if (soc_litedramcore_inti_p0_rddata_valid) begin
soc_litedramcore_phaseinjector0_rddata_status <= soc_litedramcore_inti_p0_rddata;
end
if (soc_litedramcore_inti_p1_rddata_valid) begin
soc_litedramcore_phaseinjector1_rddata_status <= soc_litedramcore_inti_p1_rddata;
end
if (soc_litedramcore_inti_p2_rddata_valid) begin
soc_litedramcore_phaseinjector2_rddata_status <= soc_litedramcore_inti_p2_rddata;
end
if (soc_litedramcore_inti_p3_rddata_valid) begin
soc_litedramcore_phaseinjector3_rddata_status <= soc_litedramcore_inti_p3_rddata;
end
if ((soc_litedramcore_timer_wait & (~soc_litedramcore_timer_done0))) begin
soc_litedramcore_timer_count1 <= (soc_litedramcore_timer_count1 - 1'd1);
end else begin
soc_litedramcore_timer_count1 <= 10'd781;
end
soc_litedramcore_postponer_req_o <= 1'd0;
if (soc_litedramcore_postponer_req_i) begin
soc_litedramcore_postponer_count <= (soc_litedramcore_postponer_count - 1'd1);
if ((soc_litedramcore_postponer_count == 1'd0)) begin
soc_litedramcore_postponer_count <= 1'd0;
soc_litedramcore_postponer_req_o <= 1'd1;
end
end
if (soc_litedramcore_sequencer_start0) begin
soc_litedramcore_sequencer_count <= 1'd0;
end else begin
if (soc_litedramcore_sequencer_done1) begin
if ((soc_litedramcore_sequencer_count != 1'd0)) begin
soc_litedramcore_sequencer_count <= (soc_litedramcore_sequencer_count - 1'd1);
end
end
end
soc_litedramcore_cmd_payload_a <= 1'd0;
soc_litedramcore_cmd_payload_ba <= 1'd0;
soc_litedramcore_cmd_payload_cas <= 1'd0;
soc_litedramcore_cmd_payload_ras <= 1'd0;
soc_litedramcore_cmd_payload_we <= 1'd0;
soc_litedramcore_sequencer_done1 <= 1'd0;
if ((soc_litedramcore_sequencer_start1 & (soc_litedramcore_sequencer_counter == 1'd0))) begin
soc_litedramcore_cmd_payload_a <= 11'd1024;
soc_litedramcore_cmd_payload_ba <= 1'd0;
soc_litedramcore_cmd_payload_cas <= 1'd0;
soc_litedramcore_cmd_payload_ras <= 1'd1;
soc_litedramcore_cmd_payload_we <= 1'd1;
end
if ((soc_litedramcore_sequencer_counter == 2'd3)) begin
soc_litedramcore_cmd_payload_a <= 11'd1024;
soc_litedramcore_cmd_payload_ba <= 1'd0;
soc_litedramcore_cmd_payload_cas <= 1'd1;
soc_litedramcore_cmd_payload_ras <= 1'd1;
soc_litedramcore_cmd_payload_we <= 1'd0;
end
if ((soc_litedramcore_sequencer_counter == 6'd35)) begin
soc_litedramcore_cmd_payload_a <= 1'd0;
soc_litedramcore_cmd_payload_ba <= 1'd0;
soc_litedramcore_cmd_payload_cas <= 1'd0;
soc_litedramcore_cmd_payload_ras <= 1'd0;
soc_litedramcore_cmd_payload_we <= 1'd0;
soc_litedramcore_sequencer_done1 <= 1'd1;
end
if ((soc_litedramcore_sequencer_counter == 6'd35)) begin
soc_litedramcore_sequencer_counter <= 1'd0;
end else begin
if ((soc_litedramcore_sequencer_counter != 1'd0)) begin
soc_litedramcore_sequencer_counter <= (soc_litedramcore_sequencer_counter + 1'd1);
end else begin
if (soc_litedramcore_sequencer_start1) begin
soc_litedramcore_sequencer_counter <= 1'd1;
end
end
end
if ((soc_litedramcore_zqcs_timer_wait & (~soc_litedramcore_zqcs_timer_done0))) begin
soc_litedramcore_zqcs_timer_count1 <= (soc_litedramcore_zqcs_timer_count1 - 1'd1);
end else begin
soc_litedramcore_zqcs_timer_count1 <= 27'd99999999;
end
soc_litedramcore_zqcs_executer_done <= 1'd0;
if ((soc_litedramcore_zqcs_executer_start & (soc_litedramcore_zqcs_executer_counter == 1'd0))) begin
soc_litedramcore_cmd_payload_a <= 11'd1024;
soc_litedramcore_cmd_payload_ba <= 1'd0;
soc_litedramcore_cmd_payload_cas <= 1'd0;
soc_litedramcore_cmd_payload_ras <= 1'd1;
soc_litedramcore_cmd_payload_we <= 1'd1;
end
if ((soc_litedramcore_zqcs_executer_counter == 2'd3)) begin
soc_litedramcore_cmd_payload_a <= 1'd0;
soc_litedramcore_cmd_payload_ba <= 1'd0;
soc_litedramcore_cmd_payload_cas <= 1'd0;
soc_litedramcore_cmd_payload_ras <= 1'd0;
soc_litedramcore_cmd_payload_we <= 1'd1;
end
if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin
soc_litedramcore_cmd_payload_a <= 1'd0;
soc_litedramcore_cmd_payload_ba <= 1'd0;
soc_litedramcore_cmd_payload_cas <= 1'd0;
soc_litedramcore_cmd_payload_ras <= 1'd0;
soc_litedramcore_cmd_payload_we <= 1'd0;
soc_litedramcore_zqcs_executer_done <= 1'd1;
end
if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin
soc_litedramcore_zqcs_executer_counter <= 1'd0;
end else begin
if ((soc_litedramcore_zqcs_executer_counter != 1'd0)) begin
soc_litedramcore_zqcs_executer_counter <= (soc_litedramcore_zqcs_executer_counter + 1'd1);
end else begin
if (soc_litedramcore_zqcs_executer_start) begin
soc_litedramcore_zqcs_executer_counter <= 1'd1;
end
end
end
refresher_state <= refresher_next_state;
if (soc_litedramcore_bankmachine0_row_close) begin
soc_litedramcore_bankmachine0_row_opened <= 1'd0;
end else begin
if (soc_litedramcore_bankmachine0_row_open) begin
soc_litedramcore_bankmachine0_row_opened <= 1'd1;
soc_litedramcore_bankmachine0_row <= soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
end
end
if (((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
end
if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
end
if (((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
if ((~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
end
end
if (((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
soc_litedramcore_bankmachine0_cmd_buffer_source_valid <= soc_litedramcore_bankmachine0_cmd_buffer_sink_valid;
soc_litedramcore_bankmachine0_cmd_buffer_source_first <= soc_litedramcore_bankmachine0_cmd_buffer_sink_first;
soc_litedramcore_bankmachine0_cmd_buffer_source_last <= soc_litedramcore_bankmachine0_cmd_buffer_sink_last;
soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
end
if (soc_litedramcore_bankmachine0_twtpcon_valid) begin
soc_litedramcore_bankmachine0_twtpcon_count <= 3'd5;
if (1'd0) begin
soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
end else begin
soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_bankmachine0_twtpcon_ready)) begin
soc_litedramcore_bankmachine0_twtpcon_count <= (soc_litedramcore_bankmachine0_twtpcon_count - 1'd1);
if ((soc_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
end
end
end
if (soc_litedramcore_bankmachine0_trccon_valid) begin
soc_litedramcore_bankmachine0_trccon_count <= 3'd5;
if (1'd0) begin
soc_litedramcore_bankmachine0_trccon_ready <= 1'd1;
end else begin
soc_litedramcore_bankmachine0_trccon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_bankmachine0_trccon_ready)) begin
soc_litedramcore_bankmachine0_trccon_count <= (soc_litedramcore_bankmachine0_trccon_count - 1'd1);
if ((soc_litedramcore_bankmachine0_trccon_count == 1'd1)) begin
soc_litedramcore_bankmachine0_trccon_ready <= 1'd1;
end
end
end
if (soc_litedramcore_bankmachine0_trascon_valid) begin
soc_litedramcore_bankmachine0_trascon_count <= 3'd4;
if (1'd0) begin
soc_litedramcore_bankmachine0_trascon_ready <= 1'd1;
end else begin
soc_litedramcore_bankmachine0_trascon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_bankmachine0_trascon_ready)) begin
soc_litedramcore_bankmachine0_trascon_count <= (soc_litedramcore_bankmachine0_trascon_count - 1'd1);
if ((soc_litedramcore_bankmachine0_trascon_count == 1'd1)) begin
soc_litedramcore_bankmachine0_trascon_ready <= 1'd1;
end
end
end
bankmachine0_state <= bankmachine0_next_state;
if (soc_litedramcore_bankmachine1_row_close) begin
soc_litedramcore_bankmachine1_row_opened <= 1'd0;
end else begin
if (soc_litedramcore_bankmachine1_row_open) begin
soc_litedramcore_bankmachine1_row_opened <= 1'd1;
soc_litedramcore_bankmachine1_row <= soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
end
end
if (((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
end
if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
end
if (((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
if ((~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
end
end
if (((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
soc_litedramcore_bankmachine1_cmd_buffer_source_valid <= soc_litedramcore_bankmachine1_cmd_buffer_sink_valid;
soc_litedramcore_bankmachine1_cmd_buffer_source_first <= soc_litedramcore_bankmachine1_cmd_buffer_sink_first;
soc_litedramcore_bankmachine1_cmd_buffer_source_last <= soc_litedramcore_bankmachine1_cmd_buffer_sink_last;
soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
end
if (soc_litedramcore_bankmachine1_twtpcon_valid) begin
soc_litedramcore_bankmachine1_twtpcon_count <= 3'd5;
if (1'd0) begin
soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
end else begin
soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_bankmachine1_twtpcon_ready)) begin
soc_litedramcore_bankmachine1_twtpcon_count <= (soc_litedramcore_bankmachine1_twtpcon_count - 1'd1);
if ((soc_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
end
end
end
if (soc_litedramcore_bankmachine1_trccon_valid) begin
soc_litedramcore_bankmachine1_trccon_count <= 3'd5;
if (1'd0) begin
soc_litedramcore_bankmachine1_trccon_ready <= 1'd1;
end else begin
soc_litedramcore_bankmachine1_trccon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_bankmachine1_trccon_ready)) begin
soc_litedramcore_bankmachine1_trccon_count <= (soc_litedramcore_bankmachine1_trccon_count - 1'd1);
if ((soc_litedramcore_bankmachine1_trccon_count == 1'd1)) begin
soc_litedramcore_bankmachine1_trccon_ready <= 1'd1;
end
end
end
if (soc_litedramcore_bankmachine1_trascon_valid) begin
soc_litedramcore_bankmachine1_trascon_count <= 3'd4;
if (1'd0) begin
soc_litedramcore_bankmachine1_trascon_ready <= 1'd1;
end else begin
soc_litedramcore_bankmachine1_trascon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_bankmachine1_trascon_ready)) begin
soc_litedramcore_bankmachine1_trascon_count <= (soc_litedramcore_bankmachine1_trascon_count - 1'd1);
if ((soc_litedramcore_bankmachine1_trascon_count == 1'd1)) begin
soc_litedramcore_bankmachine1_trascon_ready <= 1'd1;
end
end
end
bankmachine1_state <= bankmachine1_next_state;
if (soc_litedramcore_bankmachine2_row_close) begin
soc_litedramcore_bankmachine2_row_opened <= 1'd0;
end else begin
if (soc_litedramcore_bankmachine2_row_open) begin
soc_litedramcore_bankmachine2_row_opened <= 1'd1;
soc_litedramcore_bankmachine2_row <= soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
end
end
if (((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
end
if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
end
if (((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
if ((~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
end
end
if (((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
soc_litedramcore_bankmachine2_cmd_buffer_source_valid <= soc_litedramcore_bankmachine2_cmd_buffer_sink_valid;
soc_litedramcore_bankmachine2_cmd_buffer_source_first <= soc_litedramcore_bankmachine2_cmd_buffer_sink_first;
soc_litedramcore_bankmachine2_cmd_buffer_source_last <= soc_litedramcore_bankmachine2_cmd_buffer_sink_last;
soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
end
if (soc_litedramcore_bankmachine2_twtpcon_valid) begin
soc_litedramcore_bankmachine2_twtpcon_count <= 3'd5;
if (1'd0) begin
soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
end else begin
soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_bankmachine2_twtpcon_ready)) begin
soc_litedramcore_bankmachine2_twtpcon_count <= (soc_litedramcore_bankmachine2_twtpcon_count - 1'd1);
if ((soc_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
end
end
end
if (soc_litedramcore_bankmachine2_trccon_valid) begin
soc_litedramcore_bankmachine2_trccon_count <= 3'd5;
if (1'd0) begin
soc_litedramcore_bankmachine2_trccon_ready <= 1'd1;
end else begin
soc_litedramcore_bankmachine2_trccon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_bankmachine2_trccon_ready)) begin
soc_litedramcore_bankmachine2_trccon_count <= (soc_litedramcore_bankmachine2_trccon_count - 1'd1);
if ((soc_litedramcore_bankmachine2_trccon_count == 1'd1)) begin
soc_litedramcore_bankmachine2_trccon_ready <= 1'd1;
end
end
end
if (soc_litedramcore_bankmachine2_trascon_valid) begin
soc_litedramcore_bankmachine2_trascon_count <= 3'd4;
if (1'd0) begin
soc_litedramcore_bankmachine2_trascon_ready <= 1'd1;
end else begin
soc_litedramcore_bankmachine2_trascon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_bankmachine2_trascon_ready)) begin
soc_litedramcore_bankmachine2_trascon_count <= (soc_litedramcore_bankmachine2_trascon_count - 1'd1);
if ((soc_litedramcore_bankmachine2_trascon_count == 1'd1)) begin
soc_litedramcore_bankmachine2_trascon_ready <= 1'd1;
end
end
end
bankmachine2_state <= bankmachine2_next_state;
if (soc_litedramcore_bankmachine3_row_close) begin
soc_litedramcore_bankmachine3_row_opened <= 1'd0;
end else begin
if (soc_litedramcore_bankmachine3_row_open) begin
soc_litedramcore_bankmachine3_row_opened <= 1'd1;
soc_litedramcore_bankmachine3_row <= soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
end
end
if (((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
end
if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
end
if (((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
if ((~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
end
end
if (((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
soc_litedramcore_bankmachine3_cmd_buffer_source_valid <= soc_litedramcore_bankmachine3_cmd_buffer_sink_valid;
soc_litedramcore_bankmachine3_cmd_buffer_source_first <= soc_litedramcore_bankmachine3_cmd_buffer_sink_first;
soc_litedramcore_bankmachine3_cmd_buffer_source_last <= soc_litedramcore_bankmachine3_cmd_buffer_sink_last;
soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
end
if (soc_litedramcore_bankmachine3_twtpcon_valid) begin
soc_litedramcore_bankmachine3_twtpcon_count <= 3'd5;
if (1'd0) begin
soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
end else begin
soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_bankmachine3_twtpcon_ready)) begin
soc_litedramcore_bankmachine3_twtpcon_count <= (soc_litedramcore_bankmachine3_twtpcon_count - 1'd1);
if ((soc_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
end
end
end
if (soc_litedramcore_bankmachine3_trccon_valid) begin
soc_litedramcore_bankmachine3_trccon_count <= 3'd5;
if (1'd0) begin
soc_litedramcore_bankmachine3_trccon_ready <= 1'd1;
end else begin
soc_litedramcore_bankmachine3_trccon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_bankmachine3_trccon_ready)) begin
soc_litedramcore_bankmachine3_trccon_count <= (soc_litedramcore_bankmachine3_trccon_count - 1'd1);
if ((soc_litedramcore_bankmachine3_trccon_count == 1'd1)) begin
soc_litedramcore_bankmachine3_trccon_ready <= 1'd1;
end
end
end
if (soc_litedramcore_bankmachine3_trascon_valid) begin
soc_litedramcore_bankmachine3_trascon_count <= 3'd4;
if (1'd0) begin
soc_litedramcore_bankmachine3_trascon_ready <= 1'd1;
end else begin
soc_litedramcore_bankmachine3_trascon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_bankmachine3_trascon_ready)) begin
soc_litedramcore_bankmachine3_trascon_count <= (soc_litedramcore_bankmachine3_trascon_count - 1'd1);
if ((soc_litedramcore_bankmachine3_trascon_count == 1'd1)) begin
soc_litedramcore_bankmachine3_trascon_ready <= 1'd1;
end
end
end
bankmachine3_state <= bankmachine3_next_state;
if (soc_litedramcore_bankmachine4_row_close) begin
soc_litedramcore_bankmachine4_row_opened <= 1'd0;
end else begin
if (soc_litedramcore_bankmachine4_row_open) begin
soc_litedramcore_bankmachine4_row_opened <= 1'd1;
soc_litedramcore_bankmachine4_row <= soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
end
end
if (((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
end
if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
end
if (((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
if ((~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
end
end
if (((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
soc_litedramcore_bankmachine4_cmd_buffer_source_valid <= soc_litedramcore_bankmachine4_cmd_buffer_sink_valid;
soc_litedramcore_bankmachine4_cmd_buffer_source_first <= soc_litedramcore_bankmachine4_cmd_buffer_sink_first;
soc_litedramcore_bankmachine4_cmd_buffer_source_last <= soc_litedramcore_bankmachine4_cmd_buffer_sink_last;
soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
end
if (soc_litedramcore_bankmachine4_twtpcon_valid) begin
soc_litedramcore_bankmachine4_twtpcon_count <= 3'd5;
if (1'd0) begin
soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
end else begin
soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_bankmachine4_twtpcon_ready)) begin
soc_litedramcore_bankmachine4_twtpcon_count <= (soc_litedramcore_bankmachine4_twtpcon_count - 1'd1);
if ((soc_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
end
end
end
if (soc_litedramcore_bankmachine4_trccon_valid) begin
soc_litedramcore_bankmachine4_trccon_count <= 3'd5;
if (1'd0) begin
soc_litedramcore_bankmachine4_trccon_ready <= 1'd1;
end else begin
soc_litedramcore_bankmachine4_trccon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_bankmachine4_trccon_ready)) begin
soc_litedramcore_bankmachine4_trccon_count <= (soc_litedramcore_bankmachine4_trccon_count - 1'd1);
if ((soc_litedramcore_bankmachine4_trccon_count == 1'd1)) begin
soc_litedramcore_bankmachine4_trccon_ready <= 1'd1;
end
end
end
if (soc_litedramcore_bankmachine4_trascon_valid) begin
soc_litedramcore_bankmachine4_trascon_count <= 3'd4;
if (1'd0) begin
soc_litedramcore_bankmachine4_trascon_ready <= 1'd1;
end else begin
soc_litedramcore_bankmachine4_trascon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_bankmachine4_trascon_ready)) begin
soc_litedramcore_bankmachine4_trascon_count <= (soc_litedramcore_bankmachine4_trascon_count - 1'd1);
if ((soc_litedramcore_bankmachine4_trascon_count == 1'd1)) begin
soc_litedramcore_bankmachine4_trascon_ready <= 1'd1;
end
end
end
bankmachine4_state <= bankmachine4_next_state;
if (soc_litedramcore_bankmachine5_row_close) begin
soc_litedramcore_bankmachine5_row_opened <= 1'd0;
end else begin
if (soc_litedramcore_bankmachine5_row_open) begin
soc_litedramcore_bankmachine5_row_opened <= 1'd1;
soc_litedramcore_bankmachine5_row <= soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
end
end
if (((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
end
if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
end
if (((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
if ((~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
end
end
if (((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
soc_litedramcore_bankmachine5_cmd_buffer_source_valid <= soc_litedramcore_bankmachine5_cmd_buffer_sink_valid;
soc_litedramcore_bankmachine5_cmd_buffer_source_first <= soc_litedramcore_bankmachine5_cmd_buffer_sink_first;
soc_litedramcore_bankmachine5_cmd_buffer_source_last <= soc_litedramcore_bankmachine5_cmd_buffer_sink_last;
soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
end
if (soc_litedramcore_bankmachine5_twtpcon_valid) begin
soc_litedramcore_bankmachine5_twtpcon_count <= 3'd5;
if (1'd0) begin
soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
end else begin
soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_bankmachine5_twtpcon_ready)) begin
soc_litedramcore_bankmachine5_twtpcon_count <= (soc_litedramcore_bankmachine5_twtpcon_count - 1'd1);
if ((soc_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
end
end
end
if (soc_litedramcore_bankmachine5_trccon_valid) begin
soc_litedramcore_bankmachine5_trccon_count <= 3'd5;
if (1'd0) begin
soc_litedramcore_bankmachine5_trccon_ready <= 1'd1;
end else begin
soc_litedramcore_bankmachine5_trccon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_bankmachine5_trccon_ready)) begin
soc_litedramcore_bankmachine5_trccon_count <= (soc_litedramcore_bankmachine5_trccon_count - 1'd1);
if ((soc_litedramcore_bankmachine5_trccon_count == 1'd1)) begin
soc_litedramcore_bankmachine5_trccon_ready <= 1'd1;
end
end
end
if (soc_litedramcore_bankmachine5_trascon_valid) begin
soc_litedramcore_bankmachine5_trascon_count <= 3'd4;
if (1'd0) begin
soc_litedramcore_bankmachine5_trascon_ready <= 1'd1;
end else begin
soc_litedramcore_bankmachine5_trascon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_bankmachine5_trascon_ready)) begin
soc_litedramcore_bankmachine5_trascon_count <= (soc_litedramcore_bankmachine5_trascon_count - 1'd1);
if ((soc_litedramcore_bankmachine5_trascon_count == 1'd1)) begin
soc_litedramcore_bankmachine5_trascon_ready <= 1'd1;
end
end
end
bankmachine5_state <= bankmachine5_next_state;
if (soc_litedramcore_bankmachine6_row_close) begin
soc_litedramcore_bankmachine6_row_opened <= 1'd0;
end else begin
if (soc_litedramcore_bankmachine6_row_open) begin
soc_litedramcore_bankmachine6_row_opened <= 1'd1;
soc_litedramcore_bankmachine6_row <= soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
end
end
if (((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
end
if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
end
if (((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
if ((~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
end
end
if (((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
soc_litedramcore_bankmachine6_cmd_buffer_source_valid <= soc_litedramcore_bankmachine6_cmd_buffer_sink_valid;
soc_litedramcore_bankmachine6_cmd_buffer_source_first <= soc_litedramcore_bankmachine6_cmd_buffer_sink_first;
soc_litedramcore_bankmachine6_cmd_buffer_source_last <= soc_litedramcore_bankmachine6_cmd_buffer_sink_last;
soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
end
if (soc_litedramcore_bankmachine6_twtpcon_valid) begin
soc_litedramcore_bankmachine6_twtpcon_count <= 3'd5;
if (1'd0) begin
soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
end else begin
soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_bankmachine6_twtpcon_ready)) begin
soc_litedramcore_bankmachine6_twtpcon_count <= (soc_litedramcore_bankmachine6_twtpcon_count - 1'd1);
if ((soc_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
end
end
end
if (soc_litedramcore_bankmachine6_trccon_valid) begin
soc_litedramcore_bankmachine6_trccon_count <= 3'd5;
if (1'd0) begin
soc_litedramcore_bankmachine6_trccon_ready <= 1'd1;
end else begin
soc_litedramcore_bankmachine6_trccon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_bankmachine6_trccon_ready)) begin
soc_litedramcore_bankmachine6_trccon_count <= (soc_litedramcore_bankmachine6_trccon_count - 1'd1);
if ((soc_litedramcore_bankmachine6_trccon_count == 1'd1)) begin
soc_litedramcore_bankmachine6_trccon_ready <= 1'd1;
end
end
end
if (soc_litedramcore_bankmachine6_trascon_valid) begin
soc_litedramcore_bankmachine6_trascon_count <= 3'd4;
if (1'd0) begin
soc_litedramcore_bankmachine6_trascon_ready <= 1'd1;
end else begin
soc_litedramcore_bankmachine6_trascon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_bankmachine6_trascon_ready)) begin
soc_litedramcore_bankmachine6_trascon_count <= (soc_litedramcore_bankmachine6_trascon_count - 1'd1);
if ((soc_litedramcore_bankmachine6_trascon_count == 1'd1)) begin
soc_litedramcore_bankmachine6_trascon_ready <= 1'd1;
end
end
end
bankmachine6_state <= bankmachine6_next_state;
if (soc_litedramcore_bankmachine7_row_close) begin
soc_litedramcore_bankmachine7_row_opened <= 1'd0;
end else begin
if (soc_litedramcore_bankmachine7_row_open) begin
soc_litedramcore_bankmachine7_row_opened <= 1'd1;
soc_litedramcore_bankmachine7_row <= soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
end
end
if (((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
end
if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
end
if (((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
if ((~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
end
end
if (((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
soc_litedramcore_bankmachine7_cmd_buffer_source_valid <= soc_litedramcore_bankmachine7_cmd_buffer_sink_valid;
soc_litedramcore_bankmachine7_cmd_buffer_source_first <= soc_litedramcore_bankmachine7_cmd_buffer_sink_first;
soc_litedramcore_bankmachine7_cmd_buffer_source_last <= soc_litedramcore_bankmachine7_cmd_buffer_sink_last;
soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
end
if (soc_litedramcore_bankmachine7_twtpcon_valid) begin
soc_litedramcore_bankmachine7_twtpcon_count <= 3'd5;
if (1'd0) begin
soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
end else begin
soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_bankmachine7_twtpcon_ready)) begin
soc_litedramcore_bankmachine7_twtpcon_count <= (soc_litedramcore_bankmachine7_twtpcon_count - 1'd1);
if ((soc_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
end
end
end
if (soc_litedramcore_bankmachine7_trccon_valid) begin
soc_litedramcore_bankmachine7_trccon_count <= 3'd5;
if (1'd0) begin
soc_litedramcore_bankmachine7_trccon_ready <= 1'd1;
end else begin
soc_litedramcore_bankmachine7_trccon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_bankmachine7_trccon_ready)) begin
soc_litedramcore_bankmachine7_trccon_count <= (soc_litedramcore_bankmachine7_trccon_count - 1'd1);
if ((soc_litedramcore_bankmachine7_trccon_count == 1'd1)) begin
soc_litedramcore_bankmachine7_trccon_ready <= 1'd1;
end
end
end
if (soc_litedramcore_bankmachine7_trascon_valid) begin
soc_litedramcore_bankmachine7_trascon_count <= 3'd4;
if (1'd0) begin
soc_litedramcore_bankmachine7_trascon_ready <= 1'd1;
end else begin
soc_litedramcore_bankmachine7_trascon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_bankmachine7_trascon_ready)) begin
soc_litedramcore_bankmachine7_trascon_count <= (soc_litedramcore_bankmachine7_trascon_count - 1'd1);
if ((soc_litedramcore_bankmachine7_trascon_count == 1'd1)) begin
soc_litedramcore_bankmachine7_trascon_ready <= 1'd1;
end
end
end
bankmachine7_state <= bankmachine7_next_state;
if ((~soc_litedramcore_en0)) begin
soc_litedramcore_time0 <= 5'd31;
end else begin
if ((~soc_litedramcore_max_time0)) begin
soc_litedramcore_time0 <= (soc_litedramcore_time0 - 1'd1);
end
end
if ((~soc_litedramcore_en1)) begin
soc_litedramcore_time1 <= 4'd15;
end else begin
if ((~soc_litedramcore_max_time1)) begin
soc_litedramcore_time1 <= (soc_litedramcore_time1 - 1'd1);
end
end
if (soc_litedramcore_choose_cmd_ce) begin
case (soc_litedramcore_choose_cmd_grant)
1'd0: begin
if (soc_litedramcore_choose_cmd_request[1]) begin
soc_litedramcore_choose_cmd_grant <= 1'd1;
end else begin
if (soc_litedramcore_choose_cmd_request[2]) begin
soc_litedramcore_choose_cmd_grant <= 2'd2;
end else begin
if (soc_litedramcore_choose_cmd_request[3]) begin
soc_litedramcore_choose_cmd_grant <= 2'd3;
end else begin
if (soc_litedramcore_choose_cmd_request[4]) begin
soc_litedramcore_choose_cmd_grant <= 3'd4;
end else begin
if (soc_litedramcore_choose_cmd_request[5]) begin
soc_litedramcore_choose_cmd_grant <= 3'd5;
end else begin
if (soc_litedramcore_choose_cmd_request[6]) begin
soc_litedramcore_choose_cmd_grant <= 3'd6;
end else begin
if (soc_litedramcore_choose_cmd_request[7]) begin
soc_litedramcore_choose_cmd_grant <= 3'd7;
end
end
end
end
end
end
end
end
1'd1: begin
if (soc_litedramcore_choose_cmd_request[2]) begin
soc_litedramcore_choose_cmd_grant <= 2'd2;
end else begin
if (soc_litedramcore_choose_cmd_request[3]) begin
soc_litedramcore_choose_cmd_grant <= 2'd3;
end else begin
if (soc_litedramcore_choose_cmd_request[4]) begin
soc_litedramcore_choose_cmd_grant <= 3'd4;
end else begin
if (soc_litedramcore_choose_cmd_request[5]) begin
soc_litedramcore_choose_cmd_grant <= 3'd5;
end else begin
if (soc_litedramcore_choose_cmd_request[6]) begin
soc_litedramcore_choose_cmd_grant <= 3'd6;
end else begin
if (soc_litedramcore_choose_cmd_request[7]) begin
soc_litedramcore_choose_cmd_grant <= 3'd7;
end else begin
if (soc_litedramcore_choose_cmd_request[0]) begin
soc_litedramcore_choose_cmd_grant <= 1'd0;
end
end
end
end
end
end
end
end
2'd2: begin
if (soc_litedramcore_choose_cmd_request[3]) begin
soc_litedramcore_choose_cmd_grant <= 2'd3;
end else begin
if (soc_litedramcore_choose_cmd_request[4]) begin
soc_litedramcore_choose_cmd_grant <= 3'd4;
end else begin
if (soc_litedramcore_choose_cmd_request[5]) begin
soc_litedramcore_choose_cmd_grant <= 3'd5;
end else begin
if (soc_litedramcore_choose_cmd_request[6]) begin
soc_litedramcore_choose_cmd_grant <= 3'd6;
end else begin
if (soc_litedramcore_choose_cmd_request[7]) begin
soc_litedramcore_choose_cmd_grant <= 3'd7;
end else begin
if (soc_litedramcore_choose_cmd_request[0]) begin
soc_litedramcore_choose_cmd_grant <= 1'd0;
end else begin
if (soc_litedramcore_choose_cmd_request[1]) begin
soc_litedramcore_choose_cmd_grant <= 1'd1;
end
end
end
end
end
end
end
end
2'd3: begin
if (soc_litedramcore_choose_cmd_request[4]) begin
soc_litedramcore_choose_cmd_grant <= 3'd4;
end else begin
if (soc_litedramcore_choose_cmd_request[5]) begin
soc_litedramcore_choose_cmd_grant <= 3'd5;
end else begin
if (soc_litedramcore_choose_cmd_request[6]) begin
soc_litedramcore_choose_cmd_grant <= 3'd6;
end else begin
if (soc_litedramcore_choose_cmd_request[7]) begin
soc_litedramcore_choose_cmd_grant <= 3'd7;
end else begin
if (soc_litedramcore_choose_cmd_request[0]) begin
soc_litedramcore_choose_cmd_grant <= 1'd0;
end else begin
if (soc_litedramcore_choose_cmd_request[1]) begin
soc_litedramcore_choose_cmd_grant <= 1'd1;
end else begin
if (soc_litedramcore_choose_cmd_request[2]) begin
soc_litedramcore_choose_cmd_grant <= 2'd2;
end
end
end
end
end
end
end
end
3'd4: begin
if (soc_litedramcore_choose_cmd_request[5]) begin
soc_litedramcore_choose_cmd_grant <= 3'd5;
end else begin
if (soc_litedramcore_choose_cmd_request[6]) begin
soc_litedramcore_choose_cmd_grant <= 3'd6;
end else begin
if (soc_litedramcore_choose_cmd_request[7]) begin
soc_litedramcore_choose_cmd_grant <= 3'd7;
end else begin
if (soc_litedramcore_choose_cmd_request[0]) begin
soc_litedramcore_choose_cmd_grant <= 1'd0;
end else begin
if (soc_litedramcore_choose_cmd_request[1]) begin
soc_litedramcore_choose_cmd_grant <= 1'd1;
end else begin
if (soc_litedramcore_choose_cmd_request[2]) begin
soc_litedramcore_choose_cmd_grant <= 2'd2;
end else begin
if (soc_litedramcore_choose_cmd_request[3]) begin
soc_litedramcore_choose_cmd_grant <= 2'd3;
end
end
end
end
end
end
end
end
3'd5: begin
if (soc_litedramcore_choose_cmd_request[6]) begin
soc_litedramcore_choose_cmd_grant <= 3'd6;
end else begin
if (soc_litedramcore_choose_cmd_request[7]) begin
soc_litedramcore_choose_cmd_grant <= 3'd7;
end else begin
if (soc_litedramcore_choose_cmd_request[0]) begin
soc_litedramcore_choose_cmd_grant <= 1'd0;
end else begin
if (soc_litedramcore_choose_cmd_request[1]) begin
soc_litedramcore_choose_cmd_grant <= 1'd1;
end else begin
if (soc_litedramcore_choose_cmd_request[2]) begin
soc_litedramcore_choose_cmd_grant <= 2'd2;
end else begin
if (soc_litedramcore_choose_cmd_request[3]) begin
soc_litedramcore_choose_cmd_grant <= 2'd3;
end else begin
if (soc_litedramcore_choose_cmd_request[4]) begin
soc_litedramcore_choose_cmd_grant <= 3'd4;
end
end
end
end
end
end
end
end
3'd6: begin
if (soc_litedramcore_choose_cmd_request[7]) begin
soc_litedramcore_choose_cmd_grant <= 3'd7;
end else begin
if (soc_litedramcore_choose_cmd_request[0]) begin
soc_litedramcore_choose_cmd_grant <= 1'd0;
end else begin
if (soc_litedramcore_choose_cmd_request[1]) begin
soc_litedramcore_choose_cmd_grant <= 1'd1;
end else begin
if (soc_litedramcore_choose_cmd_request[2]) begin
soc_litedramcore_choose_cmd_grant <= 2'd2;
end else begin
if (soc_litedramcore_choose_cmd_request[3]) begin
soc_litedramcore_choose_cmd_grant <= 2'd3;
end else begin
if (soc_litedramcore_choose_cmd_request[4]) begin
soc_litedramcore_choose_cmd_grant <= 3'd4;
end else begin
if (soc_litedramcore_choose_cmd_request[5]) begin
soc_litedramcore_choose_cmd_grant <= 3'd5;
end
end
end
end
end
end
end
end
3'd7: begin
if (soc_litedramcore_choose_cmd_request[0]) begin
soc_litedramcore_choose_cmd_grant <= 1'd0;
end else begin
if (soc_litedramcore_choose_cmd_request[1]) begin
soc_litedramcore_choose_cmd_grant <= 1'd1;
end else begin
if (soc_litedramcore_choose_cmd_request[2]) begin
soc_litedramcore_choose_cmd_grant <= 2'd2;
end else begin
if (soc_litedramcore_choose_cmd_request[3]) begin
soc_litedramcore_choose_cmd_grant <= 2'd3;
end else begin
if (soc_litedramcore_choose_cmd_request[4]) begin
soc_litedramcore_choose_cmd_grant <= 3'd4;
end else begin
if (soc_litedramcore_choose_cmd_request[5]) begin
soc_litedramcore_choose_cmd_grant <= 3'd5;
end else begin
if (soc_litedramcore_choose_cmd_request[6]) begin
soc_litedramcore_choose_cmd_grant <= 3'd6;
end
end
end
end
end
end
end
end
endcase
end
if (soc_litedramcore_choose_req_ce) begin
case (soc_litedramcore_choose_req_grant)
1'd0: begin
if (soc_litedramcore_choose_req_request[1]) begin
soc_litedramcore_choose_req_grant <= 1'd1;
end else begin
if (soc_litedramcore_choose_req_request[2]) begin
soc_litedramcore_choose_req_grant <= 2'd2;
end else begin
if (soc_litedramcore_choose_req_request[3]) begin
soc_litedramcore_choose_req_grant <= 2'd3;
end else begin
if (soc_litedramcore_choose_req_request[4]) begin
soc_litedramcore_choose_req_grant <= 3'd4;
end else begin
if (soc_litedramcore_choose_req_request[5]) begin
soc_litedramcore_choose_req_grant <= 3'd5;
end else begin
if (soc_litedramcore_choose_req_request[6]) begin
soc_litedramcore_choose_req_grant <= 3'd6;
end else begin
if (soc_litedramcore_choose_req_request[7]) begin
soc_litedramcore_choose_req_grant <= 3'd7;
end
end
end
end
end
end
end
end
1'd1: begin
if (soc_litedramcore_choose_req_request[2]) begin
soc_litedramcore_choose_req_grant <= 2'd2;
end else begin
if (soc_litedramcore_choose_req_request[3]) begin
soc_litedramcore_choose_req_grant <= 2'd3;
end else begin
if (soc_litedramcore_choose_req_request[4]) begin
soc_litedramcore_choose_req_grant <= 3'd4;
end else begin
if (soc_litedramcore_choose_req_request[5]) begin
soc_litedramcore_choose_req_grant <= 3'd5;
end else begin
if (soc_litedramcore_choose_req_request[6]) begin
soc_litedramcore_choose_req_grant <= 3'd6;
end else begin
if (soc_litedramcore_choose_req_request[7]) begin
soc_litedramcore_choose_req_grant <= 3'd7;
end else begin
if (soc_litedramcore_choose_req_request[0]) begin
soc_litedramcore_choose_req_grant <= 1'd0;
end
end
end
end
end
end
end
end
2'd2: begin
if (soc_litedramcore_choose_req_request[3]) begin
soc_litedramcore_choose_req_grant <= 2'd3;
end else begin
if (soc_litedramcore_choose_req_request[4]) begin
soc_litedramcore_choose_req_grant <= 3'd4;
end else begin
if (soc_litedramcore_choose_req_request[5]) begin
soc_litedramcore_choose_req_grant <= 3'd5;
end else begin
if (soc_litedramcore_choose_req_request[6]) begin
soc_litedramcore_choose_req_grant <= 3'd6;
end else begin
if (soc_litedramcore_choose_req_request[7]) begin
soc_litedramcore_choose_req_grant <= 3'd7;
end else begin
if (soc_litedramcore_choose_req_request[0]) begin
soc_litedramcore_choose_req_grant <= 1'd0;
end else begin
if (soc_litedramcore_choose_req_request[1]) begin
soc_litedramcore_choose_req_grant <= 1'd1;
end
end
end
end
end
end
end
end
2'd3: begin
if (soc_litedramcore_choose_req_request[4]) begin
soc_litedramcore_choose_req_grant <= 3'd4;
end else begin
if (soc_litedramcore_choose_req_request[5]) begin
soc_litedramcore_choose_req_grant <= 3'd5;
end else begin
if (soc_litedramcore_choose_req_request[6]) begin
soc_litedramcore_choose_req_grant <= 3'd6;
end else begin
if (soc_litedramcore_choose_req_request[7]) begin
soc_litedramcore_choose_req_grant <= 3'd7;
end else begin
if (soc_litedramcore_choose_req_request[0]) begin
soc_litedramcore_choose_req_grant <= 1'd0;
end else begin
if (soc_litedramcore_choose_req_request[1]) begin
soc_litedramcore_choose_req_grant <= 1'd1;
end else begin
if (soc_litedramcore_choose_req_request[2]) begin
soc_litedramcore_choose_req_grant <= 2'd2;
end
end
end
end
end
end
end
end
3'd4: begin
if (soc_litedramcore_choose_req_request[5]) begin
soc_litedramcore_choose_req_grant <= 3'd5;
end else begin
if (soc_litedramcore_choose_req_request[6]) begin
soc_litedramcore_choose_req_grant <= 3'd6;
end else begin
if (soc_litedramcore_choose_req_request[7]) begin
soc_litedramcore_choose_req_grant <= 3'd7;
end else begin
if (soc_litedramcore_choose_req_request[0]) begin
soc_litedramcore_choose_req_grant <= 1'd0;
end else begin
if (soc_litedramcore_choose_req_request[1]) begin
soc_litedramcore_choose_req_grant <= 1'd1;
end else begin
if (soc_litedramcore_choose_req_request[2]) begin
soc_litedramcore_choose_req_grant <= 2'd2;
end else begin
if (soc_litedramcore_choose_req_request[3]) begin
soc_litedramcore_choose_req_grant <= 2'd3;
end
end
end
end
end
end
end
end
3'd5: begin
if (soc_litedramcore_choose_req_request[6]) begin
soc_litedramcore_choose_req_grant <= 3'd6;
end else begin
if (soc_litedramcore_choose_req_request[7]) begin
soc_litedramcore_choose_req_grant <= 3'd7;
end else begin
if (soc_litedramcore_choose_req_request[0]) begin
soc_litedramcore_choose_req_grant <= 1'd0;
end else begin
if (soc_litedramcore_choose_req_request[1]) begin
soc_litedramcore_choose_req_grant <= 1'd1;
end else begin
if (soc_litedramcore_choose_req_request[2]) begin
soc_litedramcore_choose_req_grant <= 2'd2;
end else begin
if (soc_litedramcore_choose_req_request[3]) begin
soc_litedramcore_choose_req_grant <= 2'd3;
end else begin
if (soc_litedramcore_choose_req_request[4]) begin
soc_litedramcore_choose_req_grant <= 3'd4;
end
end
end
end
end
end
end
end
3'd6: begin
if (soc_litedramcore_choose_req_request[7]) begin
soc_litedramcore_choose_req_grant <= 3'd7;
end else begin
if (soc_litedramcore_choose_req_request[0]) begin
soc_litedramcore_choose_req_grant <= 1'd0;
end else begin
if (soc_litedramcore_choose_req_request[1]) begin
soc_litedramcore_choose_req_grant <= 1'd1;
end else begin
if (soc_litedramcore_choose_req_request[2]) begin
soc_litedramcore_choose_req_grant <= 2'd2;
end else begin
if (soc_litedramcore_choose_req_request[3]) begin
soc_litedramcore_choose_req_grant <= 2'd3;
end else begin
if (soc_litedramcore_choose_req_request[4]) begin
soc_litedramcore_choose_req_grant <= 3'd4;
end else begin
if (soc_litedramcore_choose_req_request[5]) begin
soc_litedramcore_choose_req_grant <= 3'd5;
end
end
end
end
end
end
end
end
3'd7: begin
if (soc_litedramcore_choose_req_request[0]) begin
soc_litedramcore_choose_req_grant <= 1'd0;
end else begin
if (soc_litedramcore_choose_req_request[1]) begin
soc_litedramcore_choose_req_grant <= 1'd1;
end else begin
if (soc_litedramcore_choose_req_request[2]) begin
soc_litedramcore_choose_req_grant <= 2'd2;
end else begin
if (soc_litedramcore_choose_req_request[3]) begin
soc_litedramcore_choose_req_grant <= 2'd3;
end else begin
if (soc_litedramcore_choose_req_request[4]) begin
soc_litedramcore_choose_req_grant <= 3'd4;
end else begin
if (soc_litedramcore_choose_req_request[5]) begin
soc_litedramcore_choose_req_grant <= 3'd5;
end else begin
if (soc_litedramcore_choose_req_request[6]) begin
soc_litedramcore_choose_req_grant <= 3'd6;
end
end
end
end
end
end
end
end
endcase
end
soc_litedramcore_dfi_p0_cs_n <= 1'd0;
soc_litedramcore_dfi_p0_bank <= array_muxed0;
soc_litedramcore_dfi_p0_address <= array_muxed1;
soc_litedramcore_dfi_p0_cas_n <= (~array_muxed2);
soc_litedramcore_dfi_p0_ras_n <= (~array_muxed3);
soc_litedramcore_dfi_p0_we_n <= (~array_muxed4);
soc_litedramcore_dfi_p0_rddata_en <= array_muxed5;
soc_litedramcore_dfi_p0_wrdata_en <= array_muxed6;
soc_litedramcore_dfi_p1_cs_n <= 1'd0;
soc_litedramcore_dfi_p1_bank <= array_muxed7;
soc_litedramcore_dfi_p1_address <= array_muxed8;
soc_litedramcore_dfi_p1_cas_n <= (~array_muxed9);
soc_litedramcore_dfi_p1_ras_n <= (~array_muxed10);
soc_litedramcore_dfi_p1_we_n <= (~array_muxed11);
soc_litedramcore_dfi_p1_rddata_en <= array_muxed12;
soc_litedramcore_dfi_p1_wrdata_en <= array_muxed13;
soc_litedramcore_dfi_p2_cs_n <= 1'd0;
soc_litedramcore_dfi_p2_bank <= array_muxed14;
soc_litedramcore_dfi_p2_address <= array_muxed15;
soc_litedramcore_dfi_p2_cas_n <= (~array_muxed16);
soc_litedramcore_dfi_p2_ras_n <= (~array_muxed17);
soc_litedramcore_dfi_p2_we_n <= (~array_muxed18);
soc_litedramcore_dfi_p2_rddata_en <= array_muxed19;
soc_litedramcore_dfi_p2_wrdata_en <= array_muxed20;
soc_litedramcore_dfi_p3_cs_n <= 1'd0;
soc_litedramcore_dfi_p3_bank <= array_muxed21;
soc_litedramcore_dfi_p3_address <= array_muxed22;
soc_litedramcore_dfi_p3_cas_n <= (~array_muxed23);
soc_litedramcore_dfi_p3_ras_n <= (~array_muxed24);
soc_litedramcore_dfi_p3_we_n <= (~array_muxed25);
soc_litedramcore_dfi_p3_rddata_en <= array_muxed26;
soc_litedramcore_dfi_p3_wrdata_en <= array_muxed27;
if (soc_litedramcore_trrdcon_valid) begin
soc_litedramcore_trrdcon_count <= 1'd1;
if (1'd0) begin
soc_litedramcore_trrdcon_ready <= 1'd1;
end else begin
soc_litedramcore_trrdcon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_trrdcon_ready)) begin
soc_litedramcore_trrdcon_count <= (soc_litedramcore_trrdcon_count - 1'd1);
if ((soc_litedramcore_trrdcon_count == 1'd1)) begin
soc_litedramcore_trrdcon_ready <= 1'd1;
end
end
end
soc_litedramcore_tfawcon_window <= {soc_litedramcore_tfawcon_window, soc_litedramcore_tfawcon_valid};
if ((soc_litedramcore_tfawcon_count < 3'd4)) begin
if ((soc_litedramcore_tfawcon_count == 2'd3)) begin
soc_litedramcore_tfawcon_ready <= (~soc_litedramcore_tfawcon_valid);
end else begin
soc_litedramcore_tfawcon_ready <= 1'd1;
end
end
if (soc_litedramcore_tccdcon_valid) begin
soc_litedramcore_tccdcon_count <= 1'd0;
if (1'd1) begin
soc_litedramcore_tccdcon_ready <= 1'd1;
end else begin
soc_litedramcore_tccdcon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_tccdcon_ready)) begin
soc_litedramcore_tccdcon_count <= (soc_litedramcore_tccdcon_count - 1'd1);
if ((soc_litedramcore_tccdcon_count == 1'd1)) begin
soc_litedramcore_tccdcon_ready <= 1'd1;
end
end
end
if (soc_litedramcore_twtrcon_valid) begin
soc_litedramcore_twtrcon_count <= 3'd4;
if (1'd0) begin
soc_litedramcore_twtrcon_ready <= 1'd1;
end else begin
soc_litedramcore_twtrcon_ready <= 1'd0;
end
end else begin
if ((~soc_litedramcore_twtrcon_ready)) begin
soc_litedramcore_twtrcon_count <= (soc_litedramcore_twtrcon_count - 1'd1);
if ((soc_litedramcore_twtrcon_count == 1'd1)) begin
soc_litedramcore_twtrcon_ready <= 1'd1;
end
end
end
multiplexer_state <= multiplexer_next_state;
new_master_wdata_ready0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_wdata_ready)) | ((roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_wdata_ready)) | ((roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_wdata_ready)) | ((roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_wdata_ready)) | ((roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_wdata_ready)) | ((roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_wdata_ready)) | ((roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_wdata_ready)) | ((roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_wdata_ready));
new_master_wdata_ready1 <= new_master_wdata_ready0;
new_master_rdata_valid0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_rdata_valid)) | ((roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_rdata_valid)) | ((roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_rdata_valid)) | ((roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_rdata_valid)) | ((roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_rdata_valid)) | ((roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_rdata_valid)) | ((roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_rdata_valid)) | ((roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_rdata_valid));
new_master_rdata_valid1 <= new_master_rdata_valid0;
new_master_rdata_valid2 <= new_master_rdata_valid1;
new_master_rdata_valid3 <= new_master_rdata_valid2;
new_master_rdata_valid4 <= new_master_rdata_valid3;
new_master_rdata_valid5 <= new_master_rdata_valid4;
new_master_rdata_valid6 <= new_master_rdata_valid5;
new_master_rdata_valid7 <= new_master_rdata_valid6;
new_master_rdata_valid8 <= new_master_rdata_valid7;
state <= next_state;
if (litedramcore_dat_w_next_value_ce0) begin
litedramcore_dat_w <= litedramcore_dat_w_next_value0;
end
if (litedramcore_adr_next_value_ce1) begin
litedramcore_adr <= litedramcore_adr_next_value1;
end
if (litedramcore_we_next_value_ce2) begin
litedramcore_we <= litedramcore_we_next_value2;
end
interface0_bank_bus_dat_r <= 1'd0;
if (csrbank0_sel) begin
case (interface0_bank_bus_adr[8:0])
1'd0: begin
interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
end
1'd1: begin
interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
end
endcase
end
if (csrbank0_init_done0_re) begin
soc_init_done_storage <= csrbank0_init_done0_r;
end
soc_init_done_re <= csrbank0_init_done0_re;
if (csrbank0_init_error0_re) begin
soc_init_error_storage <= csrbank0_init_error0_r;
end
soc_init_error_re <= csrbank0_init_error0_re;
interface1_bank_bus_dat_r <= 1'd0;
if (csrbank1_sel) begin
case (interface1_bank_bus_adr[8:0])
1'd0: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_control0_w;
end
1'd1: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_command0_w;
end
2'd2: begin
interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector0_command_issue_w;
end
2'd3: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address1_w;
end
3'd4: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address0_w;
end
3'd5: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_baddress0_w;
end
3'd6: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata3_w;
end
3'd7: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata2_w;
end
4'd8: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata1_w;
end
4'd9: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata0_w;
end
4'd10: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata3_w;
end
4'd11: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata2_w;
end
4'd12: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata1_w;
end
4'd13: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata0_w;
end
4'd14: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_command0_w;
end
4'd15: begin
interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector1_command_issue_w;
end
5'd16: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address1_w;
end
5'd17: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address0_w;
end
5'd18: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_baddress0_w;
end
5'd19: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata3_w;
end
5'd20: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata2_w;
end
5'd21: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata1_w;
end
5'd22: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata0_w;
end
5'd23: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata3_w;
end
5'd24: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata2_w;
end
5'd25: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata1_w;
end
5'd26: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata0_w;
end
5'd27: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_command0_w;
end
5'd28: begin
interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector2_command_issue_w;
end
5'd29: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address1_w;
end
5'd30: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address0_w;
end
5'd31: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_baddress0_w;
end
6'd32: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata3_w;
end
6'd33: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata2_w;
end
6'd34: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata1_w;
end
6'd35: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata0_w;
end
6'd36: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata3_w;
end
6'd37: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata2_w;
end
6'd38: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata1_w;
end
6'd39: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata0_w;
end
6'd40: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_command0_w;
end
6'd41: begin
interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector3_command_issue_w;
end
6'd42: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address1_w;
end
6'd43: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address0_w;
end
6'd44: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_baddress0_w;
end
6'd45: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata3_w;
end
6'd46: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata2_w;
end
6'd47: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata1_w;
end
6'd48: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata0_w;
end
6'd49: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata3_w;
end
6'd50: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata2_w;
end
6'd51: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata1_w;
end
6'd52: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata0_w;
end
endcase
end
if (csrbank1_dfii_control0_re) begin
soc_litedramcore_storage[3:0] <= csrbank1_dfii_control0_r;
end
soc_litedramcore_re <= csrbank1_dfii_control0_re;
if (csrbank1_dfii_pi0_command0_re) begin
soc_litedramcore_phaseinjector0_command_storage[5:0] <= csrbank1_dfii_pi0_command0_r;
end
soc_litedramcore_phaseinjector0_command_re <= csrbank1_dfii_pi0_command0_re;
if (csrbank1_dfii_pi0_address1_re) begin
soc_litedramcore_phaseinjector0_address_storage[13:8] <= csrbank1_dfii_pi0_address1_r;
end
if (csrbank1_dfii_pi0_address0_re) begin
soc_litedramcore_phaseinjector0_address_storage[7:0] <= csrbank1_dfii_pi0_address0_r;
end
soc_litedramcore_phaseinjector0_address_re <= csrbank1_dfii_pi0_address0_re;
if (csrbank1_dfii_pi0_baddress0_re) begin
soc_litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank1_dfii_pi0_baddress0_r;
end
soc_litedramcore_phaseinjector0_baddress_re <= csrbank1_dfii_pi0_baddress0_re;
if (csrbank1_dfii_pi0_wrdata3_re) begin
soc_litedramcore_phaseinjector0_wrdata_storage[31:24] <= csrbank1_dfii_pi0_wrdata3_r;
end
if (csrbank1_dfii_pi0_wrdata2_re) begin
soc_litedramcore_phaseinjector0_wrdata_storage[23:16] <= csrbank1_dfii_pi0_wrdata2_r;
end
if (csrbank1_dfii_pi0_wrdata1_re) begin
soc_litedramcore_phaseinjector0_wrdata_storage[15:8] <= csrbank1_dfii_pi0_wrdata1_r;
end
if (csrbank1_dfii_pi0_wrdata0_re) begin
soc_litedramcore_phaseinjector0_wrdata_storage[7:0] <= csrbank1_dfii_pi0_wrdata0_r;
end
soc_litedramcore_phaseinjector0_wrdata_re <= csrbank1_dfii_pi0_wrdata0_re;
soc_litedramcore_phaseinjector0_rddata_re <= csrbank1_dfii_pi0_rddata0_re;
if (csrbank1_dfii_pi1_command0_re) begin
soc_litedramcore_phaseinjector1_command_storage[5:0] <= csrbank1_dfii_pi1_command0_r;
end
soc_litedramcore_phaseinjector1_command_re <= csrbank1_dfii_pi1_command0_re;
if (csrbank1_dfii_pi1_address1_re) begin
soc_litedramcore_phaseinjector1_address_storage[13:8] <= csrbank1_dfii_pi1_address1_r;
end
if (csrbank1_dfii_pi1_address0_re) begin
soc_litedramcore_phaseinjector1_address_storage[7:0] <= csrbank1_dfii_pi1_address0_r;
end
soc_litedramcore_phaseinjector1_address_re <= csrbank1_dfii_pi1_address0_re;
if (csrbank1_dfii_pi1_baddress0_re) begin
soc_litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank1_dfii_pi1_baddress0_r;
end
soc_litedramcore_phaseinjector1_baddress_re <= csrbank1_dfii_pi1_baddress0_re;
if (csrbank1_dfii_pi1_wrdata3_re) begin
soc_litedramcore_phaseinjector1_wrdata_storage[31:24] <= csrbank1_dfii_pi1_wrdata3_r;
end
if (csrbank1_dfii_pi1_wrdata2_re) begin
soc_litedramcore_phaseinjector1_wrdata_storage[23:16] <= csrbank1_dfii_pi1_wrdata2_r;
end
if (csrbank1_dfii_pi1_wrdata1_re) begin
soc_litedramcore_phaseinjector1_wrdata_storage[15:8] <= csrbank1_dfii_pi1_wrdata1_r;
end
if (csrbank1_dfii_pi1_wrdata0_re) begin
soc_litedramcore_phaseinjector1_wrdata_storage[7:0] <= csrbank1_dfii_pi1_wrdata0_r;
end
soc_litedramcore_phaseinjector1_wrdata_re <= csrbank1_dfii_pi1_wrdata0_re;
soc_litedramcore_phaseinjector1_rddata_re <= csrbank1_dfii_pi1_rddata0_re;
if (csrbank1_dfii_pi2_command0_re) begin
soc_litedramcore_phaseinjector2_command_storage[5:0] <= csrbank1_dfii_pi2_command0_r;
end
soc_litedramcore_phaseinjector2_command_re <= csrbank1_dfii_pi2_command0_re;
if (csrbank1_dfii_pi2_address1_re) begin
soc_litedramcore_phaseinjector2_address_storage[13:8] <= csrbank1_dfii_pi2_address1_r;
end
if (csrbank1_dfii_pi2_address0_re) begin
soc_litedramcore_phaseinjector2_address_storage[7:0] <= csrbank1_dfii_pi2_address0_r;
end
soc_litedramcore_phaseinjector2_address_re <= csrbank1_dfii_pi2_address0_re;
if (csrbank1_dfii_pi2_baddress0_re) begin
soc_litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank1_dfii_pi2_baddress0_r;
end
soc_litedramcore_phaseinjector2_baddress_re <= csrbank1_dfii_pi2_baddress0_re;
if (csrbank1_dfii_pi2_wrdata3_re) begin
soc_litedramcore_phaseinjector2_wrdata_storage[31:24] <= csrbank1_dfii_pi2_wrdata3_r;
end
if (csrbank1_dfii_pi2_wrdata2_re) begin
soc_litedramcore_phaseinjector2_wrdata_storage[23:16] <= csrbank1_dfii_pi2_wrdata2_r;
end
if (csrbank1_dfii_pi2_wrdata1_re) begin
soc_litedramcore_phaseinjector2_wrdata_storage[15:8] <= csrbank1_dfii_pi2_wrdata1_r;
end
if (csrbank1_dfii_pi2_wrdata0_re) begin
soc_litedramcore_phaseinjector2_wrdata_storage[7:0] <= csrbank1_dfii_pi2_wrdata0_r;
end
soc_litedramcore_phaseinjector2_wrdata_re <= csrbank1_dfii_pi2_wrdata0_re;
soc_litedramcore_phaseinjector2_rddata_re <= csrbank1_dfii_pi2_rddata0_re;
if (csrbank1_dfii_pi3_command0_re) begin
soc_litedramcore_phaseinjector3_command_storage[5:0] <= csrbank1_dfii_pi3_command0_r;
end
soc_litedramcore_phaseinjector3_command_re <= csrbank1_dfii_pi3_command0_re;
if (csrbank1_dfii_pi3_address1_re) begin
soc_litedramcore_phaseinjector3_address_storage[13:8] <= csrbank1_dfii_pi3_address1_r;
end
if (csrbank1_dfii_pi3_address0_re) begin
soc_litedramcore_phaseinjector3_address_storage[7:0] <= csrbank1_dfii_pi3_address0_r;
end
soc_litedramcore_phaseinjector3_address_re <= csrbank1_dfii_pi3_address0_re;
if (csrbank1_dfii_pi3_baddress0_re) begin
soc_litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank1_dfii_pi3_baddress0_r;
end
soc_litedramcore_phaseinjector3_baddress_re <= csrbank1_dfii_pi3_baddress0_re;
if (csrbank1_dfii_pi3_wrdata3_re) begin
soc_litedramcore_phaseinjector3_wrdata_storage[31:24] <= csrbank1_dfii_pi3_wrdata3_r;
end
if (csrbank1_dfii_pi3_wrdata2_re) begin
soc_litedramcore_phaseinjector3_wrdata_storage[23:16] <= csrbank1_dfii_pi3_wrdata2_r;
end
if (csrbank1_dfii_pi3_wrdata1_re) begin
soc_litedramcore_phaseinjector3_wrdata_storage[15:8] <= csrbank1_dfii_pi3_wrdata1_r;
end
if (csrbank1_dfii_pi3_wrdata0_re) begin
soc_litedramcore_phaseinjector3_wrdata_storage[7:0] <= csrbank1_dfii_pi3_wrdata0_r;
end
soc_litedramcore_phaseinjector3_wrdata_re <= csrbank1_dfii_pi3_wrdata0_re;
soc_litedramcore_phaseinjector3_rddata_re <= csrbank1_dfii_pi3_rddata0_re;
if (sys_rst) begin
soc_ddrphy_bankmodel0_active <= 1'd0;
soc_ddrphy_bankmodel0_row <= 14'd0;
soc_ddrphy_bankmodel1_active <= 1'd0;
soc_ddrphy_bankmodel1_row <= 14'd0;
soc_ddrphy_bankmodel2_active <= 1'd0;
soc_ddrphy_bankmodel2_row <= 14'd0;
soc_ddrphy_bankmodel3_active <= 1'd0;
soc_ddrphy_bankmodel3_row <= 14'd0;
soc_ddrphy_bankmodel4_active <= 1'd0;
soc_ddrphy_bankmodel4_row <= 14'd0;
soc_ddrphy_bankmodel5_active <= 1'd0;
soc_ddrphy_bankmodel5_row <= 14'd0;
soc_ddrphy_bankmodel6_active <= 1'd0;
soc_ddrphy_bankmodel6_row <= 14'd0;
soc_ddrphy_bankmodel7_active <= 1'd0;
soc_ddrphy_bankmodel7_row <= 14'd0;
soc_ddrphy_new_bank_write0 <= 1'd0;
soc_ddrphy_new_bank_write_col0 <= 10'd0;
soc_ddrphy_new_bank_write1 <= 1'd0;
soc_ddrphy_new_bank_write_col1 <= 10'd0;
soc_ddrphy_new_bank_write2 <= 1'd0;
soc_ddrphy_new_bank_write_col2 <= 10'd0;
soc_ddrphy_new_bank_write3 <= 1'd0;
soc_ddrphy_new_bank_write_col3 <= 10'd0;
soc_ddrphy_new_bank_write4 <= 1'd0;
soc_ddrphy_new_bank_write_col4 <= 10'd0;
soc_ddrphy_new_bank_write5 <= 1'd0;
soc_ddrphy_new_bank_write_col5 <= 10'd0;
soc_ddrphy_new_bank_write6 <= 1'd0;
soc_ddrphy_new_bank_write_col6 <= 10'd0;
soc_ddrphy_new_bank_write7 <= 1'd0;
soc_ddrphy_new_bank_write_col7 <= 10'd0;
soc_ddrphy_new_banks_read0 <= 1'd0;
soc_ddrphy_new_banks_read_data0 <= 128'd0;
soc_ddrphy_new_banks_read1 <= 1'd0;
soc_ddrphy_new_banks_read_data1 <= 128'd0;
soc_ddrphy_new_banks_read2 <= 1'd0;
soc_ddrphy_new_banks_read_data2 <= 128'd0;
soc_ddrphy_new_banks_read3 <= 1'd0;
soc_ddrphy_new_banks_read_data3 <= 128'd0;
soc_ddrphy_new_banks_read4 <= 1'd0;
soc_ddrphy_new_banks_read_data4 <= 128'd0;
soc_ddrphy_new_banks_read5 <= 1'd0;
soc_ddrphy_new_banks_read_data5 <= 128'd0;
soc_ddrphy_new_banks_read6 <= 1'd0;
soc_ddrphy_new_banks_read_data6 <= 128'd0;
soc_ddrphy_new_banks_read7 <= 1'd0;
soc_ddrphy_new_banks_read_data7 <= 128'd0;
soc_litedramcore_storage <= 4'd1;
soc_litedramcore_re <= 1'd0;
soc_litedramcore_phaseinjector0_command_storage <= 6'd0;
soc_litedramcore_phaseinjector0_command_re <= 1'd0;
soc_litedramcore_phaseinjector0_address_re <= 1'd0;
soc_litedramcore_phaseinjector0_baddress_re <= 1'd0;
soc_litedramcore_phaseinjector0_wrdata_re <= 1'd0;
soc_litedramcore_phaseinjector0_rddata_status <= 32'd0;
soc_litedramcore_phaseinjector0_rddata_re <= 1'd0;
soc_litedramcore_phaseinjector1_command_storage <= 6'd0;
soc_litedramcore_phaseinjector1_command_re <= 1'd0;
soc_litedramcore_phaseinjector1_address_re <= 1'd0;
soc_litedramcore_phaseinjector1_baddress_re <= 1'd0;
soc_litedramcore_phaseinjector1_wrdata_re <= 1'd0;
soc_litedramcore_phaseinjector1_rddata_status <= 32'd0;
soc_litedramcore_phaseinjector1_rddata_re <= 1'd0;
soc_litedramcore_phaseinjector2_command_storage <= 6'd0;
soc_litedramcore_phaseinjector2_command_re <= 1'd0;
soc_litedramcore_phaseinjector2_address_re <= 1'd0;
soc_litedramcore_phaseinjector2_baddress_re <= 1'd0;
soc_litedramcore_phaseinjector2_wrdata_re <= 1'd0;
soc_litedramcore_phaseinjector2_rddata_status <= 32'd0;
soc_litedramcore_phaseinjector2_rddata_re <= 1'd0;
soc_litedramcore_phaseinjector3_command_storage <= 6'd0;
soc_litedramcore_phaseinjector3_command_re <= 1'd0;
soc_litedramcore_phaseinjector3_address_re <= 1'd0;
soc_litedramcore_phaseinjector3_baddress_re <= 1'd0;
soc_litedramcore_phaseinjector3_wrdata_re <= 1'd0;
soc_litedramcore_phaseinjector3_rddata_status <= 32'd0;
soc_litedramcore_phaseinjector3_rddata_re <= 1'd0;
soc_litedramcore_dfi_p0_address <= 14'd0;
soc_litedramcore_dfi_p0_bank <= 3'd0;
soc_litedramcore_dfi_p0_cas_n <= 1'd1;
soc_litedramcore_dfi_p0_cs_n <= 1'd1;
soc_litedramcore_dfi_p0_ras_n <= 1'd1;
soc_litedramcore_dfi_p0_we_n <= 1'd1;
soc_litedramcore_dfi_p0_wrdata_en <= 1'd0;
soc_litedramcore_dfi_p0_rddata_en <= 1'd0;
soc_litedramcore_dfi_p1_address <= 14'd0;
soc_litedramcore_dfi_p1_bank <= 3'd0;
soc_litedramcore_dfi_p1_cas_n <= 1'd1;
soc_litedramcore_dfi_p1_cs_n <= 1'd1;
soc_litedramcore_dfi_p1_ras_n <= 1'd1;
soc_litedramcore_dfi_p1_we_n <= 1'd1;
soc_litedramcore_dfi_p1_wrdata_en <= 1'd0;
soc_litedramcore_dfi_p1_rddata_en <= 1'd0;
soc_litedramcore_dfi_p2_address <= 14'd0;
soc_litedramcore_dfi_p2_bank <= 3'd0;
soc_litedramcore_dfi_p2_cas_n <= 1'd1;
soc_litedramcore_dfi_p2_cs_n <= 1'd1;
soc_litedramcore_dfi_p2_ras_n <= 1'd1;
soc_litedramcore_dfi_p2_we_n <= 1'd1;
soc_litedramcore_dfi_p2_wrdata_en <= 1'd0;
soc_litedramcore_dfi_p2_rddata_en <= 1'd0;
soc_litedramcore_dfi_p3_address <= 14'd0;
soc_litedramcore_dfi_p3_bank <= 3'd0;
soc_litedramcore_dfi_p3_cas_n <= 1'd1;
soc_litedramcore_dfi_p3_cs_n <= 1'd1;
soc_litedramcore_dfi_p3_ras_n <= 1'd1;
soc_litedramcore_dfi_p3_we_n <= 1'd1;
soc_litedramcore_dfi_p3_wrdata_en <= 1'd0;
soc_litedramcore_dfi_p3_rddata_en <= 1'd0;
soc_litedramcore_cmd_payload_a <= 14'd0;
soc_litedramcore_cmd_payload_ba <= 3'd0;
soc_litedramcore_cmd_payload_cas <= 1'd0;
soc_litedramcore_cmd_payload_ras <= 1'd0;
soc_litedramcore_cmd_payload_we <= 1'd0;
soc_litedramcore_timer_count1 <= 10'd781;
soc_litedramcore_postponer_req_o <= 1'd0;
soc_litedramcore_postponer_count <= 1'd0;
soc_litedramcore_sequencer_done1 <= 1'd0;
soc_litedramcore_sequencer_counter <= 6'd0;
soc_litedramcore_sequencer_count <= 1'd0;
soc_litedramcore_zqcs_timer_count1 <= 27'd99999999;
soc_litedramcore_zqcs_executer_done <= 1'd0;
soc_litedramcore_zqcs_executer_counter <= 5'd0;
soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
soc_litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0;
soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 21'd0;
soc_litedramcore_bankmachine0_row <= 14'd0;
soc_litedramcore_bankmachine0_row_opened <= 1'd0;
soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
soc_litedramcore_bankmachine0_twtpcon_count <= 3'd0;
soc_litedramcore_bankmachine0_trccon_ready <= 1'd0;
soc_litedramcore_bankmachine0_trccon_count <= 3'd0;
soc_litedramcore_bankmachine0_trascon_ready <= 1'd0;
soc_litedramcore_bankmachine0_trascon_count <= 3'd0;
soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
soc_litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0;
soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 21'd0;
soc_litedramcore_bankmachine1_row <= 14'd0;
soc_litedramcore_bankmachine1_row_opened <= 1'd0;
soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
soc_litedramcore_bankmachine1_twtpcon_count <= 3'd0;
soc_litedramcore_bankmachine1_trccon_ready <= 1'd0;
soc_litedramcore_bankmachine1_trccon_count <= 3'd0;
soc_litedramcore_bankmachine1_trascon_ready <= 1'd0;
soc_litedramcore_bankmachine1_trascon_count <= 3'd0;
soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
soc_litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0;
soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 21'd0;
soc_litedramcore_bankmachine2_row <= 14'd0;
soc_litedramcore_bankmachine2_row_opened <= 1'd0;
soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
soc_litedramcore_bankmachine2_twtpcon_count <= 3'd0;
soc_litedramcore_bankmachine2_trccon_ready <= 1'd0;
soc_litedramcore_bankmachine2_trccon_count <= 3'd0;
soc_litedramcore_bankmachine2_trascon_ready <= 1'd0;
soc_litedramcore_bankmachine2_trascon_count <= 3'd0;
soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
soc_litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0;
soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 21'd0;
soc_litedramcore_bankmachine3_row <= 14'd0;
soc_litedramcore_bankmachine3_row_opened <= 1'd0;
soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
soc_litedramcore_bankmachine3_twtpcon_count <= 3'd0;
soc_litedramcore_bankmachine3_trccon_ready <= 1'd0;
soc_litedramcore_bankmachine3_trccon_count <= 3'd0;
soc_litedramcore_bankmachine3_trascon_ready <= 1'd0;
soc_litedramcore_bankmachine3_trascon_count <= 3'd0;
soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
soc_litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0;
soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 21'd0;
soc_litedramcore_bankmachine4_row <= 14'd0;
soc_litedramcore_bankmachine4_row_opened <= 1'd0;
soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
soc_litedramcore_bankmachine4_twtpcon_count <= 3'd0;
soc_litedramcore_bankmachine4_trccon_ready <= 1'd0;
soc_litedramcore_bankmachine4_trccon_count <= 3'd0;
soc_litedramcore_bankmachine4_trascon_ready <= 1'd0;
soc_litedramcore_bankmachine4_trascon_count <= 3'd0;
soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
soc_litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0;
soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 21'd0;
soc_litedramcore_bankmachine5_row <= 14'd0;
soc_litedramcore_bankmachine5_row_opened <= 1'd0;
soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
soc_litedramcore_bankmachine5_twtpcon_count <= 3'd0;
soc_litedramcore_bankmachine5_trccon_ready <= 1'd0;
soc_litedramcore_bankmachine5_trccon_count <= 3'd0;
soc_litedramcore_bankmachine5_trascon_ready <= 1'd0;
soc_litedramcore_bankmachine5_trascon_count <= 3'd0;
soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
soc_litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0;
soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 21'd0;
soc_litedramcore_bankmachine6_row <= 14'd0;
soc_litedramcore_bankmachine6_row_opened <= 1'd0;
soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
soc_litedramcore_bankmachine6_twtpcon_count <= 3'd0;
soc_litedramcore_bankmachine6_trccon_ready <= 1'd0;
soc_litedramcore_bankmachine6_trccon_count <= 3'd0;
soc_litedramcore_bankmachine6_trascon_ready <= 1'd0;
soc_litedramcore_bankmachine6_trascon_count <= 3'd0;
soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
soc_litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0;
soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 21'd0;
soc_litedramcore_bankmachine7_row <= 14'd0;
soc_litedramcore_bankmachine7_row_opened <= 1'd0;
soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
soc_litedramcore_bankmachine7_twtpcon_count <= 3'd0;
soc_litedramcore_bankmachine7_trccon_ready <= 1'd0;
soc_litedramcore_bankmachine7_trccon_count <= 3'd0;
soc_litedramcore_bankmachine7_trascon_ready <= 1'd0;
soc_litedramcore_bankmachine7_trascon_count <= 3'd0;
soc_litedramcore_choose_cmd_grant <= 3'd0;
soc_litedramcore_choose_req_grant <= 3'd0;
soc_litedramcore_trrdcon_ready <= 1'd0;
soc_litedramcore_trrdcon_count <= 1'd0;
soc_litedramcore_tfawcon_ready <= 1'd1;
soc_litedramcore_tfawcon_window <= 5'd0;
soc_litedramcore_tccdcon_ready <= 1'd0;
soc_litedramcore_tccdcon_count <= 1'd0;
soc_litedramcore_twtrcon_ready <= 1'd0;
soc_litedramcore_twtrcon_count <= 3'd0;
soc_litedramcore_time0 <= 5'd0;
soc_litedramcore_time1 <= 4'd0;
soc_init_done_storage <= 1'd0;
soc_init_done_re <= 1'd0;
soc_init_error_storage <= 1'd0;
soc_init_error_re <= 1'd0;
refresher_state <= 2'd0;
bankmachine0_state <= 4'd0;
bankmachine1_state <= 4'd0;
bankmachine2_state <= 4'd0;
bankmachine3_state <= 4'd0;
bankmachine4_state <= 4'd0;
bankmachine5_state <= 4'd0;
bankmachine6_state <= 4'd0;
bankmachine7_state <= 4'd0;
multiplexer_state <= 4'd0;
new_master_wdata_ready0 <= 1'd0;
new_master_wdata_ready1 <= 1'd0;
new_master_rdata_valid0 <= 1'd0;
new_master_rdata_valid1 <= 1'd0;
new_master_rdata_valid2 <= 1'd0;
new_master_rdata_valid3 <= 1'd0;
new_master_rdata_valid4 <= 1'd0;
new_master_rdata_valid5 <= 1'd0;
new_master_rdata_valid6 <= 1'd0;
new_master_rdata_valid7 <= 1'd0;
new_master_rdata_valid8 <= 1'd0;
litedramcore_we <= 1'd0;
state <= 2'd0;
end
end
reg [127:0] mem[0:2097151];
reg [20:0] memadr;
always @(posedge sys_clk) begin
if (soc_ddrphy_bankmodel0_write_port_we[0])
mem[soc_ddrphy_bankmodel0_write_port_adr][7:0] <= soc_ddrphy_bankmodel0_write_port_dat_w[7:0];
if (soc_ddrphy_bankmodel0_write_port_we[1])
mem[soc_ddrphy_bankmodel0_write_port_adr][15:8] <= soc_ddrphy_bankmodel0_write_port_dat_w[15:8];
if (soc_ddrphy_bankmodel0_write_port_we[2])
mem[soc_ddrphy_bankmodel0_write_port_adr][23:16] <= soc_ddrphy_bankmodel0_write_port_dat_w[23:16];
if (soc_ddrphy_bankmodel0_write_port_we[3])
mem[soc_ddrphy_bankmodel0_write_port_adr][31:24] <= soc_ddrphy_bankmodel0_write_port_dat_w[31:24];
if (soc_ddrphy_bankmodel0_write_port_we[4])
mem[soc_ddrphy_bankmodel0_write_port_adr][39:32] <= soc_ddrphy_bankmodel0_write_port_dat_w[39:32];
if (soc_ddrphy_bankmodel0_write_port_we[5])
mem[soc_ddrphy_bankmodel0_write_port_adr][47:40] <= soc_ddrphy_bankmodel0_write_port_dat_w[47:40];
if (soc_ddrphy_bankmodel0_write_port_we[6])
mem[soc_ddrphy_bankmodel0_write_port_adr][55:48] <= soc_ddrphy_bankmodel0_write_port_dat_w[55:48];
if (soc_ddrphy_bankmodel0_write_port_we[7])
mem[soc_ddrphy_bankmodel0_write_port_adr][63:56] <= soc_ddrphy_bankmodel0_write_port_dat_w[63:56];
if (soc_ddrphy_bankmodel0_write_port_we[8])
mem[soc_ddrphy_bankmodel0_write_port_adr][71:64] <= soc_ddrphy_bankmodel0_write_port_dat_w[71:64];
if (soc_ddrphy_bankmodel0_write_port_we[9])
mem[soc_ddrphy_bankmodel0_write_port_adr][79:72] <= soc_ddrphy_bankmodel0_write_port_dat_w[79:72];
if (soc_ddrphy_bankmodel0_write_port_we[10])
mem[soc_ddrphy_bankmodel0_write_port_adr][87:80] <= soc_ddrphy_bankmodel0_write_port_dat_w[87:80];
if (soc_ddrphy_bankmodel0_write_port_we[11])
mem[soc_ddrphy_bankmodel0_write_port_adr][95:88] <= soc_ddrphy_bankmodel0_write_port_dat_w[95:88];
if (soc_ddrphy_bankmodel0_write_port_we[12])
mem[soc_ddrphy_bankmodel0_write_port_adr][103:96] <= soc_ddrphy_bankmodel0_write_port_dat_w[103:96];
if (soc_ddrphy_bankmodel0_write_port_we[13])
mem[soc_ddrphy_bankmodel0_write_port_adr][111:104] <= soc_ddrphy_bankmodel0_write_port_dat_w[111:104];
if (soc_ddrphy_bankmodel0_write_port_we[14])
mem[soc_ddrphy_bankmodel0_write_port_adr][119:112] <= soc_ddrphy_bankmodel0_write_port_dat_w[119:112];
if (soc_ddrphy_bankmodel0_write_port_we[15])
mem[soc_ddrphy_bankmodel0_write_port_adr][127:120] <= soc_ddrphy_bankmodel0_write_port_dat_w[127:120];
memadr <= soc_ddrphy_bankmodel0_write_port_adr;
end
always @(posedge sys_clk) begin
end
assign soc_ddrphy_bankmodel0_write_port_dat_r = mem[memadr];
assign soc_ddrphy_bankmodel0_read_port_dat_r = mem[soc_ddrphy_bankmodel0_read_port_adr];
reg [127:0] mem_1[0:2097151];
reg [20:0] memadr_1;
always @(posedge sys_clk) begin
if (soc_ddrphy_bankmodel1_write_port_we[0])
mem_1[soc_ddrphy_bankmodel1_write_port_adr][7:0] <= soc_ddrphy_bankmodel1_write_port_dat_w[7:0];
if (soc_ddrphy_bankmodel1_write_port_we[1])
mem_1[soc_ddrphy_bankmodel1_write_port_adr][15:8] <= soc_ddrphy_bankmodel1_write_port_dat_w[15:8];
if (soc_ddrphy_bankmodel1_write_port_we[2])
mem_1[soc_ddrphy_bankmodel1_write_port_adr][23:16] <= soc_ddrphy_bankmodel1_write_port_dat_w[23:16];
if (soc_ddrphy_bankmodel1_write_port_we[3])
mem_1[soc_ddrphy_bankmodel1_write_port_adr][31:24] <= soc_ddrphy_bankmodel1_write_port_dat_w[31:24];
if (soc_ddrphy_bankmodel1_write_port_we[4])
mem_1[soc_ddrphy_bankmodel1_write_port_adr][39:32] <= soc_ddrphy_bankmodel1_write_port_dat_w[39:32];
if (soc_ddrphy_bankmodel1_write_port_we[5])
mem_1[soc_ddrphy_bankmodel1_write_port_adr][47:40] <= soc_ddrphy_bankmodel1_write_port_dat_w[47:40];
if (soc_ddrphy_bankmodel1_write_port_we[6])
mem_1[soc_ddrphy_bankmodel1_write_port_adr][55:48] <= soc_ddrphy_bankmodel1_write_port_dat_w[55:48];
if (soc_ddrphy_bankmodel1_write_port_we[7])
mem_1[soc_ddrphy_bankmodel1_write_port_adr][63:56] <= soc_ddrphy_bankmodel1_write_port_dat_w[63:56];
if (soc_ddrphy_bankmodel1_write_port_we[8])
mem_1[soc_ddrphy_bankmodel1_write_port_adr][71:64] <= soc_ddrphy_bankmodel1_write_port_dat_w[71:64];
if (soc_ddrphy_bankmodel1_write_port_we[9])
mem_1[soc_ddrphy_bankmodel1_write_port_adr][79:72] <= soc_ddrphy_bankmodel1_write_port_dat_w[79:72];
if (soc_ddrphy_bankmodel1_write_port_we[10])
mem_1[soc_ddrphy_bankmodel1_write_port_adr][87:80] <= soc_ddrphy_bankmodel1_write_port_dat_w[87:80];
if (soc_ddrphy_bankmodel1_write_port_we[11])
mem_1[soc_ddrphy_bankmodel1_write_port_adr][95:88] <= soc_ddrphy_bankmodel1_write_port_dat_w[95:88];
if (soc_ddrphy_bankmodel1_write_port_we[12])
mem_1[soc_ddrphy_bankmodel1_write_port_adr][103:96] <= soc_ddrphy_bankmodel1_write_port_dat_w[103:96];
if (soc_ddrphy_bankmodel1_write_port_we[13])
mem_1[soc_ddrphy_bankmodel1_write_port_adr][111:104] <= soc_ddrphy_bankmodel1_write_port_dat_w[111:104];
if (soc_ddrphy_bankmodel1_write_port_we[14])
mem_1[soc_ddrphy_bankmodel1_write_port_adr][119:112] <= soc_ddrphy_bankmodel1_write_port_dat_w[119:112];
if (soc_ddrphy_bankmodel1_write_port_we[15])
mem_1[soc_ddrphy_bankmodel1_write_port_adr][127:120] <= soc_ddrphy_bankmodel1_write_port_dat_w[127:120];
memadr_1 <= soc_ddrphy_bankmodel1_write_port_adr;
end
always @(posedge sys_clk) begin
end
assign soc_ddrphy_bankmodel1_write_port_dat_r = mem_1[memadr_1];
assign soc_ddrphy_bankmodel1_read_port_dat_r = mem_1[soc_ddrphy_bankmodel1_read_port_adr];
reg [127:0] mem_2[0:2097151];
reg [20:0] memadr_2;
always @(posedge sys_clk) begin
if (soc_ddrphy_bankmodel2_write_port_we[0])
mem_2[soc_ddrphy_bankmodel2_write_port_adr][7:0] <= soc_ddrphy_bankmodel2_write_port_dat_w[7:0];
if (soc_ddrphy_bankmodel2_write_port_we[1])
mem_2[soc_ddrphy_bankmodel2_write_port_adr][15:8] <= soc_ddrphy_bankmodel2_write_port_dat_w[15:8];
if (soc_ddrphy_bankmodel2_write_port_we[2])
mem_2[soc_ddrphy_bankmodel2_write_port_adr][23:16] <= soc_ddrphy_bankmodel2_write_port_dat_w[23:16];
if (soc_ddrphy_bankmodel2_write_port_we[3])
mem_2[soc_ddrphy_bankmodel2_write_port_adr][31:24] <= soc_ddrphy_bankmodel2_write_port_dat_w[31:24];
if (soc_ddrphy_bankmodel2_write_port_we[4])
mem_2[soc_ddrphy_bankmodel2_write_port_adr][39:32] <= soc_ddrphy_bankmodel2_write_port_dat_w[39:32];
if (soc_ddrphy_bankmodel2_write_port_we[5])
mem_2[soc_ddrphy_bankmodel2_write_port_adr][47:40] <= soc_ddrphy_bankmodel2_write_port_dat_w[47:40];
if (soc_ddrphy_bankmodel2_write_port_we[6])
mem_2[soc_ddrphy_bankmodel2_write_port_adr][55:48] <= soc_ddrphy_bankmodel2_write_port_dat_w[55:48];
if (soc_ddrphy_bankmodel2_write_port_we[7])
mem_2[soc_ddrphy_bankmodel2_write_port_adr][63:56] <= soc_ddrphy_bankmodel2_write_port_dat_w[63:56];
if (soc_ddrphy_bankmodel2_write_port_we[8])
mem_2[soc_ddrphy_bankmodel2_write_port_adr][71:64] <= soc_ddrphy_bankmodel2_write_port_dat_w[71:64];
if (soc_ddrphy_bankmodel2_write_port_we[9])
mem_2[soc_ddrphy_bankmodel2_write_port_adr][79:72] <= soc_ddrphy_bankmodel2_write_port_dat_w[79:72];
if (soc_ddrphy_bankmodel2_write_port_we[10])
mem_2[soc_ddrphy_bankmodel2_write_port_adr][87:80] <= soc_ddrphy_bankmodel2_write_port_dat_w[87:80];
if (soc_ddrphy_bankmodel2_write_port_we[11])
mem_2[soc_ddrphy_bankmodel2_write_port_adr][95:88] <= soc_ddrphy_bankmodel2_write_port_dat_w[95:88];
if (soc_ddrphy_bankmodel2_write_port_we[12])
mem_2[soc_ddrphy_bankmodel2_write_port_adr][103:96] <= soc_ddrphy_bankmodel2_write_port_dat_w[103:96];
if (soc_ddrphy_bankmodel2_write_port_we[13])
mem_2[soc_ddrphy_bankmodel2_write_port_adr][111:104] <= soc_ddrphy_bankmodel2_write_port_dat_w[111:104];
if (soc_ddrphy_bankmodel2_write_port_we[14])
mem_2[soc_ddrphy_bankmodel2_write_port_adr][119:112] <= soc_ddrphy_bankmodel2_write_port_dat_w[119:112];
if (soc_ddrphy_bankmodel2_write_port_we[15])
mem_2[soc_ddrphy_bankmodel2_write_port_adr][127:120] <= soc_ddrphy_bankmodel2_write_port_dat_w[127:120];
memadr_2 <= soc_ddrphy_bankmodel2_write_port_adr;
end
always @(posedge sys_clk) begin
end
assign soc_ddrphy_bankmodel2_write_port_dat_r = mem_2[memadr_2];
assign soc_ddrphy_bankmodel2_read_port_dat_r = mem_2[soc_ddrphy_bankmodel2_read_port_adr];
reg [127:0] mem_3[0:2097151];
reg [20:0] memadr_3;
always @(posedge sys_clk) begin
if (soc_ddrphy_bankmodel3_write_port_we[0])
mem_3[soc_ddrphy_bankmodel3_write_port_adr][7:0] <= soc_ddrphy_bankmodel3_write_port_dat_w[7:0];
if (soc_ddrphy_bankmodel3_write_port_we[1])
mem_3[soc_ddrphy_bankmodel3_write_port_adr][15:8] <= soc_ddrphy_bankmodel3_write_port_dat_w[15:8];
if (soc_ddrphy_bankmodel3_write_port_we[2])
mem_3[soc_ddrphy_bankmodel3_write_port_adr][23:16] <= soc_ddrphy_bankmodel3_write_port_dat_w[23:16];
if (soc_ddrphy_bankmodel3_write_port_we[3])
mem_3[soc_ddrphy_bankmodel3_write_port_adr][31:24] <= soc_ddrphy_bankmodel3_write_port_dat_w[31:24];
if (soc_ddrphy_bankmodel3_write_port_we[4])
mem_3[soc_ddrphy_bankmodel3_write_port_adr][39:32] <= soc_ddrphy_bankmodel3_write_port_dat_w[39:32];
if (soc_ddrphy_bankmodel3_write_port_we[5])
mem_3[soc_ddrphy_bankmodel3_write_port_adr][47:40] <= soc_ddrphy_bankmodel3_write_port_dat_w[47:40];
if (soc_ddrphy_bankmodel3_write_port_we[6])
mem_3[soc_ddrphy_bankmodel3_write_port_adr][55:48] <= soc_ddrphy_bankmodel3_write_port_dat_w[55:48];
if (soc_ddrphy_bankmodel3_write_port_we[7])
mem_3[soc_ddrphy_bankmodel3_write_port_adr][63:56] <= soc_ddrphy_bankmodel3_write_port_dat_w[63:56];
if (soc_ddrphy_bankmodel3_write_port_we[8])
mem_3[soc_ddrphy_bankmodel3_write_port_adr][71:64] <= soc_ddrphy_bankmodel3_write_port_dat_w[71:64];
if (soc_ddrphy_bankmodel3_write_port_we[9])
mem_3[soc_ddrphy_bankmodel3_write_port_adr][79:72] <= soc_ddrphy_bankmodel3_write_port_dat_w[79:72];
if (soc_ddrphy_bankmodel3_write_port_we[10])
mem_3[soc_ddrphy_bankmodel3_write_port_adr][87:80] <= soc_ddrphy_bankmodel3_write_port_dat_w[87:80];
if (soc_ddrphy_bankmodel3_write_port_we[11])
mem_3[soc_ddrphy_bankmodel3_write_port_adr][95:88] <= soc_ddrphy_bankmodel3_write_port_dat_w[95:88];
if (soc_ddrphy_bankmodel3_write_port_we[12])
mem_3[soc_ddrphy_bankmodel3_write_port_adr][103:96] <= soc_ddrphy_bankmodel3_write_port_dat_w[103:96];
if (soc_ddrphy_bankmodel3_write_port_we[13])
mem_3[soc_ddrphy_bankmodel3_write_port_adr][111:104] <= soc_ddrphy_bankmodel3_write_port_dat_w[111:104];
if (soc_ddrphy_bankmodel3_write_port_we[14])
mem_3[soc_ddrphy_bankmodel3_write_port_adr][119:112] <= soc_ddrphy_bankmodel3_write_port_dat_w[119:112];
if (soc_ddrphy_bankmodel3_write_port_we[15])
mem_3[soc_ddrphy_bankmodel3_write_port_adr][127:120] <= soc_ddrphy_bankmodel3_write_port_dat_w[127:120];
memadr_3 <= soc_ddrphy_bankmodel3_write_port_adr;
end
always @(posedge sys_clk) begin
end
assign soc_ddrphy_bankmodel3_write_port_dat_r = mem_3[memadr_3];
assign soc_ddrphy_bankmodel3_read_port_dat_r = mem_3[soc_ddrphy_bankmodel3_read_port_adr];
reg [127:0] mem_4[0:2097151];
reg [20:0] memadr_4;
always @(posedge sys_clk) begin
if (soc_ddrphy_bankmodel4_write_port_we[0])
mem_4[soc_ddrphy_bankmodel4_write_port_adr][7:0] <= soc_ddrphy_bankmodel4_write_port_dat_w[7:0];
if (soc_ddrphy_bankmodel4_write_port_we[1])
mem_4[soc_ddrphy_bankmodel4_write_port_adr][15:8] <= soc_ddrphy_bankmodel4_write_port_dat_w[15:8];
if (soc_ddrphy_bankmodel4_write_port_we[2])
mem_4[soc_ddrphy_bankmodel4_write_port_adr][23:16] <= soc_ddrphy_bankmodel4_write_port_dat_w[23:16];
if (soc_ddrphy_bankmodel4_write_port_we[3])
mem_4[soc_ddrphy_bankmodel4_write_port_adr][31:24] <= soc_ddrphy_bankmodel4_write_port_dat_w[31:24];
if (soc_ddrphy_bankmodel4_write_port_we[4])
mem_4[soc_ddrphy_bankmodel4_write_port_adr][39:32] <= soc_ddrphy_bankmodel4_write_port_dat_w[39:32];
if (soc_ddrphy_bankmodel4_write_port_we[5])
mem_4[soc_ddrphy_bankmodel4_write_port_adr][47:40] <= soc_ddrphy_bankmodel4_write_port_dat_w[47:40];
if (soc_ddrphy_bankmodel4_write_port_we[6])
mem_4[soc_ddrphy_bankmodel4_write_port_adr][55:48] <= soc_ddrphy_bankmodel4_write_port_dat_w[55:48];
if (soc_ddrphy_bankmodel4_write_port_we[7])
mem_4[soc_ddrphy_bankmodel4_write_port_adr][63:56] <= soc_ddrphy_bankmodel4_write_port_dat_w[63:56];
if (soc_ddrphy_bankmodel4_write_port_we[8])
mem_4[soc_ddrphy_bankmodel4_write_port_adr][71:64] <= soc_ddrphy_bankmodel4_write_port_dat_w[71:64];
if (soc_ddrphy_bankmodel4_write_port_we[9])
mem_4[soc_ddrphy_bankmodel4_write_port_adr][79:72] <= soc_ddrphy_bankmodel4_write_port_dat_w[79:72];
if (soc_ddrphy_bankmodel4_write_port_we[10])
mem_4[soc_ddrphy_bankmodel4_write_port_adr][87:80] <= soc_ddrphy_bankmodel4_write_port_dat_w[87:80];
if (soc_ddrphy_bankmodel4_write_port_we[11])
mem_4[soc_ddrphy_bankmodel4_write_port_adr][95:88] <= soc_ddrphy_bankmodel4_write_port_dat_w[95:88];
if (soc_ddrphy_bankmodel4_write_port_we[12])
mem_4[soc_ddrphy_bankmodel4_write_port_adr][103:96] <= soc_ddrphy_bankmodel4_write_port_dat_w[103:96];
if (soc_ddrphy_bankmodel4_write_port_we[13])
mem_4[soc_ddrphy_bankmodel4_write_port_adr][111:104] <= soc_ddrphy_bankmodel4_write_port_dat_w[111:104];
if (soc_ddrphy_bankmodel4_write_port_we[14])
mem_4[soc_ddrphy_bankmodel4_write_port_adr][119:112] <= soc_ddrphy_bankmodel4_write_port_dat_w[119:112];
if (soc_ddrphy_bankmodel4_write_port_we[15])
mem_4[soc_ddrphy_bankmodel4_write_port_adr][127:120] <= soc_ddrphy_bankmodel4_write_port_dat_w[127:120];
memadr_4 <= soc_ddrphy_bankmodel4_write_port_adr;
end
always @(posedge sys_clk) begin
end
assign soc_ddrphy_bankmodel4_write_port_dat_r = mem_4[memadr_4];
assign soc_ddrphy_bankmodel4_read_port_dat_r = mem_4[soc_ddrphy_bankmodel4_read_port_adr];
reg [127:0] mem_5[0:2097151];
reg [20:0] memadr_5;
always @(posedge sys_clk) begin
if (soc_ddrphy_bankmodel5_write_port_we[0])
mem_5[soc_ddrphy_bankmodel5_write_port_adr][7:0] <= soc_ddrphy_bankmodel5_write_port_dat_w[7:0];
if (soc_ddrphy_bankmodel5_write_port_we[1])
mem_5[soc_ddrphy_bankmodel5_write_port_adr][15:8] <= soc_ddrphy_bankmodel5_write_port_dat_w[15:8];
if (soc_ddrphy_bankmodel5_write_port_we[2])
mem_5[soc_ddrphy_bankmodel5_write_port_adr][23:16] <= soc_ddrphy_bankmodel5_write_port_dat_w[23:16];
if (soc_ddrphy_bankmodel5_write_port_we[3])
mem_5[soc_ddrphy_bankmodel5_write_port_adr][31:24] <= soc_ddrphy_bankmodel5_write_port_dat_w[31:24];
if (soc_ddrphy_bankmodel5_write_port_we[4])
mem_5[soc_ddrphy_bankmodel5_write_port_adr][39:32] <= soc_ddrphy_bankmodel5_write_port_dat_w[39:32];
if (soc_ddrphy_bankmodel5_write_port_we[5])
mem_5[soc_ddrphy_bankmodel5_write_port_adr][47:40] <= soc_ddrphy_bankmodel5_write_port_dat_w[47:40];
if (soc_ddrphy_bankmodel5_write_port_we[6])
mem_5[soc_ddrphy_bankmodel5_write_port_adr][55:48] <= soc_ddrphy_bankmodel5_write_port_dat_w[55:48];
if (soc_ddrphy_bankmodel5_write_port_we[7])
mem_5[soc_ddrphy_bankmodel5_write_port_adr][63:56] <= soc_ddrphy_bankmodel5_write_port_dat_w[63:56];
if (soc_ddrphy_bankmodel5_write_port_we[8])
mem_5[soc_ddrphy_bankmodel5_write_port_adr][71:64] <= soc_ddrphy_bankmodel5_write_port_dat_w[71:64];
if (soc_ddrphy_bankmodel5_write_port_we[9])
mem_5[soc_ddrphy_bankmodel5_write_port_adr][79:72] <= soc_ddrphy_bankmodel5_write_port_dat_w[79:72];
if (soc_ddrphy_bankmodel5_write_port_we[10])
mem_5[soc_ddrphy_bankmodel5_write_port_adr][87:80] <= soc_ddrphy_bankmodel5_write_port_dat_w[87:80];
if (soc_ddrphy_bankmodel5_write_port_we[11])
mem_5[soc_ddrphy_bankmodel5_write_port_adr][95:88] <= soc_ddrphy_bankmodel5_write_port_dat_w[95:88];
if (soc_ddrphy_bankmodel5_write_port_we[12])
mem_5[soc_ddrphy_bankmodel5_write_port_adr][103:96] <= soc_ddrphy_bankmodel5_write_port_dat_w[103:96];
if (soc_ddrphy_bankmodel5_write_port_we[13])
mem_5[soc_ddrphy_bankmodel5_write_port_adr][111:104] <= soc_ddrphy_bankmodel5_write_port_dat_w[111:104];
if (soc_ddrphy_bankmodel5_write_port_we[14])
mem_5[soc_ddrphy_bankmodel5_write_port_adr][119:112] <= soc_ddrphy_bankmodel5_write_port_dat_w[119:112];
if (soc_ddrphy_bankmodel5_write_port_we[15])
mem_5[soc_ddrphy_bankmodel5_write_port_adr][127:120] <= soc_ddrphy_bankmodel5_write_port_dat_w[127:120];
memadr_5 <= soc_ddrphy_bankmodel5_write_port_adr;
end
always @(posedge sys_clk) begin
end
assign soc_ddrphy_bankmodel5_write_port_dat_r = mem_5[memadr_5];
assign soc_ddrphy_bankmodel5_read_port_dat_r = mem_5[soc_ddrphy_bankmodel5_read_port_adr];
reg [127:0] mem_6[0:2097151];
reg [20:0] memadr_6;
always @(posedge sys_clk) begin
if (soc_ddrphy_bankmodel6_write_port_we[0])
mem_6[soc_ddrphy_bankmodel6_write_port_adr][7:0] <= soc_ddrphy_bankmodel6_write_port_dat_w[7:0];
if (soc_ddrphy_bankmodel6_write_port_we[1])
mem_6[soc_ddrphy_bankmodel6_write_port_adr][15:8] <= soc_ddrphy_bankmodel6_write_port_dat_w[15:8];
if (soc_ddrphy_bankmodel6_write_port_we[2])
mem_6[soc_ddrphy_bankmodel6_write_port_adr][23:16] <= soc_ddrphy_bankmodel6_write_port_dat_w[23:16];
if (soc_ddrphy_bankmodel6_write_port_we[3])
mem_6[soc_ddrphy_bankmodel6_write_port_adr][31:24] <= soc_ddrphy_bankmodel6_write_port_dat_w[31:24];
if (soc_ddrphy_bankmodel6_write_port_we[4])
mem_6[soc_ddrphy_bankmodel6_write_port_adr][39:32] <= soc_ddrphy_bankmodel6_write_port_dat_w[39:32];
if (soc_ddrphy_bankmodel6_write_port_we[5])
mem_6[soc_ddrphy_bankmodel6_write_port_adr][47:40] <= soc_ddrphy_bankmodel6_write_port_dat_w[47:40];
if (soc_ddrphy_bankmodel6_write_port_we[6])
mem_6[soc_ddrphy_bankmodel6_write_port_adr][55:48] <= soc_ddrphy_bankmodel6_write_port_dat_w[55:48];
if (soc_ddrphy_bankmodel6_write_port_we[7])
mem_6[soc_ddrphy_bankmodel6_write_port_adr][63:56] <= soc_ddrphy_bankmodel6_write_port_dat_w[63:56];
if (soc_ddrphy_bankmodel6_write_port_we[8])
mem_6[soc_ddrphy_bankmodel6_write_port_adr][71:64] <= soc_ddrphy_bankmodel6_write_port_dat_w[71:64];
if (soc_ddrphy_bankmodel6_write_port_we[9])
mem_6[soc_ddrphy_bankmodel6_write_port_adr][79:72] <= soc_ddrphy_bankmodel6_write_port_dat_w[79:72];
if (soc_ddrphy_bankmodel6_write_port_we[10])
mem_6[soc_ddrphy_bankmodel6_write_port_adr][87:80] <= soc_ddrphy_bankmodel6_write_port_dat_w[87:80];
if (soc_ddrphy_bankmodel6_write_port_we[11])
mem_6[soc_ddrphy_bankmodel6_write_port_adr][95:88] <= soc_ddrphy_bankmodel6_write_port_dat_w[95:88];
if (soc_ddrphy_bankmodel6_write_port_we[12])
mem_6[soc_ddrphy_bankmodel6_write_port_adr][103:96] <= soc_ddrphy_bankmodel6_write_port_dat_w[103:96];
if (soc_ddrphy_bankmodel6_write_port_we[13])
mem_6[soc_ddrphy_bankmodel6_write_port_adr][111:104] <= soc_ddrphy_bankmodel6_write_port_dat_w[111:104];
if (soc_ddrphy_bankmodel6_write_port_we[14])
mem_6[soc_ddrphy_bankmodel6_write_port_adr][119:112] <= soc_ddrphy_bankmodel6_write_port_dat_w[119:112];
if (soc_ddrphy_bankmodel6_write_port_we[15])
mem_6[soc_ddrphy_bankmodel6_write_port_adr][127:120] <= soc_ddrphy_bankmodel6_write_port_dat_w[127:120];
memadr_6 <= soc_ddrphy_bankmodel6_write_port_adr;
end
always @(posedge sys_clk) begin
end
assign soc_ddrphy_bankmodel6_write_port_dat_r = mem_6[memadr_6];
assign soc_ddrphy_bankmodel6_read_port_dat_r = mem_6[soc_ddrphy_bankmodel6_read_port_adr];
reg [127:0] mem_7[0:2097151];
reg [20:0] memadr_7;
always @(posedge sys_clk) begin
if (soc_ddrphy_bankmodel7_write_port_we[0])
mem_7[soc_ddrphy_bankmodel7_write_port_adr][7:0] <= soc_ddrphy_bankmodel7_write_port_dat_w[7:0];
if (soc_ddrphy_bankmodel7_write_port_we[1])
mem_7[soc_ddrphy_bankmodel7_write_port_adr][15:8] <= soc_ddrphy_bankmodel7_write_port_dat_w[15:8];
if (soc_ddrphy_bankmodel7_write_port_we[2])
mem_7[soc_ddrphy_bankmodel7_write_port_adr][23:16] <= soc_ddrphy_bankmodel7_write_port_dat_w[23:16];
if (soc_ddrphy_bankmodel7_write_port_we[3])
mem_7[soc_ddrphy_bankmodel7_write_port_adr][31:24] <= soc_ddrphy_bankmodel7_write_port_dat_w[31:24];
if (soc_ddrphy_bankmodel7_write_port_we[4])
mem_7[soc_ddrphy_bankmodel7_write_port_adr][39:32] <= soc_ddrphy_bankmodel7_write_port_dat_w[39:32];
if (soc_ddrphy_bankmodel7_write_port_we[5])
mem_7[soc_ddrphy_bankmodel7_write_port_adr][47:40] <= soc_ddrphy_bankmodel7_write_port_dat_w[47:40];
if (soc_ddrphy_bankmodel7_write_port_we[6])
mem_7[soc_ddrphy_bankmodel7_write_port_adr][55:48] <= soc_ddrphy_bankmodel7_write_port_dat_w[55:48];
if (soc_ddrphy_bankmodel7_write_port_we[7])
mem_7[soc_ddrphy_bankmodel7_write_port_adr][63:56] <= soc_ddrphy_bankmodel7_write_port_dat_w[63:56];
if (soc_ddrphy_bankmodel7_write_port_we[8])
mem_7[soc_ddrphy_bankmodel7_write_port_adr][71:64] <= soc_ddrphy_bankmodel7_write_port_dat_w[71:64];
if (soc_ddrphy_bankmodel7_write_port_we[9])
mem_7[soc_ddrphy_bankmodel7_write_port_adr][79:72] <= soc_ddrphy_bankmodel7_write_port_dat_w[79:72];
if (soc_ddrphy_bankmodel7_write_port_we[10])
mem_7[soc_ddrphy_bankmodel7_write_port_adr][87:80] <= soc_ddrphy_bankmodel7_write_port_dat_w[87:80];
if (soc_ddrphy_bankmodel7_write_port_we[11])
mem_7[soc_ddrphy_bankmodel7_write_port_adr][95:88] <= soc_ddrphy_bankmodel7_write_port_dat_w[95:88];
if (soc_ddrphy_bankmodel7_write_port_we[12])
mem_7[soc_ddrphy_bankmodel7_write_port_adr][103:96] <= soc_ddrphy_bankmodel7_write_port_dat_w[103:96];
if (soc_ddrphy_bankmodel7_write_port_we[13])
mem_7[soc_ddrphy_bankmodel7_write_port_adr][111:104] <= soc_ddrphy_bankmodel7_write_port_dat_w[111:104];
if (soc_ddrphy_bankmodel7_write_port_we[14])
mem_7[soc_ddrphy_bankmodel7_write_port_adr][119:112] <= soc_ddrphy_bankmodel7_write_port_dat_w[119:112];
if (soc_ddrphy_bankmodel7_write_port_we[15])
mem_7[soc_ddrphy_bankmodel7_write_port_adr][127:120] <= soc_ddrphy_bankmodel7_write_port_dat_w[127:120];
memadr_7 <= soc_ddrphy_bankmodel7_write_port_adr;
end
always @(posedge sys_clk) begin
end
assign soc_ddrphy_bankmodel7_write_port_dat_r = mem_7[memadr_7];
assign soc_ddrphy_bankmodel7_read_port_dat_r = mem_7[soc_ddrphy_bankmodel7_read_port_adr];
reg [23:0] storage[0:15];
reg [23:0] memdat;
always @(posedge sys_clk) begin
if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
memdat <= storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat;
assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_1[0:15];
reg [23:0] memdat_1;
always @(posedge sys_clk) begin
if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
memdat_1 <= storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1;
assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_2[0:15];
reg [23:0] memdat_2;
always @(posedge sys_clk) begin
if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
memdat_2 <= storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2;
assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_3[0:15];
reg [23:0] memdat_3;
always @(posedge sys_clk) begin
if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
memdat_3 <= storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3;
assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_4[0:15];
reg [23:0] memdat_4;
always @(posedge sys_clk) begin
if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
memdat_4 <= storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4;
assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_5[0:15];
reg [23:0] memdat_5;
always @(posedge sys_clk) begin
if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
memdat_5 <= storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5;
assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_6[0:15];
reg [23:0] memdat_6;
always @(posedge sys_clk) begin
if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
memdat_6 <= storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6;
assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_7[0:15];
reg [23:0] memdat_7;
always @(posedge sys_clk) begin
if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
memdat_7 <= storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7;
assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
endmodule