forked from cores/microwatt
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caravel-mp
| Author | SHA1 | Date |
|---|---|---|
Anton Blanchard
|
2083bc3ed0 | 3 years ago |
|
Anton Blanchard
|
ace41e5153 | 3 years ago |
 Anton Blanchard
|
907c833521 | 3 years ago |
|
Anton Blanchard
|
5c40143754 | 3 years ago |
|
Anton Blanchard
|
d0ced7441f | 3 years ago |
|
Anton Blanchard
|
606359cce3 | 3 years ago |
|
Anton Blanchard
|
49b332e17f | 3 years ago |
|
Anton Blanchard
|
d5e3be80fe | 3 years ago |
|
Anton Blanchard
|
d504ae63f6 | 3 years ago |
|
Anton Blanchard
|
15bb4aa90a | 3 years ago |
|
Anton Blanchard
|
c2577b5446 | 3 years ago |
|
Anton Blanchard
|
5249d633cf | 3 years ago |
|
Anton Blanchard
|
8ecb30da05 | 3 years ago |
|
Anton Blanchard
|
747c96b100 | 3 years ago |
|
Anton Blanchard
|
faab169307 | 3 years ago |
@ -0,0 +1,24 @@
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module Microwatt_FP_DFFRFile (
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`ifdef USE_POWER_PINS
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inout VPWR,
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inout VGND,
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`endif
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input [6:0] R1, R2, R3, RW,
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input [63:0] DW,
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output [63:0] D1, D2, D3,
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input CLK,
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input WE
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);
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reg [63:0] registers[0:95];
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assign D1 = registers[R1];
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assign D2 = registers[R2];
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assign D3 = registers[R3];
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always @(posedge CLK) begin
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if (WE)
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registers[RW] <= DW;
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end
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endmodule
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@ -0,0 +1,40 @@
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module RAM32_1RW1R #(
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parameter BITS=5
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) (
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`ifdef USE_POWER_PINS
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inout VPWR,
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inout VGND,
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`endif
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input CLK,
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input EN0,
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input [BITS-1:0] A0,
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input [7:0] WE0,
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input [63:0] Di0,
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output reg [63:0] Do0,
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input EN1,
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input [BITS-1:0] A1,
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output reg [63:0] Do1
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);
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reg [63:0] RAM[2**BITS-1:0];
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always @(posedge CLK) begin
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if (EN1)
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Do1 <= RAM[A1];
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end
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generate
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genvar i;
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for (i=0; i<8; i=i+1) begin: BYTE
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always @(posedge CLK) begin
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if (EN0) begin
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if (WE0[i])
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RAM[A0][i*8+7:i*8] <= Di0[i*8+7:i*8];
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end
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end
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end
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endgenerate
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endmodule
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@ -0,0 +1,42 @@
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module RAM512 #(
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parameter BITS=9,
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parameter FILENAME="firmware.hex"
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) (
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`ifdef USE_POWER_PINS
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inout VPWR,
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inout VGND,
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`endif
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input CLK,
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input [7:0] WE0,
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input EN0,
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input [63:0] Di0,
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output reg [63:0] Do0,
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input [BITS-1:0] A0
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);
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reg [63:0] RAM[2**BITS-1:0];
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always @(posedge CLK) begin
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if (EN0)
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Do0 <= RAM[A0];
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else
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Do0 <= 64'b0;
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end
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generate
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genvar i;
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for (i=0; i<8; i=i+1) begin: BYTE
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always @(posedge CLK) begin
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if (EN0) begin
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if (WE0[i])
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RAM[A0][i*8+7:i*8] <= Di0[i*8+7:i*8];
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end
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end
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end
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endgenerate
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initial begin
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$readmemh(FILENAME, RAM);
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end
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endmodule
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@ -0,0 +1,22 @@
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module multiply_add_64x64
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#(
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parameter BITS=64
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) (
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`ifdef USE_POWER_PINS
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inout VPWR,
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inout VGND,
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`endif
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input clk,
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input [BITS-1:0] a,
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input [BITS-1:0] b,
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input [BITS*2-1:0] c,
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output [BITS*2-1:0] o
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);
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reg [BITS*2-1:0] o_tmp;
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always @(posedge clk) begin
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o_tmp = (a * b) + c;
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end
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assign o = o_tmp;
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endmodule
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@ -0,0 +1,99 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity cache_ram is
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generic(
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ROW_BITS : integer := 5;
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WIDTH : integer := 64;
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TRACE : boolean := false;
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ADD_BUF : boolean := false
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);
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port(
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clk : in std_logic;
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rd_en : in std_logic;
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rd_addr : in std_logic_vector(ROW_BITS - 1 downto 0);
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rd_data : out std_logic_vector(WIDTH - 1 downto 0);
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wr_sel : in std_logic_vector(WIDTH/8 - 1 downto 0);
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wr_addr : in std_logic_vector(ROW_BITS - 1 downto 0);
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wr_data : in std_logic_vector(WIDTH - 1 downto 0)
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);
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end cache_ram;
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architecture rtl of cache_ram is
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component RAM32_1RW1R port(
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CLK : in std_logic;
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EN0 : in std_logic;
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A0 : in std_logic_vector(4 downto 0);
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WE0 : in std_logic_vector(7 downto 0);
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Di0 : in std_logic_vector(63 downto 0);
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Do0 : out std_logic_vector(63 downto 0);
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EN1 : in std_logic;
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A1 : in std_logic_vector(4 downto 0);
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Do1 : out std_logic_vector(63 downto 0)
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);
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end component;
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signal wr_enable: std_logic;
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signal rd_data0_tmp : std_logic_vector(WIDTH - 1 downto 0);
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signal rd_data0_saved : std_logic_vector(WIDTH - 1 downto 0);
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signal rd_data0 : std_logic_vector(WIDTH - 1 downto 0);
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signal rd_en_prev: std_ulogic;
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begin
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assert (ROW_BITS = 5) report "ROW_BITS must be 5" severity FAILURE;
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assert (WIDTH = 64) report "Must be 64 bit" severity FAILURE;
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assert (TRACE = false) report "Trace not supported" severity FAILURE;
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wr_enable <= or(wr_sel);
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cache_ram_0 : RAM32_1RW1R
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port map (
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CLK => clk,
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EN0 => wr_enable,
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A0 => wr_addr,
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WE0 => wr_sel,
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Di0 => wr_data,
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Do0 => open,
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EN1 => rd_en,
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A1 => rd_addr,
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Do1 => rd_data0_tmp
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);
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-- The caches rely on cache_ram latching the last read. Handle it here
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-- for now.
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process(clk)
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begin
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if rising_edge(clk) then
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rd_en_prev <= rd_en;
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if rd_en_prev = '1' then
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rd_data0_saved <= rd_data0_tmp;
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end if;
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end if;
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end process;
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rd_data0 <= rd_data0_tmp when rd_en_prev = '1' else rd_data0_saved;
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buf: if ADD_BUF generate
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begin
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process(clk)
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begin
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if rising_edge(clk) then
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rd_data <= rd_data0;
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end if;
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end process;
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end generate;
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nobuf: if not ADD_BUF generate
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begin
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rd_data <= rd_data0;
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end generate;
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end architecture rtl;
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@ -0,0 +1,63 @@
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library ieee;
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use ieee.std_logic_1164.all;
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library work;
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entity main_bram is
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generic(
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WIDTH : natural := 64;
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HEIGHT_BITS : natural;
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MEMORY_SIZE : natural;
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RAM_INIT_FILE : string
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);
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port(
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clk : in std_logic;
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addr : in std_logic_vector(HEIGHT_BITS - 1 downto 0) ;
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din : in std_logic_vector(WIDTH-1 downto 0);
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dout : out std_logic_vector(WIDTH-1 downto 0);
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sel : in std_logic_vector((WIDTH/8)-1 downto 0);
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re : in std_ulogic;
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we : in std_ulogic
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);
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end entity main_bram;
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architecture behaviour of main_bram is
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component RAM512 port (
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CLK : in std_ulogic;
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WE0 : in std_ulogic_vector(7 downto 0);
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EN0 : in std_ulogic;
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Di0 : in std_ulogic_vector(63 downto 0);
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Do0 : out std_ulogic_vector(63 downto 0);
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A0 : in std_ulogic_vector(8 downto 0)
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);
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end component;
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signal sel_qual: std_ulogic_vector((WIDTH/8)-1 downto 0);
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signal obuf : std_logic_vector(WIDTH-1 downto 0);
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begin
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assert (WIDTH = 64) report "Must be 64 bit" severity FAILURE;
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||||
-- Do we have a log2 round up issue here?
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assert (HEIGHT_BITS = 9) report "HEIGHT_BITS must be 10" severity FAILURE;
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assert (MEMORY_SIZE = 4096) report "MEMORY_SIZE must be 4096" severity FAILURE;
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sel_qual <= sel when we = '1' else (others => '0');
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memory_0 : RAM512
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port map (
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CLK => clk,
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WE0 => sel_qual(7 downto 0),
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EN0 => re or we,
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Di0 => din(63 downto 0),
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Do0 => obuf(63 downto 0),
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A0 => addr(8 downto 0)
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);
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||||
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-- The wishbone BRAM wrapper assumes a 1 cycle delay
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memory_read_buffer: process(clk)
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begin
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if rising_edge(clk) then
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dout <= obuf;
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end if;
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end process;
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end architecture behaviour;
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@ -0,0 +1,83 @@
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#include <stdlib.h>
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#include "Vtoplevel.h"
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#include "verilated.h"
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#include "verilated_vcd_c.h"
|
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/*
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* Current simulation time
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* This is a 64-bit integer to reduce wrap over issues and
|
||||
* allow modulus. You can also use a double, if you wish.
|
||||
*/
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vluint64_t main_time = 0;
|
||||
|
||||
/*
|
||||
* Called by $time in Verilog
|
||||
* converts to double, to match
|
||||
* what SystemC does
|
||||
*/
|
||||
double sc_time_stamp(void)
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{
|
||||
return main_time;
|
||||
}
|
||||
|
||||
#if VM_TRACE
|
||||
VerilatedVcdC *tfp;
|
||||
#endif
|
||||
|
||||
void tick(Vtoplevel *top)
|
||||
{
|
||||
top->ext_clk = 1;
|
||||
top->eval();
|
||||
#if VM_TRACE
|
||||
if (tfp)
|
||||
tfp->dump((double) main_time);
|
||||
#endif
|
||||
main_time++;
|
||||
|
||||
top->ext_clk = 0;
|
||||
top->eval();
|
||||
#if VM_TRACE
|
||||
if (tfp)
|
||||
tfp->dump((double) main_time);
|
||||
#endif
|
||||
main_time++;
|
||||
}
|
||||
|
||||
void uart_tx(unsigned char tx);
|
||||
unsigned char uart_rx(void);
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
Verilated::commandArgs(argc, argv);
|
||||
|
||||
// init top verilog instance
|
||||
Vtoplevel* top = new Vtoplevel;
|
||||
|
||||
#if VM_TRACE
|
||||
// init trace dump
|
||||
Verilated::traceEverOn(true);
|
||||
tfp = new VerilatedVcdC;
|
||||
top->trace(tfp, 99);
|
||||
tfp->open("microwatt-verilator.vcd");
|
||||
#endif
|
||||
|
||||
// Reset
|
||||
top->ext_rst = 0;
|
||||
for (unsigned long i = 0; i < 5; i++)
|
||||
tick(top);
|
||||
top->ext_rst = 1;
|
||||
|
||||
while(!Verilated::gotFinish()) {
|
||||
tick(top);
|
||||
|
||||
uart_tx(top->uart0_txd);
|
||||
top->uart0_rxd = uart_rx();
|
||||
}
|
||||
|
||||
#if VM_TRACE
|
||||
tfp->close();
|
||||
delete tfp;
|
||||
#endif
|
||||
|
||||
delete top;
|
||||
}
|
||||
@ -0,0 +1,127 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.common.all;
|
||||
|
||||
entity multiply is
|
||||
generic (
|
||||
PIPELINE_DEPTH : natural := 2
|
||||
);
|
||||
port (
|
||||
clk : in std_logic;
|
||||
|
||||
m_in : in MultiplyInputType;
|
||||
m_out : out MultiplyOutputType
|
||||
);
|
||||
end entity multiply;
|
||||
|
||||
architecture behaviour of multiply is
|
||||
signal m: MultiplyInputType := MultiplyInputInit;
|
||||
|
||||
type multiply_pipeline_stage is record
|
||||
valid : std_ulogic;
|
||||
is_32bit : std_ulogic;
|
||||
not_res : std_ulogic;
|
||||
end record;
|
||||
constant MultiplyPipelineStageInit : multiply_pipeline_stage := (valid => '0',
|
||||
is_32bit => '0',
|
||||
not_res => '0');
|
||||
|
||||
type multiply_pipeline_type is array(0 to PIPELINE_DEPTH-1) of multiply_pipeline_stage;
|
||||
constant MultiplyPipelineInit : multiply_pipeline_type := (others => MultiplyPipelineStageInit);
|
||||
|
||||
type reg_type is record
|
||||
multiply_pipeline : multiply_pipeline_type;
|
||||
end record;
|
||||
|
||||
signal r, rin : reg_type := (multiply_pipeline => MultiplyPipelineInit);
|
||||
signal overflow : std_ulogic;
|
||||
signal ovf_in : std_ulogic;
|
||||
|
||||
signal mult_out : std_logic_vector(127 downto 0);
|
||||
|
||||
component multiply_add_64x64 port(
|
||||
clk : in std_logic;
|
||||
a : in std_logic_vector(63 downto 0);
|
||||
b : in std_logic_vector(63 downto 0);
|
||||
c : in std_logic_vector(127 downto 0);
|
||||
o : out std_logic_vector(127 downto 0)
|
||||
);
|
||||
end component;
|
||||
begin
|
||||
multiply_0: process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
m <= m_in;
|
||||
r <= rin;
|
||||
overflow <= ovf_in;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
multiplier : multiply_add_64x64
|
||||
port map (
|
||||
clk => clk,
|
||||
a => m.data1,
|
||||
b => m.data2,
|
||||
c => m.addend,
|
||||
o => mult_out
|
||||
);
|
||||
|
||||
multiply_1: process(all)
|
||||
variable v : reg_type;
|
||||
variable d : std_ulogic_vector(127 downto 0);
|
||||
variable d2 : std_ulogic_vector(63 downto 0);
|
||||
variable ov : std_ulogic;
|
||||
begin
|
||||
v := r;
|
||||
v.multiply_pipeline(0).valid := m.valid;
|
||||
v.multiply_pipeline(0).is_32bit := m.is_32bit;
|
||||
v.multiply_pipeline(0).not_res := m.not_result;
|
||||
|
||||
loop_0: for i in 1 to PIPELINE_DEPTH-1 loop
|
||||
v.multiply_pipeline(i) := r.multiply_pipeline(i-1);
|
||||
end loop;
|
||||
|
||||
if v.multiply_pipeline(PIPELINE_DEPTH-1).not_res = '1' then
|
||||
d := not mult_out;
|
||||
else
|
||||
d := mult_out;
|
||||
end if;
|
||||
|
||||
ov := '0';
|
||||
if v.multiply_pipeline(PIPELINE_DEPTH-1).is_32bit = '1' then
|
||||
ov := (or d(63 downto 31)) and not (and d(63 downto 31));
|
||||
else
|
||||
ov := (or d(127 downto 63)) and not (and d(127 downto 63));
|
||||
end if;
|
||||
ovf_in <= ov;
|
||||
|
||||
m_out.result <= d;
|
||||
m_out.overflow <= overflow;
|
||||
m_out.valid <= v.multiply_pipeline(PIPELINE_DEPTH-1).valid;
|
||||
|
||||
rin <= v;
|
||||
end process;
|
||||
end architecture behaviour;
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity short_multiply is
|
||||
port (
|
||||
clk : in std_ulogic;
|
||||
|
||||
a_in : in std_ulogic_vector(15 downto 0);
|
||||
b_in : in std_ulogic_vector(15 downto 0);
|
||||
m_out : out std_ulogic_vector(31 downto 0)
|
||||
);
|
||||
end entity short_multiply;
|
||||
|
||||
architecture behaviour of short_multiply is
|
||||
begin
|
||||
m_out <= std_ulogic_vector(signed(a_in) * signed(b_in));
|
||||
end architecture behaviour;
|
||||
@ -0,0 +1,103 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.common.all;
|
||||
|
||||
entity register_file is
|
||||
generic (
|
||||
SIM : boolean := false;
|
||||
HAS_FPU : boolean := true;
|
||||
LOG_LENGTH : natural := 0
|
||||
);
|
||||
port(
|
||||
clk : in std_logic;
|
||||
|
||||
d_in : in Decode2ToRegisterFileType;
|
||||
d_out : out RegisterFileToDecode2Type;
|
||||
|
||||
w_in : in WritebackToRegisterFileType;
|
||||
|
||||
dbg_gpr_req : in std_ulogic;
|
||||
dbg_gpr_ack : out std_ulogic;
|
||||
dbg_gpr_addr : in gspr_index_t;
|
||||
dbg_gpr_data : out std_ulogic_vector(63 downto 0);
|
||||
|
||||
sim_dump : in std_ulogic;
|
||||
sim_dump_done : out std_ulogic;
|
||||
|
||||
log_out : out std_ulogic_vector(71 downto 0)
|
||||
);
|
||||
end entity register_file;
|
||||
|
||||
architecture behaviour of register_file is
|
||||
component Microwatt_FP_DFFRFile port (
|
||||
CLK : in std_ulogic;
|
||||
|
||||
R1 : in std_ulogic_vector(6 downto 0);
|
||||
R2 : in std_ulogic_vector(6 downto 0);
|
||||
R3 : in std_ulogic_vector(6 downto 0);
|
||||
|
||||
D1 : out std_ulogic_vector(63 downto 0);
|
||||
D2 : out std_ulogic_vector(63 downto 0);
|
||||
D3 : out std_ulogic_vector(63 downto 0);
|
||||
|
||||
WE : in std_ulogic;
|
||||
RW : in std_ulogic_vector(6 downto 0);
|
||||
DW : in std_ulogic_vector(63 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal d1: std_ulogic_vector(63 downto 0);
|
||||
signal d2: std_ulogic_vector(63 downto 0);
|
||||
signal d3: std_ulogic_vector(63 downto 0);
|
||||
begin
|
||||
|
||||
register_file_0 : Microwatt_FP_DFFRFile
|
||||
port map (
|
||||
CLK => clk,
|
||||
|
||||
R1 => d_in.read1_reg,
|
||||
R2 => d_in.read2_reg,
|
||||
R3 => d_in.read3_reg,
|
||||
|
||||
D1 => d1,
|
||||
D2 => d2,
|
||||
D3 => d3,
|
||||
|
||||
WE => w_in.write_enable,
|
||||
RW => w_in.write_reg,
|
||||
DW => w_in.write_data
|
||||
);
|
||||
|
||||
x_state_check: process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if w_in.write_enable = '1' then
|
||||
assert not(is_x(w_in.write_data)) and not(is_x(w_in.write_reg)) severity failure;
|
||||
end if;
|
||||
end if;
|
||||
end process x_state_check;
|
||||
|
||||
-- Forward any written data
|
||||
register_read_0: process(all)
|
||||
begin
|
||||
d_out.read1_data <= d1;
|
||||
d_out.read2_data <= d2;
|
||||
d_out.read3_data <= d3;
|
||||
|
||||
if w_in.write_enable = '1' then
|
||||
if d_in.read1_reg = w_in.write_reg then
|
||||
d_out.read1_data <= w_in.write_data;
|
||||
end if;
|
||||
if d_in.read2_reg = w_in.write_reg then
|
||||
d_out.read2_data <= w_in.write_data;
|
||||
end if;
|
||||
if d_in.read3_reg = w_in.write_reg then
|
||||
d_out.read3_data <= w_in.write_data;
|
||||
end if;
|
||||
end if;
|
||||
end process register_read_0;
|
||||
|
||||
end architecture behaviour;
|
||||
@ -0,0 +1,285 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.wishbone_types.all;
|
||||
|
||||
entity toplevel is
|
||||
generic (
|
||||
MEMORY_SIZE : integer := 8192;
|
||||
RAM_INIT_FILE : string := "firmware.hex";
|
||||
RESET_LOW : boolean := true;
|
||||
CLK_INPUT : positive := 100000000;
|
||||
CLK_FREQUENCY : positive := 100000000;
|
||||
HAS_FPU : boolean := true;
|
||||
HAS_BTC : boolean := false;
|
||||
NO_BRAM : boolean := false;
|
||||
DISABLE_FLATTEN_CORE : boolean := false;
|
||||
ALT_RESET_ADDRESS : std_logic_vector(63 downto 0) := (27 downto 0 => '0', others => '1');
|
||||
SPI_FLASH_OFFSET : integer := 0;
|
||||
SPI_FLASH_DEF_CKDV : natural := 4;
|
||||
SPI_FLASH_DEF_QUAD : boolean := false;
|
||||
SPI_BOOT_CLOCKS : boolean := false;
|
||||
LOG_LENGTH : natural := 0;
|
||||
UART_IS_16550 : boolean := true;
|
||||
HAS_UART1 : boolean := false;
|
||||
HAS_JTAG : boolean := true;
|
||||
ICACHE_NUM_LINES : natural := 4;
|
||||
ICACHE_NUM_WAYS : natural := 1;
|
||||
ICACHE_TLB_SIZE : natural := 4;
|
||||
DCACHE_NUM_LINES : natural := 4;
|
||||
DCACHE_NUM_WAYS : natural := 1;
|
||||
DCACHE_TLB_SET_SIZE : natural := 2;
|
||||
DCACHE_TLB_NUM_WAYS : natural := 2;
|
||||
HAS_GPIO : boolean := true;
|
||||
NGPIO : natural := 32
|
||||
);
|
||||
port(
|
||||
ext_clk : in std_ulogic;
|
||||
ext_rst : in std_ulogic;
|
||||
|
||||
-- UART0 signals:
|
||||
uart0_txd : out std_ulogic;
|
||||
uart0_rxd : in std_ulogic;
|
||||
|
||||
-- SPI
|
||||
spi_flash_cs_n : out std_ulogic;
|
||||
spi_flash_clk : out std_ulogic;
|
||||
spi_flash_sdat_i : in std_ulogic_vector(3 downto 0);
|
||||
spi_flash_sdat_o : out std_ulogic_vector(3 downto 0);
|
||||
spi_flash_sdat_oe : out std_ulogic_vector(3 downto 0);
|
||||
|
||||
-- GPIO
|
||||
gpio_in : in std_ulogic_vector(NGPIO - 1 downto 0);
|
||||
gpio_out : out std_ulogic_vector(NGPIO - 1 downto 0);
|
||||
gpio_dir : out std_ulogic_vector(NGPIO - 1 downto 0);
|
||||
|
||||
-- JTAG signals:
|
||||
jtag_tck : in std_ulogic;
|
||||
jtag_tdi : in std_ulogic;
|
||||
jtag_tms : in std_ulogic;
|
||||
jtag_trst : in std_ulogic;
|
||||
jtag_tdo : out std_ulogic;
|
||||
|
||||
-- simplebus
|
||||
simplebus_clk : out std_logic;
|
||||
simplebus_bus_out : out std_logic_vector(7 downto 0);
|
||||
simplebus_parity_out : out std_logic;
|
||||
simplebus_bus_in : in std_logic_vector(7 downto 0);
|
||||
simplebus_parity_in : in std_logic;
|
||||
simplebus_enabled : out std_logic;
|
||||
simplebus_irq : in std_ulogic;
|
||||
|
||||
-- Add an I/O pin to select fetching from flash on reset
|
||||
alt_reset : in std_ulogic
|
||||
);
|
||||
end entity toplevel;
|
||||
|
||||
architecture behaviour of toplevel is
|
||||
-- reset signals
|
||||
signal system_rst : std_ulogic;
|
||||
|
||||
-- simplebus wishbone connection
|
||||
signal wb_simplebus_out : wishbone_master_out;
|
||||
signal wb_simplebus_in : wishbone_slave_out;
|
||||
|
||||
-- simplebus split out wishbone
|
||||
signal wb_simplebus_adr : wishbone_addr_type;
|
||||
signal wb_simplebus_dat_o : wishbone_data_type;
|
||||
signal wb_simplebus_cyc : std_ulogic;
|
||||
signal wb_simplebus_stb : std_ulogic;
|
||||
signal wb_simplebus_sel : wishbone_sel_type;
|
||||
signal wb_simplebus_we : std_ulogic;
|
||||
signal wb_simplebus_dat_i : wishbone_data_type;
|
||||
signal wb_simplebus_ack : std_ulogic;
|
||||
signal wb_simplebus_stall : std_ulogic;
|
||||
|
||||
-- simplebus I/O wishbone
|
||||
signal wb_ext_io_in : wb_io_master_out;
|
||||
signal wb_ext_io_out : wb_io_slave_out;
|
||||
signal wb_ext_is_simplebus : std_ulogic;
|
||||
|
||||
-- simplebus I/O split out wishbone
|
||||
signal wb_simplebus_ctrl_adr : std_ulogic_vector(29 downto 0);
|
||||
signal wb_simplebus_ctrl_dat_o : std_ulogic_vector(31 downto 0);
|
||||
signal wb_simplebus_ctrl_cyc : std_ulogic;
|
||||
signal wb_simplebus_ctrl_stb : std_ulogic;
|
||||
signal wb_simplebus_ctrl_sel : std_ulogic_vector(3 downto 0);
|
||||
signal wb_simplebus_ctrl_we : std_ulogic;
|
||||
signal wb_simplebus_ctrl_dat_i : std_ulogic_vector(31 downto 0);
|
||||
signal wb_simplebus_ctrl_ack : std_ulogic;
|
||||
signal wb_simplebus_ctrl_stall : std_ulogic;
|
||||
|
||||
component simplebus_host port(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
|
||||
wb_cyc : in std_logic;
|
||||
wb_stb : in std_logic;
|
||||
wb_we : in std_logic;
|
||||
wb_adr : in wishbone_addr_type;
|
||||
wb_dat_w : in wishbone_data_type;
|
||||
wb_sel : in std_logic_vector;
|
||||
wb_ack : out std_logic;
|
||||
wb_stall : out std_logic;
|
||||
wb_dat_r : out wishbone_data_type;
|
||||
|
||||
wb_ctrl_cyc : in std_logic;
|
||||
wb_ctrl_stb : in std_logic;
|
||||
wb_ctrl_we : in std_logic;
|
||||
wb_ctrl_adr : in std_logic_vector(29 downto 0);
|
||||
wb_ctrl_dat_w : in std_logic_vector(31 downto 0);
|
||||
wb_ctrl_sel : in std_logic_vector(3 downto 0);
|
||||
wb_ctrl_ack : out std_logic;
|
||||
wb_ctrl_stall : out std_logic;
|
||||
wb_ctrl_dat_r : out std_logic_vector(31 downto 0);
|
||||
|
||||
clk_out : out std_logic;
|
||||
bus_out : out std_logic_vector(7 downto 0);
|
||||
parity_out : out std_logic;
|
||||
bus_in : in std_logic_vector(7 downto 0);
|
||||
parity_in : in std_logic;
|
||||
enabled : out std_logic
|
||||
);
|
||||
end component simplebus_host;
|
||||
|
||||
begin
|
||||
|
||||
system_rst <= not ext_rst when RESET_LOW else ext_rst;
|
||||
|
||||
-- Main SoC
|
||||
soc0: entity work.soc
|
||||
generic map(
|
||||
MEMORY_SIZE => MEMORY_SIZE,
|
||||
RAM_INIT_FILE => RAM_INIT_FILE,
|
||||
SIM => false,
|
||||
CLK_FREQ => CLK_FREQUENCY,
|
||||
HAS_FPU => HAS_FPU,
|
||||
HAS_BTC => HAS_BTC,
|
||||
HAS_DRAM => true,
|
||||
DRAM_SIZE => 0,
|
||||
DRAM_INIT_SIZE => 0,
|
||||
DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
|
||||
ALT_RESET_ADDRESS => ALT_RESET_ADDRESS,
|
||||
HAS_SPI_FLASH => true,
|
||||
SPI_FLASH_DLINES => 4,
|
||||
SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
|
||||
SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV,
|
||||
SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD,
|
||||
SPI_BOOT_CLOCKS => SPI_BOOT_CLOCKS,
|
||||
LOG_LENGTH => LOG_LENGTH,
|
||||
UART0_IS_16550 => UART_IS_16550,
|
||||
HAS_UART1 => HAS_UART1,
|
||||
HAS_GPIO => HAS_GPIO,
|
||||
NGPIO => NGPIO,
|
||||
HAS_JTAG => HAS_JTAG,
|
||||
ICACHE_NUM_LINES => ICACHE_NUM_LINES,
|
||||
ICACHE_NUM_WAYS => ICACHE_NUM_WAYS,
|
||||
ICACHE_TLB_SIZE => ICACHE_TLB_SIZE,
|
||||
DCACHE_NUM_LINES => DCACHE_NUM_LINES,
|
||||
DCACHE_NUM_WAYS => DCACHE_NUM_WAYS,
|
||||
DCACHE_TLB_SET_SIZE => DCACHE_TLB_SET_SIZE,
|
||||
DCACHE_TLB_NUM_WAYS => DCACHE_TLB_NUM_WAYS
|
||||
)
|
||||
port map (
|
||||
-- System signals
|
||||
system_clk => ext_clk,
|
||||
rst => system_rst,
|
||||
|
||||
-- UART signals
|
||||
uart0_txd => uart0_txd,
|
||||
uart0_rxd => uart0_rxd,
|
||||
|
||||
-- SPI signals
|
||||
spi_flash_sck => spi_flash_clk,
|
||||
spi_flash_cs_n => spi_flash_cs_n,
|
||||
spi_flash_sdat_o => spi_flash_sdat_o,
|
||||
spi_flash_sdat_oe => spi_flash_sdat_oe,
|
||||
spi_flash_sdat_i => spi_flash_sdat_i,
|
||||
|
||||
-- GPIO signals
|
||||
gpio_in => gpio_in,
|
||||
gpio_out => gpio_out,
|
||||
gpio_dir => gpio_dir,
|
||||
|
||||
-- JTAG signals
|
||||
jtag_tck => jtag_tck,
|
||||
jtag_tdi => jtag_tdi,
|
||||
jtag_tms => jtag_tms,
|
||||
jtag_trst => jtag_trst,
|
||||
jtag_tdo => jtag_tdo,
|
||||
|
||||
-- simplebus 64-bit wishbone
|
||||
wb_dram_in => wb_simplebus_out,
|
||||
wb_dram_out => wb_simplebus_in,
|
||||
|
||||
-- simplebus 32-bit external IO wishbone
|
||||
wb_ext_io_in => wb_ext_io_in,
|
||||
wb_ext_io_out => wb_ext_io_out,
|
||||
wb_ext_is_dram_csr => wb_ext_is_simplebus,
|
||||
|
||||
ext_irq_eth => simplebus_irq,
|
||||
|
||||
-- Reset PC to flash offset 0 (ie 0xf000000)
|
||||
alt_reset => alt_reset
|
||||
);
|
||||
|
||||
-- simplebus wishbone
|
||||
wb_simplebus_adr <= wb_simplebus_out.adr;
|
||||
wb_simplebus_dat_o <= wb_simplebus_out.dat;
|
||||
wb_simplebus_cyc <= wb_simplebus_out.cyc;
|
||||
wb_simplebus_stb <= wb_simplebus_out.stb;
|
||||
wb_simplebus_sel <= wb_simplebus_out.sel;
|
||||
wb_simplebus_we <= wb_simplebus_out.we;
|
||||
|
||||
wb_simplebus_in.dat <= wb_simplebus_dat_i;
|
||||
wb_simplebus_in.ack <= wb_simplebus_ack;
|
||||
wb_simplebus_in.stall <= wb_simplebus_stall;
|
||||
|
||||
-- simplebus I/O wishbone
|
||||
wb_simplebus_ctrl_adr <= wb_ext_io_in.adr;
|
||||
wb_simplebus_ctrl_dat_o <= wb_ext_io_in.dat;
|
||||
wb_simplebus_ctrl_cyc <= wb_ext_io_in.cyc and wb_ext_is_simplebus;
|
||||
wb_simplebus_ctrl_stb <= wb_ext_io_in.stb and wb_ext_is_simplebus;
|
||||
wb_simplebus_ctrl_sel <= wb_ext_io_in.sel;
|
||||
wb_simplebus_ctrl_we <= wb_ext_io_in.we;
|
||||
|
||||
wb_ext_io_out.dat <= wb_simplebus_ctrl_dat_i;
|
||||
wb_ext_io_out.ack <= wb_simplebus_ctrl_ack;
|
||||
wb_ext_io_out.stall <= wb_simplebus_ctrl_stall;
|
||||
|
||||
simplebus_0: simplebus_host
|
||||
port map(
|
||||
clk => ext_clk,
|
||||
rst => system_rst,
|
||||
|
||||
wb_cyc => wb_simplebus_cyc,
|
||||
wb_stb => wb_simplebus_stb,
|
||||
wb_we => wb_simplebus_we,
|
||||
wb_adr => wb_simplebus_adr,
|
||||
wb_dat_w => wb_simplebus_dat_o,
|
||||
wb_sel => wb_simplebus_sel,
|
||||
wb_ack => wb_simplebus_ack,
|
||||
wb_stall => wb_simplebus_stall,
|
||||
wb_dat_r => wb_simplebus_dat_i,
|
||||
|
||||
wb_ctrl_cyc => wb_simplebus_ctrl_cyc,
|
||||
wb_ctrl_stb => wb_simplebus_ctrl_stb,
|
||||
wb_ctrl_we => wb_simplebus_ctrl_we,
|
||||
wb_ctrl_adr => wb_simplebus_ctrl_adr,
|
||||
wb_ctrl_dat_w => wb_simplebus_ctrl_dat_o,
|
||||
wb_ctrl_sel => wb_simplebus_ctrl_sel,
|
||||
wb_ctrl_ack => wb_simplebus_ctrl_ack,
|
||||
wb_ctrl_stall => wb_simplebus_ctrl_stall,
|
||||
wb_ctrl_dat_r => wb_simplebus_ctrl_dat_i,
|
||||
|
||||
clk_out => simplebus_clk,
|
||||
bus_out => simplebus_bus_out,
|
||||
parity_out => simplebus_parity_out,
|
||||
bus_in => simplebus_bus_in,
|
||||
parity_in => simplebus_parity_in,
|
||||
enabled => simplebus_enabled
|
||||
);
|
||||
|
||||
end architecture behaviour;
|
||||
@ -0,0 +1,72 @@
|
||||
#!/usr/bin/python
|
||||
|
||||
import argparse
|
||||
import re
|
||||
|
||||
module_regex = r'[a-zA-Z0-9_:\.\\]+'
|
||||
|
||||
# match:
|
||||
# module dcache(clk, rst, d_in, m_in, wishbone_in, d_out, m_out, stall_out, wishbone_out);
|
||||
# A bit of a hack - ignore anything contining a '`', and assume that means we've already
|
||||
# processed this module in a previous run. This helps when having to run this script
|
||||
# multiple times for different power names.
|
||||
multiline_module_re = re.compile(r'module\s+(' + module_regex + r')\(([^`]*?)\);', re.DOTALL)
|
||||
module_re = re.compile(r'module\s+(' + module_regex + r')\((.*?)\);')
|
||||
|
||||
# match:
|
||||
# dcache_64_2_2_2_2_12_0 dcache_0 (
|
||||
hookup_re = re.compile(r'\s+(' + module_regex + r') ' + module_regex + r'\s+\(')
|
||||
|
||||
header1 = """\
|
||||
`ifdef USE_POWER_PINS
|
||||
{power}, {ground},
|
||||
`endif\
|
||||
"""
|
||||
|
||||
header2 = """\
|
||||
`ifdef USE_POWER_PINS
|
||||
inout {power};
|
||||
inout {ground};
|
||||
`endif\
|
||||
"""
|
||||
|
||||
header3 = """\
|
||||
`ifdef USE_POWER_PINS
|
||||
.{power}({parent_power}),
|
||||
.{ground}({parent_ground}),
|
||||
`endif\
|
||||
"""
|
||||
|
||||
parser = argparse.ArgumentParser(description='Insert power and ground into verilog modules')
|
||||
parser.add_argument('--power', default='VPWR', help='POWER net name (default VPWR)')
|
||||
parser.add_argument('--ground', default='VGND', help='POWER net name (default VGND)')
|
||||
parser.add_argument('--parent-power', default='VPWR', help='POWER net name of parent module (default VPWR)')
|
||||
parser.add_argument('--parent-ground', default='VGND', help='POWER net name of parent module (default VGND)')
|
||||
parser.add_argument('--verilog', required=True, help='Verilog file to modify')
|
||||
parser.add_argument('--module', required=True, action='append', help='Module to replace (can be specified multiple times')
|
||||
|
||||
args = parser.parse_args()
|
||||
|
||||
with open(args.verilog, 'r') as f:
|
||||
d = f.read()
|
||||
# Remove newlines from module definitions, yosys started doing this as of
|
||||
# commit ff8e999a7112 ("Split module ports, 20 per line")
|
||||
fixed = multiline_module_re.sub(lambda m: m.group(0).replace("\n", ""), d)
|
||||
|
||||
for line in fixed.splitlines():
|
||||
m = module_re.match(line)
|
||||
m2 = hookup_re.match(line)
|
||||
if m and m.group(1) in args.module:
|
||||
module_name = m.group(1)
|
||||
module_args = m.group(2)
|
||||
print('module %s(' % (module_name))
|
||||
print("")
|
||||
print(header1.format(power=args.power, ground=args.ground))
|
||||
print(' %s);' % module_args)
|
||||
print(header2.format(power=args.power, ground=args.ground))
|
||||
elif m2 and m2.group(1) in args.module:
|
||||
print(line)
|
||||
print(header3.format(parent_power=args.parent_power, parent_ground=args.parent_ground, power=args.power, ground=args.ground))
|
||||
else:
|
||||
print(line)
|
||||
|
||||
@ -0,0 +1,37 @@
|
||||
#!/bin/bash -e
|
||||
|
||||
# process microwatt verilog
|
||||
|
||||
FILE_IN=microwatt_asic.v
|
||||
FILE_OUT=microwatt_asic_processed.v
|
||||
|
||||
# Rename top level
|
||||
sed 's/toplevel/microwatt/' < $FILE_IN > $FILE_OUT
|
||||
|
||||
# Add power to all macros, and route power in microwatt down to them
|
||||
caravel/insert_power.py --verilog=$FILE_OUT --parent-power=vccd1 --parent-ground=vssd1 --power=vccd1 --ground=vssd1 --module=microwatt --module=core_0_4_1_4_4_1_2_2_452bf2882a9b5f1c06340d5059c72dbd8af3bf8b --module=execute1_0_47ec8d98366433dc002e7721c9e37d5067547937 --module=multiply_2 --module=soc_4096_100000000_0_0_4_0_4_0_4_1_4_4_1_2_2_32_529beb193518cdd5546a21170d32ebafc9f9cb89 --module=icache_64_8_4_1_4_12_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f --module=dcache_64_4_1_2_2_12_0 --module=cache_ram_5_64_1489f923c4dca729178b3e3233458550d8dddf29 --module=main_bram_64_9_4096_a75adb9e07879fb6c63b494abe06e3f9a6bb2ed9 --module=register_file_0_3f29546453678b855931c174a97d6c0894b8f546 --module=wishbone_bram_wrapper_4096_a75adb9e07879fb6c63b494abe06e3f9a6bb2ed9 --module=fpu > ${FILE_OUT}.tmp1
|
||||
|
||||
# Hard macros use VPWR/VGND
|
||||
caravel/insert_power.py --verilog=${FILE_OUT}.tmp1 --parent-power=vccd1 --parent-ground=vssd1 --power=VPWR --ground=VGND --module=Microwatt_FP_DFFRFile --module=multiply_add_64x64 --module=RAM32_1RW1R --module=RAM512 > ${FILE_OUT}.tmp2
|
||||
|
||||
mv ${FILE_OUT}.tmp2 ${FILE_OUT}
|
||||
rm ${FILE_OUT}.tmp1
|
||||
|
||||
# Add defines
|
||||
sed -i '1 a\
|
||||
\
|
||||
/* JTAG */\
|
||||
`include "tap_top.v"\
|
||||
\
|
||||
/* UART */\
|
||||
`include "raminfr.v"\
|
||||
`include "uart_receiver.v"\
|
||||
`include "uart_rfifo.v"\
|
||||
`include "uart_tfifo.v"\
|
||||
`include "uart_transmitter.v"\
|
||||
`include "uart_defines.v"\
|
||||
`include "uart_regs.v"\
|
||||
`include "uart_sync_flops.v"\
|
||||
`include "uart_wb.v"\
|
||||
`include "uart_top.v"\
|
||||
`include "simplebus_host.v"' $FILE_OUT
|
||||
@ -0,0 +1,302 @@
|
||||
-- JTAG to DMI interface, based on the Xilinx version
|
||||
--
|
||||
-- DMI bus
|
||||
--
|
||||
-- req : ____/------------\_____
|
||||
-- addr: xxxx< >xxxxx, based on the Xilinx version
|
||||
-- dout: xxxx< >xxxxx
|
||||
-- wr : xxxx< >xxxxx
|
||||
-- din : xxxxxxxxxxxx< >xxx
|
||||
-- ack : ____________/------\___
|
||||
--
|
||||
-- * addr/dout set along with req, can be latched on same cycle by slave
|
||||
-- * ack & din remain up until req is dropped by master, the slave must
|
||||
-- provide a stable output on din on reads during that time.
|
||||
-- * req remains low at until at least one sysclk after ack seen down.
|
||||
--
|
||||
-- JTAG (tck) DMI (sys_clk)
|
||||
--
|
||||
-- * jtag_req = 1
|
||||
-- (jtag_req_0) *
|
||||
-- (jtag_req_1) -> * dmi_req = 1 >
|
||||
-- *.../...
|
||||
-- * dmi_ack = 1 <
|
||||
-- * (dmi_ack_0)
|
||||
-- * <- (dmi_ack_1)
|
||||
-- * jtag_req = 0 (and latch dmi_din)
|
||||
-- (jtag_req_0) *
|
||||
-- (jtag_req_1) -> * dmi_req = 0 >
|
||||
-- * dmi_ack = 0 <
|
||||
-- * (dmi_ack_0)
|
||||
-- * <- (dmi_ack_1)
|
||||
--
|
||||
-- jtag_req can go back to 1 when jtag_rsp_1 is 0
|
||||
--
|
||||
-- Questions/TODO:
|
||||
-- - I use 2 flip fops for sync, is that enough ?
|
||||
-- - I treat the jtag_trst as an async reset, is that necessary ?
|
||||
-- - Dbl check reset situation since we have two different resets
|
||||
-- each only resetting part of the logic...
|
||||
-- - Look at optionally removing the synchronizer on the ack path,
|
||||
-- assuming JTAG is always slow enough that ack will have been
|
||||
-- stable long enough by the time CAPTURE comes in.
|
||||
-- - We could avoid the latched request by not shifting while a
|
||||
-- request is in progress (and force TDO to 1 to return a busy
|
||||
-- status).
|
||||
--
|
||||
-- WARNING: This isn't the real DMI JTAG protocol (at least not yet).
|
||||
-- a command while busy will be ignored. A response of "11"
|
||||
-- means the previous command is still going, try again.
|
||||
-- As such We don't implement the DMI "error" status, and
|
||||
-- we don't implement DTMCS yet... This may still all change
|
||||
-- but for now it's easier that way as the real DMI protocol
|
||||
-- requires for a command to work properly that enough TCK
|
||||
-- are sent while IDLE and I'm having trouble getting that
|
||||
-- working with UrJtag and the Xilinx BSCAN2 for now.
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.math_real.all;
|
||||
|
||||
library work;
|
||||
use work.wishbone_types.all;
|
||||
|
||||
entity dmi_dtm_jtag is
|
||||
generic(ABITS : INTEGER:=8;
|
||||
DBITS : INTEGER:=32);
|
||||
|
||||
port(sys_clk : in std_ulogic;
|
||||
sys_reset : in std_ulogic;
|
||||
dmi_addr : out std_ulogic_vector(ABITS - 1 downto 0);
|
||||
dmi_din : in std_ulogic_vector(DBITS - 1 downto 0);
|
||||
dmi_dout : out std_ulogic_vector(DBITS - 1 downto 0);
|
||||
dmi_req : out std_ulogic;
|
||||
dmi_wr : out std_ulogic;
|
||||
dmi_ack : in std_ulogic;
|
||||
-- dmi_err : in std_ulogic TODO: Add error response
|
||||
jtag_tck : in std_ulogic;
|
||||
jtag_tdi : in std_ulogic;
|
||||
jtag_tms : in std_ulogic;
|
||||
jtag_trst : in std_ulogic;
|
||||
jtag_tdo : out std_ulogic
|
||||
);
|
||||
end entity dmi_dtm_jtag;
|
||||
|
||||
architecture behaviour of dmi_dtm_jtag is
|
||||
|
||||
-- Signals coming out of the JTAG TAP controller
|
||||
signal capture : std_ulogic;
|
||||
signal update : std_ulogic;
|
||||
signal sel : std_ulogic;
|
||||
signal shift : std_ulogic;
|
||||
signal tdi : std_ulogic;
|
||||
signal tdo : std_ulogic;
|
||||
|
||||
-- ** JTAG clock domain **
|
||||
|
||||
-- Shift register
|
||||
signal shiftr : std_ulogic_vector(ABITS + DBITS + 1 downto 0);
|
||||
|
||||
-- Latched request
|
||||
signal request : std_ulogic_vector(ABITS + DBITS + 1 downto 0);
|
||||
|
||||
-- A request is present
|
||||
signal jtag_req : std_ulogic;
|
||||
|
||||
-- Synchronizer for jtag_rsp (sys clk -> jtag_tck)
|
||||
signal dmi_ack_0 : std_ulogic;
|
||||
signal dmi_ack_1 : std_ulogic;
|
||||
|
||||
-- ** sys clock domain **
|
||||
|
||||
-- Synchronizer for jtag_req (jtag clk -> sys clk)
|
||||
signal jtag_req_0 : std_ulogic;
|
||||
signal jtag_req_1 : std_ulogic;
|
||||
|
||||
-- ** combination signals
|
||||
signal jtag_bsy : std_ulogic;
|
||||
signal op_valid : std_ulogic;
|
||||
signal rsp_op : std_ulogic_vector(1 downto 0);
|
||||
|
||||
-- ** Constants **
|
||||
constant DMI_REQ_NOP : std_ulogic_vector(1 downto 0) := "00";
|
||||
constant DMI_REQ_RD : std_ulogic_vector(1 downto 0) := "01";
|
||||
constant DMI_REQ_WR : std_ulogic_vector(1 downto 0) := "10";
|
||||
constant DMI_RSP_OK : std_ulogic_vector(1 downto 0) := "00";
|
||||
constant DMI_RSP_BSY : std_ulogic_vector(1 downto 0) := "11";
|
||||
|
||||
attribute ASYNC_REG : string;
|
||||
attribute ASYNC_REG of jtag_req_0: signal is "TRUE";
|
||||
attribute ASYNC_REG of jtag_req_1: signal is "TRUE";
|
||||
attribute ASYNC_REG of dmi_ack_0: signal is "TRUE";
|
||||
attribute ASYNC_REG of dmi_ack_1: signal is "TRUE";
|
||||
|
||||
component tap_top port (
|
||||
-- JTAG pads
|
||||
tms_pad_i : in std_ulogic;
|
||||
tck_pad_i : in std_ulogic;
|
||||
trst_pad_i : in std_ulogic;
|
||||
tdi_pad_i : in std_ulogic;
|
||||
tdo_pad_o : out std_ulogic;
|
||||
tdo_padoe_o : out std_ulogic;
|
||||
|
||||
-- TAP states
|
||||
shift_dr_o : out std_ulogic;
|
||||
pause_dr_o : out std_ulogic;
|
||||
update_dr_o : out std_ulogic;
|
||||
capture_dr_o : out std_ulogic;
|
||||
|
||||
-- Select signals for boundary scan or mbist
|
||||
extest_select_o : out std_ulogic;
|
||||
sample_preload_select_o : out std_ulogic;
|
||||
mbist_select_o : out std_ulogic;
|
||||
debug_select_o : out std_ulogic;
|
||||
|
||||
-- TDO signal that is connected to TDI of sub-modules.
|
||||
tdo_o : out std_ulogic;
|
||||
|
||||
-- TDI signals from sub-modules
|
||||
debug_tdi_i : in std_ulogic;
|
||||
bs_chain_tdi_i : in std_ulogic;
|
||||
mbist_tdi_i : in std_ulogic
|
||||
);
|
||||
end component;
|
||||
|
||||
begin
|
||||
tap_top0 : tap_top
|
||||
port map (
|
||||
tms_pad_i => jtag_tms,
|
||||
tck_pad_i => jtag_tck,
|
||||
trst_pad_i => jtag_trst,
|
||||
tdi_pad_i => jtag_tdi,
|
||||
tdo_pad_o => jtag_tdo,
|
||||
tdo_padoe_o => open, -- what to do with this?
|
||||
|
||||
shift_dr_o => shift,
|
||||
pause_dr_o => open, -- what to do with this?
|
||||
update_dr_o => update,
|
||||
capture_dr_o => capture,
|
||||
|
||||
-- connect boundary scan and mbist?
|
||||
extest_select_o => open,
|
||||
sample_preload_select_o => open,
|
||||
mbist_select_o => open,
|
||||
debug_select_o => sel,
|
||||
|
||||
tdo_o => tdi,
|
||||
debug_tdi_i => tdo,
|
||||
bs_chain_tdi_i => '0',
|
||||
mbist_tdi_i => '0'
|
||||
);
|
||||
|
||||
-- dmi_req synchronization
|
||||
dmi_req_sync : process(sys_clk)
|
||||
begin
|
||||
-- sys_reset is synchronous
|
||||
if rising_edge(sys_clk) then
|
||||
if (sys_reset = '1') then
|
||||
jtag_req_0 <= '0';
|
||||
jtag_req_1 <= '0';
|
||||
else
|
||||
jtag_req_0 <= jtag_req;
|
||||
jtag_req_1 <= jtag_req_0;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
dmi_req <= jtag_req_1;
|
||||
|
||||
-- dmi_ack synchronization
|
||||
dmi_ack_sync: process(jtag_tck, jtag_trst)
|
||||
begin
|
||||
-- jtag_trst is async (see comments)
|
||||
if jtag_trst = '1' then
|
||||
dmi_ack_0 <= '0';
|
||||
dmi_ack_1 <= '0';
|
||||
elsif rising_edge(jtag_tck) then
|
||||
dmi_ack_0 <= dmi_ack;
|
||||
dmi_ack_1 <= dmi_ack_0;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- jtag_bsy indicates whether we can start a new request, we can when
|
||||
-- we aren't already processing one (jtag_req) and the synchronized ack
|
||||
-- of the previous one is 0.
|
||||
--
|
||||
jtag_bsy <= jtag_req or dmi_ack_1;
|
||||
|
||||
-- decode request type in shift register
|
||||
with shiftr(1 downto 0) select op_valid <=
|
||||
'1' when DMI_REQ_RD,
|
||||
'1' when DMI_REQ_WR,
|
||||
'0' when others;
|
||||
|
||||
-- encode response op
|
||||
rsp_op <= DMI_RSP_BSY when jtag_bsy = '1' else DMI_RSP_OK;
|
||||
|
||||
-- Some DMI out signals are directly driven from the request register
|
||||
dmi_addr <= request(ABITS + DBITS + 1 downto DBITS + 2);
|
||||
dmi_dout <= request(DBITS + 1 downto 2);
|
||||
dmi_wr <= '1' when request(1 downto 0) = DMI_REQ_WR else '0';
|
||||
|
||||
-- TDO is wired to shift register bit 0
|
||||
tdo <= shiftr(0);
|
||||
|
||||
-- Main state machine. Handles shift registers, request latch and
|
||||
-- jtag_req latch. Could be split into 3 processes but it's probably
|
||||
-- not worthwhile.
|
||||
--
|
||||
shifter: process(jtag_tck, jtag_trst, sys_reset)
|
||||
begin
|
||||
if jtag_trst = '1' or sys_reset = '1' then
|
||||
shiftr <= (others => '0');
|
||||
jtag_req <= '0';
|
||||
request <= (others => '0');
|
||||
elsif rising_edge(jtag_tck) then
|
||||
|
||||
-- Handle jtag "commands" when sel is 1
|
||||
if sel = '1' then
|
||||
-- Shift state, rotate the register
|
||||
if shift = '1' then
|
||||
shiftr <= tdi & shiftr(ABITS + DBITS + 1 downto 1);
|
||||
end if;
|
||||
|
||||
-- Update state (trigger)
|
||||
--
|
||||
-- Latch the request if we aren't already processing one and
|
||||
-- it has a valid command opcode.
|
||||
--
|
||||
if update = '1' and op_valid = '1' then
|
||||
if jtag_bsy = '0' then
|
||||
request <= shiftr;
|
||||
jtag_req <= '1';
|
||||
end if;
|
||||
-- Set the shift register "op" to "busy". This will prevent
|
||||
-- us from re-starting the command on the next update if
|
||||
-- the command completes before that.
|
||||
shiftr(1 downto 0) <= DMI_RSP_BSY;
|
||||
end if;
|
||||
|
||||
-- Request completion.
|
||||
--
|
||||
-- Capture the response data for reads and clear request flag.
|
||||
--
|
||||
-- Note: We clear req (and thus dmi_req) here which relies on tck
|
||||
-- ticking and sel set. This means we are stuck with dmi_req up if
|
||||
-- the jtag interface stops. Slaves must be resilient to this.
|
||||
--
|
||||
if jtag_req = '1' and dmi_ack_1 = '1' then
|
||||
jtag_req <= '0';
|
||||
if request(1 downto 0) = DMI_REQ_RD then
|
||||
request(DBITS + 1 downto 2) <= dmi_din;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Capture state, grab latch content with updated status
|
||||
if capture = '1' then
|
||||
shiftr <= request(ABITS + DBITS + 1 downto 2) & rsp_op;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end architecture behaviour;
|
||||
Binary file not shown.
Binary file not shown.
@ -1,27 +1,13 @@
|
||||
SECTIONS
|
||||
{
|
||||
. = 0;
|
||||
_start = .;
|
||||
. = 0;
|
||||
.head : {
|
||||
KEEP(*(.head))
|
||||
}
|
||||
. = 0x1000;
|
||||
.text : { *(.text) *(.text.*) *(.rodata) *(.rodata.*) }
|
||||
. = 0x1800;
|
||||
.data : { *(.data) *(.data.*) *(.got) *(.toc) }
|
||||
. = ALIGN(0x80);
|
||||
__bss_start = .;
|
||||
.bss : {
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.common)
|
||||
*(.bss.*)
|
||||
}
|
||||
. = ALIGN(0x80);
|
||||
__bss_end = .;
|
||||
. = . + 0x2000;
|
||||
__stack_top = .;
|
||||
}
|
||||
. = 0x400;
|
||||
.text : { *(.text) }
|
||||
. = 0xA00;
|
||||
.data : { *(.data) }
|
||||
.bss : { *(.bss) }
|
||||
}
|
||||
|
||||
@ -0,0 +1,636 @@
|
||||
//////////////////////////////////////////////////////////////////////
|
||||
//// ////
|
||||
//// tap_top.v ////
|
||||
//// ////
|
||||
//// ////
|
||||
//// This file is part of the JTAG Test Access Port (TAP) ////
|
||||
//// http://www.opencores.org/projects/jtag/ ////
|
||||
//// ////
|
||||
//// Author(s): ////
|
||||
//// Igor Mohor (igorm@opencores.org) ////
|
||||
//// ////
|
||||
//// ////
|
||||
//// All additional information is avaliable in the README.txt ////
|
||||
//// file. ////
|
||||
//// ////
|
||||
//////////////////////////////////////////////////////////////////////
|
||||
//// ////
|
||||
//// Copyright (C) 2000 - 2003 Authors ////
|
||||
//// ////
|
||||
//// This source file may be used and distributed without ////
|
||||
//// restriction provided that this copyright statement is not ////
|
||||
//// removed from the file and that any derivative work contains ////
|
||||
//// the original copyright notice and the associated disclaimer. ////
|
||||
//// ////
|
||||
//// This source file is free software; you can redistribute it ////
|
||||
//// and/or modify it under the terms of the GNU Lesser General ////
|
||||
//// Public License as published by the Free Software Foundation; ////
|
||||
//// either version 2.1 of the License, or (at your option) any ////
|
||||
//// later version. ////
|
||||
//// ////
|
||||
//// This source is distributed in the hope that it will be ////
|
||||
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
||||
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
||||
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
||||
//// details. ////
|
||||
//// ////
|
||||
//// You should have received a copy of the GNU Lesser General ////
|
||||
//// Public License along with this source; if not, download it ////
|
||||
//// from http://www.opencores.org/lgpl.shtml ////
|
||||
//// ////
|
||||
//////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// CVS Revision History
|
||||
//
|
||||
// $Log: not supported by cvs2svn $
|
||||
// Revision 1.5 2004/01/18 09:27:39 simons
|
||||
// Blocking non blocking assignmenst fixed.
|
||||
//
|
||||
// Revision 1.4 2004/01/17 17:37:44 mohor
|
||||
// capture_dr_o added to ports.
|
||||
//
|
||||
// Revision 1.3 2004/01/14 13:50:56 mohor
|
||||
// 5 consecutive TMS=1 causes reset of TAP.
|
||||
//
|
||||
// Revision 1.2 2004/01/08 10:29:44 mohor
|
||||
// Control signals for tdo_pad_o mux are changed to negedge.
|
||||
//
|
||||
// Revision 1.1 2003/12/23 14:52:14 mohor
|
||||
// Directory structure changed. New version of TAP.
|
||||
//
|
||||
// Revision 1.10 2003/10/23 18:08:01 mohor
|
||||
// MBIST chain connection fixed.
|
||||
//
|
||||
// Revision 1.9 2003/10/23 16:17:02 mohor
|
||||
// CRC logic changed.
|
||||
//
|
||||
// Revision 1.8 2003/10/21 09:48:31 simons
|
||||
// Mbist support added.
|
||||
//
|
||||
// Revision 1.7 2002/11/06 14:30:10 mohor
|
||||
// Trst active high. Inverted on higher layer.
|
||||
//
|
||||
// Revision 1.6 2002/04/22 12:55:56 mohor
|
||||
// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
|
||||
//
|
||||
// Revision 1.5 2002/03/26 14:23:38 mohor
|
||||
// Signal tdo_padoe_o changed back to tdo_padoen_o.
|
||||
//
|
||||
// Revision 1.4 2002/03/25 13:16:15 mohor
|
||||
// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
|
||||
// not named correctly.
|
||||
//
|
||||
// Revision 1.3 2002/03/12 14:30:05 mohor
|
||||
// Few outputs for boundary scan chain added.
|
||||
//
|
||||
// Revision 1.2 2002/03/12 10:31:53 mohor
|
||||
// tap_top and dbg_top modules are put into two separate modules. tap_top
|
||||
// contains only tap state machine and related logic. dbg_top contains all
|
||||
// logic necessery for debugging.
|
||||
//
|
||||
// Revision 1.1 2002/03/08 15:28:16 mohor
|
||||
// Structure changed. Hooks for jtag chain added.
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
|
||||
// Top module
|
||||
module tap_top #(parameter
|
||||
IDCODE_VALUE = 32'h14d57049,
|
||||
IR_LENGTH = 6)
|
||||
(
|
||||
// JTAG pads
|
||||
tms_pad_i,
|
||||
tck_pad_i,
|
||||
trst_pad_i,
|
||||
tdi_pad_i,
|
||||
tdo_pad_o,
|
||||
tdo_padoe_o,
|
||||
|
||||
// TAP states
|
||||
shift_dr_o,
|
||||
pause_dr_o,
|
||||
update_dr_o,
|
||||
capture_dr_o,
|
||||
|
||||
// Select signals for boundary scan or mbist
|
||||
extest_select_o,
|
||||
sample_preload_select_o,
|
||||
mbist_select_o,
|
||||
debug_select_o,
|
||||
|
||||
// TDO signal that is connected to TDI of sub-modules.
|
||||
tdo_o,
|
||||
|
||||
// TDI signals from sub-modules
|
||||
debug_tdi_i, // from debug module
|
||||
bs_chain_tdi_i, // from Boundary Scan Chain
|
||||
mbist_tdi_i // from Mbist Chain
|
||||
);
|
||||
|
||||
|
||||
// JTAG pins
|
||||
input tms_pad_i; // JTAG test mode select pad
|
||||
input tck_pad_i; // JTAG test clock pad
|
||||
input trst_pad_i; // JTAG test reset pad
|
||||
input tdi_pad_i; // JTAG test data input pad
|
||||
output tdo_pad_o; // JTAG test data output pad
|
||||
output tdo_padoe_o; // Output enable for JTAG test data output pad
|
||||
|
||||
// TAP states
|
||||
output shift_dr_o;
|
||||
output pause_dr_o;
|
||||
output update_dr_o;
|
||||
output capture_dr_o;
|
||||
|
||||
// Select signals for boundary scan or mbist
|
||||
output extest_select_o;
|
||||
output sample_preload_select_o;
|
||||
output mbist_select_o;
|
||||
output debug_select_o;
|
||||
|
||||
// TDO signal that is connected to TDI of sub-modules.
|
||||
output tdo_o;
|
||||
|
||||
// TDI signals from sub-modules
|
||||
input debug_tdi_i; // from debug module
|
||||
input bs_chain_tdi_i; // from Boundary Scan Chain
|
||||
input mbist_tdi_i; // from Mbist Chain
|
||||
|
||||
//Internal constants
|
||||
localparam EXTEST = 6'b000000;
|
||||
localparam SAMPLE_PRELOAD = 6'b000001;
|
||||
localparam IDCODE = 6'b001001;
|
||||
localparam DEBUG = 6'b000011;
|
||||
localparam MBIST = 6'b001010;
|
||||
localparam BYPASS = 6'b111111;
|
||||
|
||||
// Registers
|
||||
reg test_logic_reset;
|
||||
reg run_test_idle;
|
||||
reg select_dr_scan;
|
||||
reg capture_dr;
|
||||
reg shift_dr;
|
||||
reg exit1_dr;
|
||||
reg pause_dr;
|
||||
reg exit2_dr;
|
||||
reg update_dr;
|
||||
reg select_ir_scan;
|
||||
reg capture_ir;
|
||||
reg shift_ir, shift_ir_neg;
|
||||
reg exit1_ir;
|
||||
reg pause_ir;
|
||||
reg exit2_ir;
|
||||
reg update_ir;
|
||||
reg extest_select;
|
||||
reg sample_preload_select;
|
||||
reg idcode_select;
|
||||
reg mbist_select;
|
||||
reg debug_select;
|
||||
reg bypass_select;
|
||||
reg tdo_pad_o;
|
||||
reg tdo_padoe_o;
|
||||
reg tms_q1, tms_q2, tms_q3, tms_q4;
|
||||
wire tms_reset;
|
||||
|
||||
assign tdo_o = tdi_pad_i;
|
||||
assign shift_dr_o = shift_dr;
|
||||
assign pause_dr_o = pause_dr;
|
||||
assign update_dr_o = update_dr;
|
||||
assign capture_dr_o = capture_dr;
|
||||
|
||||
assign extest_select_o = extest_select;
|
||||
assign sample_preload_select_o = sample_preload_select;
|
||||
assign mbist_select_o = mbist_select;
|
||||
assign debug_select_o = debug_select;
|
||||
|
||||
|
||||
always @ (posedge tck_pad_i)
|
||||
begin
|
||||
tms_q1 <= tms_pad_i;
|
||||
tms_q2 <= tms_q1;
|
||||
tms_q3 <= tms_q2;
|
||||
tms_q4 <= tms_q3;
|
||||
end
|
||||
|
||||
|
||||
assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i; // 5 consecutive TMS=1 causes reset
|
||||
|
||||
|
||||
/**********************************************************************************
|
||||
* *
|
||||
* TAP State Machine: Fully JTAG compliant *
|
||||
* *
|
||||
**********************************************************************************/
|
||||
|
||||
// test_logic_reset state
|
||||
always @ (posedge tck_pad_i or posedge trst_pad_i)
|
||||
begin
|
||||
if(trst_pad_i)
|
||||
test_logic_reset<= 1'b1;
|
||||
else if (tms_reset)
|
||||
test_logic_reset<= 1'b1;
|
||||
else
|
||||
begin
|
||||
if(tms_pad_i & (test_logic_reset | select_ir_scan))
|
||||
test_logic_reset<= 1'b1;
|
||||
else
|
||||
test_logic_reset<= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// run_test_idle state
|
||||
always @ (posedge tck_pad_i or posedge trst_pad_i)
|
||||
begin
|
||||
if(trst_pad_i)
|
||||
run_test_idle<= 1'b0;
|
||||
else if (tms_reset)
|
||||
run_test_idle<= 1'b0;
|
||||
else
|
||||
if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
|
||||
run_test_idle<= 1'b1;
|
||||
else
|
||||
run_test_idle<= 1'b0;
|
||||
end
|
||||
|
||||
// select_dr_scan state
|
||||
always @ (posedge tck_pad_i or posedge trst_pad_i)
|
||||
begin
|
||||
if(trst_pad_i)
|
||||
select_dr_scan<= 1'b0;
|
||||
else if (tms_reset)
|
||||
select_dr_scan<= 1'b0;
|
||||
else
|
||||
if(tms_pad_i & (run_test_idle | update_dr | update_ir))
|
||||
select_dr_scan<= 1'b1;
|
||||
else
|
||||
select_dr_scan<= 1'b0;
|
||||
end
|
||||
|
||||
// capture_dr state
|
||||
always @ (posedge tck_pad_i or posedge trst_pad_i)
|
||||
begin
|
||||
if(trst_pad_i)
|
||||
capture_dr<= 1'b0;
|
||||
else if (tms_reset)
|
||||
capture_dr<= 1'b0;
|
||||
else
|
||||
if(~tms_pad_i & select_dr_scan)
|
||||
capture_dr<= 1'b1;
|
||||
else
|
||||
capture_dr<= 1'b0;
|
||||
end
|
||||
|
||||
// shift_dr state
|
||||
always @ (posedge tck_pad_i or posedge trst_pad_i)
|
||||
begin
|
||||
if(trst_pad_i)
|
||||
shift_dr<= 1'b0;
|
||||
else if (tms_reset)
|
||||
shift_dr<= 1'b0;
|
||||
else
|
||||
if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
|
||||
shift_dr<= 1'b1;
|
||||
else
|
||||
shift_dr<= 1'b0;
|
||||
end
|
||||
|
||||
// exit1_dr state
|
||||
always @ (posedge tck_pad_i or posedge trst_pad_i)
|
||||
begin
|
||||
if(trst_pad_i)
|
||||
exit1_dr<= 1'b0;
|
||||
else if (tms_reset)
|
||||
exit1_dr<= 1'b0;
|
||||
else
|
||||
if(tms_pad_i & (capture_dr | shift_dr))
|
||||
exit1_dr<= 1'b1;
|
||||
else
|
||||
exit1_dr<= 1'b0;
|
||||
end
|
||||
|
||||
// pause_dr state
|
||||
always @ (posedge tck_pad_i or posedge trst_pad_i)
|
||||
begin
|
||||
if(trst_pad_i)
|
||||
pause_dr<= 1'b0;
|
||||
else if (tms_reset)
|
||||
pause_dr<= 1'b0;
|
||||
else
|
||||
if(~tms_pad_i & (exit1_dr | pause_dr))
|
||||
pause_dr<= 1'b1;
|
||||
else
|
||||
pause_dr<= 1'b0;
|
||||
end
|
||||
|
||||
// exit2_dr state
|
||||
always @ (posedge tck_pad_i or posedge trst_pad_i)
|
||||
begin
|
||||
if(trst_pad_i)
|
||||
exit2_dr<= 1'b0;
|
||||
else if (tms_reset)
|
||||
exit2_dr<= 1'b0;
|
||||
else
|
||||
if(tms_pad_i & pause_dr)
|
||||
exit2_dr<= 1'b1;
|
||||
else
|
||||
exit2_dr<= 1'b0;
|
||||
end
|
||||
|
||||
// update_dr state
|
||||
always @ (posedge tck_pad_i or posedge trst_pad_i)
|
||||
begin
|
||||
if(trst_pad_i)
|
||||
update_dr<= 1'b0;
|
||||
else if (tms_reset)
|
||||
update_dr<= 1'b0;
|
||||
else
|
||||
if(tms_pad_i & (exit1_dr | exit2_dr))
|
||||
update_dr<= 1'b1;
|
||||
else
|
||||
update_dr<= 1'b0;
|
||||
end
|
||||
|
||||
// select_ir_scan state
|
||||
always @ (posedge tck_pad_i or posedge trst_pad_i)
|
||||
begin
|
||||
if(trst_pad_i)
|
||||
select_ir_scan<= 1'b0;
|
||||
else if (tms_reset)
|
||||
select_ir_scan<= 1'b0;
|
||||
else
|
||||
if(tms_pad_i & select_dr_scan)
|
||||
select_ir_scan<= 1'b1;
|
||||
else
|
||||
select_ir_scan<= 1'b0;
|
||||
end
|
||||
|
||||
// capture_ir state
|
||||
always @ (posedge tck_pad_i or posedge trst_pad_i)
|
||||
begin
|
||||
if(trst_pad_i)
|
||||
capture_ir<= 1'b0;
|
||||
else if (tms_reset)
|
||||
capture_ir<= 1'b0;
|
||||
else
|
||||
if(~tms_pad_i & select_ir_scan)
|
||||
capture_ir<= 1'b1;
|
||||
else
|
||||
capture_ir<= 1'b0;
|
||||
end
|
||||
|
||||
// shift_ir state
|
||||
always @ (posedge tck_pad_i or posedge trst_pad_i)
|
||||
begin
|
||||
if(trst_pad_i)
|
||||
shift_ir<= 1'b0;
|
||||
else if (tms_reset)
|
||||
shift_ir<= 1'b0;
|
||||
else
|
||||
if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
|
||||
shift_ir<= 1'b1;
|
||||
else
|
||||
shift_ir<= 1'b0;
|
||||
end
|
||||
|
||||
// exit1_ir state
|
||||
always @ (posedge tck_pad_i or posedge trst_pad_i)
|
||||
begin
|
||||
if(trst_pad_i)
|
||||
exit1_ir<= 1'b0;
|
||||
else if (tms_reset)
|
||||
exit1_ir<= 1'b0;
|
||||
else
|
||||
if(tms_pad_i & (capture_ir | shift_ir))
|
||||
exit1_ir<= 1'b1;
|
||||
else
|
||||
exit1_ir<= 1'b0;
|
||||
end
|
||||
|
||||
// pause_ir state
|
||||
always @ (posedge tck_pad_i or posedge trst_pad_i)
|
||||
begin
|
||||
if(trst_pad_i)
|
||||
pause_ir<= 1'b0;
|
||||
else if (tms_reset)
|
||||
pause_ir<= 1'b0;
|
||||
else
|
||||
if(~tms_pad_i & (exit1_ir | pause_ir))
|
||||
pause_ir<= 1'b1;
|
||||
else
|
||||
pause_ir<= 1'b0;
|
||||
end
|
||||
|
||||
// exit2_ir state
|
||||
always @ (posedge tck_pad_i or posedge trst_pad_i)
|
||||
begin
|
||||
if(trst_pad_i)
|
||||
exit2_ir<= 1'b0;
|
||||
else if (tms_reset)
|
||||
exit2_ir<= 1'b0;
|
||||
else
|
||||
if(tms_pad_i & pause_ir)
|
||||
exit2_ir<= 1'b1;
|
||||
else
|
||||
exit2_ir<= 1'b0;
|
||||
end
|
||||
|
||||
// update_ir state
|
||||
always @ (posedge tck_pad_i or posedge trst_pad_i)
|
||||
begin
|
||||
if(trst_pad_i)
|
||||
update_ir<= 1'b0;
|
||||
else if (tms_reset)
|
||||
update_ir<= 1'b0;
|
||||
else
|
||||
if(tms_pad_i & (exit1_ir | exit2_ir))
|
||||
update_ir<= 1'b1;
|
||||
else
|
||||
update_ir<= 1'b0;
|
||||
end
|
||||
|
||||
/**********************************************************************************
|
||||
* *
|
||||
* End: TAP State Machine *
|
||||
* *
|
||||
**********************************************************************************/
|
||||
|
||||
|
||||
|
||||
/**********************************************************************************
|
||||
* *
|
||||
* jtag_ir: JTAG Instruction Register *
|
||||
* *
|
||||
**********************************************************************************/
|
||||
reg [IR_LENGTH-1:0] jtag_ir; // Instruction register
|
||||
reg [IR_LENGTH-1:0] latched_jtag_ir, latched_jtag_ir_neg;
|
||||
reg instruction_tdo;
|
||||
|
||||
always @ (posedge tck_pad_i or posedge trst_pad_i)
|
||||
begin
|
||||
if(trst_pad_i)
|
||||
jtag_ir[IR_LENGTH-1:0] <= {IR_LENGTH{1'b0}};
|
||||
else if(capture_ir)
|
||||
jtag_ir <= 6'b000101; // This value is fixed for easier fault detection
|
||||
else if(shift_ir)
|
||||
jtag_ir[IR_LENGTH-1:0] <= {tdi_pad_i, jtag_ir[IR_LENGTH-1:1]};
|
||||
end
|
||||
|
||||
always @ (negedge tck_pad_i)
|
||||
begin
|
||||
instruction_tdo <= jtag_ir[0];
|
||||
end
|
||||
/**********************************************************************************
|
||||
* *
|
||||
* End: jtag_ir *
|
||||
* *
|
||||
**********************************************************************************/
|
||||
|
||||
|
||||
|
||||
/**********************************************************************************
|
||||
* *
|
||||
* idcode logic *
|
||||
* *
|
||||
**********************************************************************************/
|
||||
reg [31:0] idcode_reg;
|
||||
reg idcode_tdo;
|
||||
|
||||
always @ (posedge tck_pad_i)
|
||||
begin
|
||||
if(idcode_select & shift_dr)
|
||||
idcode_reg <= {tdi_pad_i, idcode_reg[31:1]};
|
||||
else
|
||||
idcode_reg <= IDCODE_VALUE;
|
||||
end
|
||||
|
||||
always @ (negedge tck_pad_i)
|
||||
begin
|
||||
idcode_tdo <= idcode_reg[0];
|
||||
end
|
||||
/**********************************************************************************
|
||||
* *
|
||||
* End: idcode logic *
|
||||
* *
|
||||
**********************************************************************************/
|
||||
|
||||
|
||||
/**********************************************************************************
|
||||
* *
|
||||
* Bypass logic *
|
||||
* *
|
||||
**********************************************************************************/
|
||||
reg bypassed_tdo;
|
||||
reg bypass_reg;
|
||||
|
||||
always @ (posedge tck_pad_i or posedge trst_pad_i)
|
||||
begin
|
||||
if (trst_pad_i)
|
||||
bypass_reg<= 1'b0;
|
||||
else if(shift_dr)
|
||||
bypass_reg<= tdi_pad_i;
|
||||
end
|
||||
|
||||
always @ (negedge tck_pad_i)
|
||||
begin
|
||||
bypassed_tdo <= bypass_reg;
|
||||
end
|
||||
/**********************************************************************************
|
||||
* *
|
||||
* End: Bypass logic *
|
||||
* *
|
||||
**********************************************************************************/
|
||||
|
||||
|
||||
/**********************************************************************************
|
||||
* *
|
||||
* Activating Instructions *
|
||||
* *
|
||||
**********************************************************************************/
|
||||
// Updating jtag_ir (Instruction Register)
|
||||
always @ (posedge tck_pad_i or posedge trst_pad_i)
|
||||
begin
|
||||
if(trst_pad_i)
|
||||
latched_jtag_ir <= IDCODE; // IDCODE selected after reset
|
||||
else if (tms_reset)
|
||||
latched_jtag_ir <= IDCODE; // IDCODE selected after reset
|
||||
else if(update_ir)
|
||||
latched_jtag_ir <= jtag_ir;
|
||||
end
|
||||
|
||||
/**********************************************************************************
|
||||
* *
|
||||
* End: Activating Instructions *
|
||||
* *
|
||||
**********************************************************************************/
|
||||
|
||||
|
||||
// Updating jtag_ir (Instruction Register)
|
||||
always @ (latched_jtag_ir)
|
||||
begin
|
||||
extest_select = 1'b0;
|
||||
sample_preload_select = 1'b0;
|
||||
idcode_select = 1'b0;
|
||||
mbist_select = 1'b0;
|
||||
debug_select = 1'b0;
|
||||
bypass_select = 1'b0;
|
||||
|
||||
case(latched_jtag_ir) /* synthesis parallel_case */
|
||||
EXTEST: extest_select = 1'b1; // External test
|
||||
SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
|
||||
IDCODE: idcode_select = 1'b1; // ID Code
|
||||
MBIST: mbist_select = 1'b1; // Mbist test
|
||||
DEBUG: debug_select = 1'b1; // Debug
|
||||
BYPASS: bypass_select = 1'b1; // BYPASS
|
||||
default: bypass_select = 1'b1; // BYPASS
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
|
||||
/**********************************************************************************
|
||||
* *
|
||||
* Multiplexing TDO data *
|
||||
* *
|
||||
**********************************************************************************/
|
||||
always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or
|
||||
debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or
|
||||
bypassed_tdo)
|
||||
begin
|
||||
if(shift_ir_neg)
|
||||
tdo_pad_o = instruction_tdo;
|
||||
else
|
||||
begin
|
||||
case(latched_jtag_ir_neg) // synthesis parallel_case
|
||||
IDCODE: tdo_pad_o = idcode_tdo; // Reading ID code
|
||||
DEBUG: tdo_pad_o = debug_tdi_i; // Debug
|
||||
SAMPLE_PRELOAD: tdo_pad_o = bs_chain_tdi_i; // Sampling/Preloading
|
||||
EXTEST: tdo_pad_o = bs_chain_tdi_i; // External test
|
||||
MBIST: tdo_pad_o = mbist_tdi_i; // Mbist test
|
||||
default: tdo_pad_o = bypassed_tdo; // BYPASS instruction
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// Tristate control for tdo_pad_o pin
|
||||
always @ (negedge tck_pad_i)
|
||||
begin
|
||||
tdo_padoe_o <= shift_ir | shift_dr | (pause_dr & debug_select);
|
||||
end
|
||||
/**********************************************************************************
|
||||
* *
|
||||
* End: Multiplexing TDO data *
|
||||
* *
|
||||
**********************************************************************************/
|
||||
|
||||
|
||||
always @ (negedge tck_pad_i)
|
||||
begin
|
||||
shift_ir_neg <= shift_ir;
|
||||
latched_jtag_ir_neg <= latched_jtag_ir;
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,196 @@
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <unistd.h>
|
||||
#include <poll.h>
|
||||
#include <signal.h>
|
||||
#include <fcntl.h>
|
||||
#include <stdint.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/socket.h>
|
||||
#include <netinet/in.h>
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
/* XXX Make that some parameter */
|
||||
#define TCP_PORT 13245
|
||||
|
||||
static int fd = -1;
|
||||
static int cfd = -1;
|
||||
|
||||
static void open_socket(void)
|
||||
{
|
||||
struct sockaddr_in addr;
|
||||
int opt, rc, flags;
|
||||
|
||||
if (fd >= 0 || fd < -1)
|
||||
return;
|
||||
|
||||
signal(SIGPIPE, SIG_IGN);
|
||||
fd = socket(AF_INET, SOCK_STREAM, 0);
|
||||
if (fd < 0) {
|
||||
fprintf(stderr, "Failed to open debug socket\r\n");
|
||||
goto fail;
|
||||
}
|
||||
|
||||
rc = 0;
|
||||
flags = fcntl(fd, F_GETFL);
|
||||
if (flags >= 0)
|
||||
rc = fcntl(fd, F_SETFL, flags | O_NONBLOCK);
|
||||
if (flags < 0 || rc < 0) {
|
||||
fprintf(stderr, "Failed to configure debug socket\r\n");
|
||||
}
|
||||
|
||||
memset(&addr, 0, sizeof(addr));
|
||||
addr.sin_family = AF_INET;
|
||||
addr.sin_port = htons(TCP_PORT);
|
||||
addr.sin_addr.s_addr = htonl(INADDR_ANY);
|
||||
opt = 1;
|
||||
setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, &opt, sizeof(opt));
|
||||
rc = bind(fd, (struct sockaddr *)&addr, sizeof(addr));
|
||||
if (rc < 0) {
|
||||
fprintf(stderr, "Failed to bind debug socket\r\n");
|
||||
goto fail;
|
||||
}
|
||||
rc = listen(fd,1);
|
||||
if (rc < 0) {
|
||||
fprintf(stderr, "Failed to listen to debug socket\r\n");
|
||||
goto fail;
|
||||
}
|
||||
#ifdef DEBUG
|
||||
fprintf(stdout, "Debug socket ready\r\n");
|
||||
#endif
|
||||
return;
|
||||
fail:
|
||||
if (fd >= 0)
|
||||
close(fd);
|
||||
fd = -2;
|
||||
}
|
||||
|
||||
static void check_connection(void)
|
||||
{
|
||||
struct sockaddr_in addr;
|
||||
socklen_t addr_len = sizeof(addr);
|
||||
|
||||
cfd = accept(fd, (struct sockaddr *)&addr, &addr_len);
|
||||
if (cfd < 0)
|
||||
return;
|
||||
#ifdef DEBUG
|
||||
fprintf(stdout, "Debug client connected\r\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
static bool read_one_byte(char *c)
|
||||
{
|
||||
struct pollfd fdset[1];
|
||||
int rc;
|
||||
|
||||
if (fd == -1)
|
||||
open_socket();
|
||||
if (fd < 0)
|
||||
return false;
|
||||
if (cfd < 0)
|
||||
check_connection();
|
||||
if (cfd < 0)
|
||||
return false;
|
||||
|
||||
memset(fdset, 0, sizeof(fdset));
|
||||
fdset[0].fd = cfd;
|
||||
fdset[0].events = POLLIN;
|
||||
rc = poll(fdset, 1, 0);
|
||||
if (rc <= 0)
|
||||
return false;
|
||||
rc = read(cfd, c, 1);
|
||||
if (rc != 1) {
|
||||
#ifdef DEBUG
|
||||
fprintf(stdout, "Debug read error, assuming client disconnected !\r\n");
|
||||
#endif
|
||||
close(cfd);
|
||||
cfd = -1;
|
||||
return false;
|
||||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
fprintf(stdout, "Got message: %c\n", *c);
|
||||
#endif
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static void write_one_byte(char c)
|
||||
{
|
||||
int rc;
|
||||
|
||||
#ifdef DEBUG
|
||||
fprintf(stdout, "Sending message: %c\r\n", c);
|
||||
#endif
|
||||
|
||||
rc = write(cfd, &c, 1);
|
||||
if (rc != 1) {
|
||||
#ifdef DEBUG
|
||||
fprintf(stdout, "JTAG write error, disconnecting\r\n");
|
||||
#endif
|
||||
close(cfd);
|
||||
cfd = -1;
|
||||
}
|
||||
}
|
||||
|
||||
struct jtag_in {
|
||||
uint8_t tck;
|
||||
uint8_t tms;
|
||||
uint8_t tdi;
|
||||
uint8_t trst;
|
||||
};
|
||||
|
||||
static struct jtag_in jtag_in;
|
||||
|
||||
struct jtag_in jtag_one_cycle(uint8_t tdo)
|
||||
{
|
||||
char c;
|
||||
|
||||
if (read_one_byte(&c) == false)
|
||||
goto out;
|
||||
|
||||
// Write request
|
||||
if ((c >= '0') && (c <= '7')) {
|
||||
uint8_t val = c - '0';
|
||||
|
||||
jtag_in.tck = (val >> 2) & 1;
|
||||
jtag_in.tms = (val >> 1) & 1;
|
||||
jtag_in.tdi = (val >> 0) & 1;
|
||||
|
||||
goto out;
|
||||
}
|
||||
|
||||
// Reset request
|
||||
if ((c >= 'r') && (c <= 'u')) {
|
||||
uint8_t val = c - 'r';
|
||||
|
||||
jtag_in.trst = (val >> 1) & 1;
|
||||
}
|
||||
|
||||
switch (c) {
|
||||
case 'B': // Blink on
|
||||
case 'b': // Blink off
|
||||
goto out;
|
||||
|
||||
case 'R': // Read request
|
||||
write_one_byte(tdo + '0');
|
||||
goto out;
|
||||
|
||||
case 'Q': // Quit request
|
||||
#ifdef DEBUG
|
||||
fprintf(stdout, "Disconnecting JTAG\r\n");
|
||||
#endif
|
||||
close(cfd);
|
||||
cfd = -1;
|
||||
goto out;
|
||||
|
||||
default:
|
||||
fprintf(stderr, "Unknown JTAG command %c\r\n", c);
|
||||
}
|
||||
|
||||
out:
|
||||
return jtag_in;
|
||||
}
|
||||
Loading…
Reference in New Issue