matthew1kalasky3
/
microwatt
forked from cores/microwatt
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
1,091 Commits
31 Branches
0 Tags
65 MiB
master
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from 'faab169307'
${ noResults }
Commit Graph

2 Commits (faab169307285af3e74b6b817b2fa0de480346d3)

Author SHA1 Message Date
Raptor Engineering Development Team fcb783a0fb Extend LiteDRAM VHDL wrapper to allow more than one clock line 
This is necessary for the upcoming Arctic Tern system enablement,
since Arctic Tern uses two DRAM devices and a separate clock line
is routed to each device.  LiteX handles this behavior correctly,
therefore we assume other hardware exists that uses a similar
DRAM clock design.

Updates from Mikey to fix some compile issues.

Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
 3 years ago
Benjamin Herrenschmidt dbb137437c acorn: Add support for the Acorn CLE 215+ 
This is a NiteFury based PCIe M2 form-factor board originally
used for mining. It contains a speed grade 2 Artix 7 200T,
1GB of DDR3 and 32MB of flash.

The serial port is routed to pin 2 (RX) and 3 (TX) of the P2
connector (pin 1 is GND).

Note: Only 16MB of flash is currently usable until code is added
to configure the flash controller to use 4-bytes address commands
on that part.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago