matthew1kalasky3
/
microwatt
forked from cores/microwatt
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
1,116 Commits
31 Branches
0 Tags
65 MiB
master
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from 'ee5e3778ed'
${ noResults }
Commit Graph

1116 Commits (ee5e3778edc1d6234195d746236e3804f682a9cf)
 

Author SHA1 Message Date
Benjamin Herrenschmidt 554b753172 Add jtag support in simulation via a socket 
This adds a local socket that can be used to communicate with
the debug tool (which will be committed separately) and generates
the JTAG signals.

We generate the low level JTAG signals, thus directly driving the
simulated BSCANE2, and the Xilinx DTM

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 6 years ago
Benjamin Herrenschmidt ad14a41d80 Add DMI address decoder 
And prepare signals for core DMI support

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 6 years ago
Benjamin Herrenschmidt b46f81fae4 Wishbone debug module 
This adds a debug module off the DMI (debug) bus which can act as a
wishbone master to generate read and write cycles.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 6 years ago
Benjamin Herrenschmidt ee52fd4d80 Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs 
This adds a simple bus that can be mastered from an external
system via JTAG, which will be used to hookup various debug
modules.

It's loosely based on the RiscV model (hence the DMI name).

The module currently only supports hooking up to a Xilinx BSCANE2
but it shouldn't be too hard to adapt it to support different TAPs
if necessary.

The JTAG protocol proper is not exactly the RiscV one at this point,
though I might still change it.

This comes with some sim variants of Xilinx BSCANE2 and BUFG and a
test bench.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 6 years ago
Benjamin Herrenschmidt 1206dfe18c Use a 3 way WB arbiter and cleanup fpga toplevel 
The 3rd master is currently unused, it will host the WB debug module.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 6 years ago
Anton Blanchard 6571b13308
Merge pull request #66 from antonblanchard/reformat-4 
More reformatting
 6 years ago
Anton Blanchard 7e7010c304 Reformat crhelpers, and remove some stale code 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard ae42370d24 Reformat helpers 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 9ff86a62f5 Reformat insn_helpers 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard c5d327cebf
Merge pull request #65 from antonblanchard/loadstore-opt 
A small loadstore optimisation, and some reformatting
 6 years ago
Anton Blanchard 687051ecbb Reformat loadstore1 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 6e442e07a5 Reformat loadstore2 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard e1a71e4545 loads don't do both byte reversal and sign extension 
Give the synthesis tools a clue that we don't need to do both byte reversal
and sign extension.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 4df05e0598
Merge pull request #64 from antonblanchard/reformat-3 
Reformat some more files
 6 years ago
Anton Blanchard 48f4dcece8
Merge pull request #63 from antonblanchard/multiply-cleanup 
Multiply cleanup
 6 years ago
Anton Blanchard df1165bdfc Reformat wishbone code 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 06392e7eaa Reformat glibc_random 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 1d5e8c2eb4 Reformat simple_ram_behavioural 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard fd9e971b2c Reformat sim_console 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 28e6d343dc Reformat multiply_tb 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard fc10935797 Reformat execute2 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 4d0afa3a6d Reformat CR file 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 4d9b2a1165 Reformat register file 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 8dd97fbe7f Reformat multiply code 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 99dd4de54e Don't use VHDL 2008 condition operator in multiply 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 550b2b8608
Merge pull request #62 from antonblanchard/byte-reverse-store-opt 
Move byte reversal of stores to first cycle
 6 years ago
Anton Blanchard 135805d2ac
Merge pull request #61 from antonblanchard/execute-cleanup 
execute1 no longer needs sim_console
 6 years ago
Anton Blanchard a061924a78 Move byte reversal of stores to first cycle 
We are seeing some timing issues with the second cycle of loadstore,
and  we aren't doing much in the first cycle, so move it here.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 6d85920068 execute1 no longer needs sim_console 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard a4c8dd860a
Merge pull request #60 from antonblanchard/testbenches 
Add a few more test benches
 6 years ago
Anton Blanchard 1b6eef2a5d Fix multiply_tb 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 1e3e16e500 Add an icache testbench 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard d573748da0
Merge pull request #56 from antonblanchard/writeback-fix3 
Remove cycle in writeback
 6 years ago
Anton Blanchard 152261fac8 Remove cycle in writeback 
The pipeline had a cycle in writeback. Writeback is pretty
simple and unlikely to be a bottleneck, so lets remove it.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 7bb88d5321
Merge pull request #59 from antonblanchard/trap-decode 
Fix make check
 6 years ago
Anton Blanchard f5a5b91736
Merge pull request #58 from antonblanchard/decode2-assert 
Fix spurious outstanding assert
 6 years ago
Anton Blanchard 427effdaa9 Fix make check 
We need to finish support for all the trap instructions, but for now
we at least need a decode entry for tw, so we know to stall until the
previous instruction completes. Some of our test cases were failing
because the trap executed before the previous instruction completed.

All these trap instructions need to be resolved at completion, not
in execute.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard d813ffb748 Fix spurious outstanding assert 
Check it in the sequential process, not the combinatorial one.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 30aa16d8f3
Merge pull request #57 from antonblanchard/add-nop 
Add a decode for the nop instruction
 6 years ago
Anton Blanchard 9867fb6149 Add a decode for the nop instruction 
We want these to go out without any GPR dependencies, so add
a specific entry in decode for them.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 85062793b1
Merge pull request #55 from antonblanchard/fetch-fix 
Add a default value for RESET_ADDRESS
 6 years ago
Anton Blanchard d52046104f Add a default value for RESET_ADDRESS 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 71e45a82ee
Merge pull request #51 from antonblanchard/writeback-fix 
Some writeback updates
 6 years ago
Anton Blanchard e69e79d8af Reformat writeback.vhdl 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 50a361a5dc Exit if we try to write more than one GPR or CR in a cycle 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard ab34c48392
Merge pull request #50 from antonblanchard/decode1-opt 
No need to gate nia or insn in decode1
 6 years ago
Anton Blanchard acdb2ea157 No need to gate nia or insn in decode1 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 0e6861e5db
Merge pull request #49 from antonblanchard/icache-2 
Add a simple direct mapped icache
 6 years ago
Anton Blanchard 89849a6856 Add a simple direct mapped icache 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 6cbf456388 SOC memory wishbone should clear ACK regardless of STB 
The memory wishbone doesn't clear ACK and move the state machine on
until STB is de-asserted. This seems like it isn't compliant with
the spec and results in a maximum throughput of 1 transfer every
3 cycles.

Fixing this improves the situation to one transfer every 2 cycles.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago