Commit Graph

3 Commits (d5e3be80fecb47435dcae4d6da514e0cc8e32b72)

Author SHA1 Message Date
Anton Blanchard c2577b5446 Add ASIC target
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years ago
Anton Blanchard 5249d633cf Move register stage from after RAM to before RAM
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years ago
Anton Blanchard 8ecb30da05 Add arrays for ASIC flow
Add VHDL wrappers and verilog behaviourals for the cache_ram,
register_file and main_bram arrays.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years ago