microwatt

Author	SHA1	Message	Date
Benjamin Herrenschmidt	d21ef5836d	Pass wishbone record to bram memory module (And rename it to mw_soc_memory). This makes soc.vhdl simpler and provides the same interface as the simulated memory, which will help when sharing soc.vhdl with sim later Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	1d66e1f981	Rework wishbone slave address decoding Don't make it synchronous, no latches Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	c97b080d8c	Move wishbone arbiter out of the core Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	310a56c076	Re-indent and reformat soc.vhdl Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	a69a93b466	Split FPGA toplevel from soc This will be useful when we start needing different toplevels for different boards. We keep the reset and clock generators in the toplevel as they will eventually be taken over by litedram when we integrate it, and they are more likely to change on different system types. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago