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fpu-init
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divider-init
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alt-reset-address
log2ceil-issue
fpu-constant
asic-3
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1 Commits (cc35c499289d0a936517896627e0be209514c5ee)

Author SHA1 Message Date
Michael Neuling 5aaa63ee3b Add PLL for ECP5 device 
Means we can synthesize at 40Mhz (where we currently make timing) and
our UART still works at 115200 baud.

Tested working hello world unmodified with ECP5 eval board. Orange
Crab is updated but is untested.

Signed-off-by: Michael Neuling <mikey@neuling.org>
 4 years ago